src/gallium/drivers/radeonsi/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include "pipe/p_screen.h"
  29 #include "util/u_format.h"
  30 #include "util/u_format_s3tc.h"
  31 #include "util/u_math.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_memory.h"
  34 #include "pipebuffer/pb_buffer.h"
  35 #include "radeonsi_pipe.h"
  36 #include "r600_resource.h"
  37 #include "sid.h"
  38
  39 /* Copy from a full GPU texture to a transfer's staging one. */
  40 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  41 {
  42         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  43         struct pipe_resource *texture = transfer->resource;
  44
  45         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  46                                 0, 0, 0, 0, texture, transfer->level,
  47                                 &transfer->box);
  48 }
  49
  50
  51 /* Copy from a transfer's staging texture to a full GPU one. */
  52 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  53 {
  54         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  55         struct pipe_resource *texture = transfer->resource;
  56         struct pipe_box sbox;
  57
  58         sbox.x = sbox.y = sbox.z = 0;
  59         sbox.width = transfer->box.width;
  60         sbox.height = transfer->box.height;
  61         /* XXX that might be wrong */
  62         sbox.depth = 1;
  63         ctx->resource_copy_region(ctx, texture, transfer->level,
  64                                   transfer->box.x, transfer->box.y, transfer->box.z,
  65                                   rtransfer->staging_texture,
  66                                   0, &sbox);
  67 }
  68
  69 static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  70                                         unsigned level, unsigned layer)
  71 {
  72         return rtex->surface.level[level].offset +
  73                layer * rtex->surface.level[level].slice_size;
  74 }
  75
  76 static int r600_init_surface(struct r600_screen *rscreen,
  77                              struct radeon_surface *surface,
  78                              const struct pipe_resource *ptex,
  79                              unsigned array_mode,
  80                              bool is_flushed_depth)
  81 {
  82         const struct util_format_description *desc =
  83                 util_format_description(ptex->format);
  84         bool is_depth, is_stencil;
  85
  86         is_depth = util_format_has_depth(desc);
  87         is_stencil = util_format_has_stencil(desc);
  88
  89         surface->npix_x = ptex->width0;
  90         surface->npix_y = ptex->height0;
  91         surface->npix_z = ptex->depth0;
  92         surface->blk_w = util_format_get_blockwidth(ptex->format);
  93         surface->blk_h = util_format_get_blockheight(ptex->format);
  94         surface->blk_d = 1;
  95         surface->array_size = 1;
  96         surface->last_level = ptex->last_level;
  97
  98         if (!is_flushed_depth &&
  99             ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
 100                 surface->bpe = 4; /* stencil is allocated separately on evergreen */
 101         } else {
 102                 surface->bpe = util_format_get_blocksize(ptex->format);
 103                 /* align byte per element on dword */
 104                 if (surface->bpe == 3) {
 105                         surface->bpe = 4;
 106                 }
 107         }
 108
 109         surface->nsamples = 1;
 110         surface->flags = 0;
 111         switch (array_mode) {
 112         case V_009910_ARRAY_1D_TILED_THIN1:
 113                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
 114                 break;
 115         case V_009910_ARRAY_2D_TILED_THIN1:
 116                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
 117                 break;
 118         case V_009910_ARRAY_LINEAR_ALIGNED:
 119                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
 120                 break;
 121         case V_009910_ARRAY_LINEAR_GENERAL:
 122         default:
 123                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
 124                 break;
 125         }
 126         switch (ptex->target) {
 127         case PIPE_TEXTURE_1D:
 128                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
 129                 break;
 130         case PIPE_TEXTURE_RECT:
 131         case PIPE_TEXTURE_2D:
 132                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
 133                 break;
 134         case PIPE_TEXTURE_3D:
 135                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
 136                 break;
 137         case PIPE_TEXTURE_1D_ARRAY:
 138                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
 139                 surface->array_size = ptex->array_size;
 140                 break;
 141         case PIPE_TEXTURE_2D_ARRAY:
 142                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
 143                 surface->array_size = ptex->array_size;
 144                 break;
 145         case PIPE_TEXTURE_CUBE:
 146                 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
 147                 break;
 148         case PIPE_BUFFER:
 149         default:
 150                 return -EINVAL;
 151         }
 152         if (ptex->bind & PIPE_BIND_SCANOUT) {
 153                 surface->flags |= RADEON_SURF_SCANOUT;
 154         }
 155
 156         if (!is_flushed_depth && is_depth) {
 157                 surface->flags |= RADEON_SURF_ZBUFFER;
 158
 159                 if (is_stencil) {
 160                         surface->flags |= RADEON_SURF_SBUFFER |
 161                                 RADEON_SURF_HAS_SBUFFER_MIPTREE;
 162                 }
 163         }
 164         return 0;
 165 }
 166
 167 static int r600_setup_surface(struct pipe_screen *screen,
 168                               struct r600_resource_texture *rtex,
 169                               unsigned array_mode,
 170                               unsigned pitch_in_bytes_override)
 171 {
 172         struct r600_screen *rscreen = (struct r600_screen*)screen;
 173         int r;
 174
 175         r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
 176         if (r) {
 177                 return r;
 178         }
 179         if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
 180                 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
 181                  * for those
 182                  */
 183                 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
 184                 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
 185                 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
 186                 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
 187                         rtex->surface.stencil_offset =
 188                         rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
 189                 }
 190         }
 191         return 0;
 192 }
 193
 194 /* Figure out whether u_blitter will fallback to a transfer operation.
 195  * If so, don't use a staging resource.
 196  */
 197 static boolean permit_hardware_blit(struct pipe_screen *screen,
 198                                         const struct pipe_resource *res)
 199 {
 200         unsigned bind;
 201
 202         if (util_format_is_depth_or_stencil(res->format))
 203                 bind = PIPE_BIND_DEPTH_STENCIL;
 204         else
 205                 bind = PIPE_BIND_RENDER_TARGET;
 206
 207         /* hackaround for S3TC */
 208         if (util_format_is_compressed(res->format))
 209                 return TRUE;
 210
 211         if (!screen->is_format_supported(screen,
 212                                 res->format,
 213                                 res->target,
 214                                 res->nr_samples,
 215                                 bind))
 216                 return FALSE;
 217
 218         if (!screen->is_format_supported(screen,
 219                                 res->format,
 220                                 res->target,
 221                                 res->nr_samples,
 222                                 PIPE_BIND_SAMPLER_VIEW))
 223                 return FALSE;
 224
 225         switch (res->usage) {
 226         case PIPE_USAGE_STREAM:
 227         case PIPE_USAGE_STAGING:
 228                 return FALSE;
 229
 230         default:
 231                 return TRUE;
 232         }
 233 }
 234
 235 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 236                                         struct pipe_resource *ptex,
 237                                         struct winsys_handle *whandle)
 238 {
 239         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 240         struct si_resource *resource = &rtex->resource;
 241         struct radeon_surface *surface = &rtex->surface;
 242         struct r600_screen *rscreen = (struct r600_screen*)screen;
 243
 244         rscreen->ws->buffer_set_tiling(resource->buf,
 245                                        NULL,
 246                                        surface->level[0].mode >= RADEON_SURF_MODE_1D ?
 247                                        RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
 248                                        surface->level[0].mode >= RADEON_SURF_MODE_2D ?
 249                                        RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
 250                                        surface->bankw, surface->bankh,
 251                                        surface->tile_split,
 252                                        surface->stencil_tile_split,
 253                                        surface->mtilea,
 254                                        surface->level[0].pitch_bytes);
 255
 256         return rscreen->ws->buffer_get_handle(resource->buf,
 257                                               surface->level[0].pitch_bytes, whandle);
 258 }
 259
 260 static void r600_texture_destroy(struct pipe_screen *screen,
 261                                  struct pipe_resource *ptex)
 262 {
 263         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 264         struct si_resource *resource = &rtex->resource;
 265
 266         if (rtex->flushed_depth_texture)
 267                 si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL);
 268
 269         pb_reference(&resource->buf, NULL);
 270         FREE(rtex);
 271 }
 272
 273 static void *si_texture_transfer_map(struct pipe_context *ctx,
 274                                      struct pipe_resource *texture,
 275                                      unsigned level,
 276                                      unsigned usage,
 277                                      const struct pipe_box *box,
 278                                      struct pipe_transfer **ptransfer)
 279 {
 280         struct r600_context *rctx = (struct r600_context *)ctx;
 281         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 282         struct pipe_resource resource;
 283         struct r600_transfer *trans;
 284         int r;
 285         boolean use_staging_texture = FALSE;
 286         struct radeon_winsys_cs_handle *buf;
 287         enum pipe_format format = texture->format;
 288         unsigned offset = 0;
 289         char *map;
 290
 291         /* We cannot map a tiled texture directly because the data is
 292          * in a different order, therefore we do detiling using a blit.
 293          *
 294          * Also, use a temporary in GTT memory for read transfers, as
 295          * the CPU is much happier reading out of cached system memory
 296          * than uncached VRAM.
 297          */
 298         if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED &&
 299             rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR)
 300                 use_staging_texture = TRUE;
 301
 302         /* XXX: Use a staging texture for uploads if the underlying BO
 303          * is busy.  No interface for checking that currently? so do
 304          * it eagerly whenever the transfer doesn't require a readback
 305          * and might block.
 306          */
 307         if ((usage & PIPE_TRANSFER_WRITE) &&
 308                         !(usage & (PIPE_TRANSFER_READ |
 309                                         PIPE_TRANSFER_DONTBLOCK |
 310                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 311                 use_staging_texture = TRUE;
 312
 313         if (!permit_hardware_blit(ctx->screen, texture) ||
 314                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 315                 use_staging_texture = FALSE;
 316
 317         if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
 318                 return NULL;
 319
 320         trans = CALLOC_STRUCT(r600_transfer);
 321         if (trans == NULL)
 322                 return NULL;
 323         pipe_resource_reference(&trans->transfer.resource, texture);
 324         trans->transfer.level = level;
 325         trans->transfer.usage = usage;
 326         trans->transfer.box = *box;
 327         if (rtex->depth) {
 328                 /* XXX: only readback the rectangle which is being mapped?
 329                 */
 330                 /* XXX: when discard is true, no need to read back from depth texture
 331                 */
 332                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 333                 if (r < 0) {
 334                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 335                         pipe_resource_reference(&trans->transfer.resource, NULL);
 336                         FREE(trans);
 337                         return NULL;
 338                 }
 339                 trans->transfer.stride = rtex->flushed_depth_texture->surface.level[level].pitch_bytes;
 340                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 341         } else if (use_staging_texture) {
 342                 resource.target = PIPE_TEXTURE_2D;
 343                 resource.format = texture->format;
 344                 resource.width0 = box->width;
 345                 resource.height0 = box->height;
 346                 resource.depth0 = 1;
 347                 resource.array_size = 1;
 348                 resource.last_level = 0;
 349                 resource.nr_samples = 0;
 350                 resource.usage = PIPE_USAGE_STAGING;
 351                 resource.bind = 0;
 352                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 353                 /* For texture reading, the temporary (detiled) texture is used as
 354                  * a render target when blitting from a tiled texture. */
 355                 if (usage & PIPE_TRANSFER_READ) {
 356                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 357                 }
 358                 /* For texture writing, the temporary texture is used as a sampler
 359                  * when blitting into a tiled texture. */
 360                 if (usage & PIPE_TRANSFER_WRITE) {
 361                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 362                 }
 363                 /* Create the temporary texture. */
 364                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 365                 if (trans->staging_texture == NULL) {
 366                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 367                         pipe_resource_reference(&trans->transfer.resource, NULL);
 368                         FREE(trans);
 369                         return NULL;
 370                 }
 371
 372                 trans->transfer.stride = ((struct r600_resource_texture *)trans->staging_texture)
 373                                         ->surface.level[0].pitch_bytes;
 374                 if (usage & PIPE_TRANSFER_READ) {
 375                         r600_copy_to_staging_texture(ctx, trans);
 376                         /* Always referenced in the blit. */
 377                         radeonsi_flush(ctx, NULL, 0);
 378                 }
 379         } else {
 380                 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
 381                 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
 382                 trans->offset = r600_texture_get_offset(rtex, level, box->z);
 383         }
 384
 385         if (trans->staging_texture) {
 386                 buf = si_resource(trans->staging_texture)->cs_buf;
 387         } else {
 388                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 389
 390                 if (rtex->flushed_depth_texture)
 391                         buf = rtex->flushed_depth_texture->resource.cs_buf;
 392                 else
 393                         buf = si_resource(texture)->cs_buf;
 394
 395                 offset = trans->offset +
 396                         box->y / util_format_get_blockheight(format) * trans->transfer.stride +
 397                         box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 398         }
 399
 400         if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
 401                 pipe_resource_reference(&trans->staging_texture, NULL);
 402                 pipe_resource_reference(&trans->transfer.resource, NULL);
 403                 FREE(trans);
 404                 return NULL;
 405         }
 406
 407         *ptransfer = &trans->transfer;
 408         return map + offset;
 409 }
 410
 411 static void si_texture_transfer_unmap(struct pipe_context *ctx,
 412                                       struct pipe_transfer* transfer)
 413 {
 414         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 415         struct r600_context *rctx = (struct r600_context*)ctx;
 416         struct radeon_winsys_cs_handle *buf;
 417         struct pipe_resource *texture = transfer->resource;
 418         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 419
 420         if (rtransfer->staging_texture) {
 421                 buf = si_resource(rtransfer->staging_texture)->cs_buf;
 422         } else {
 423                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 424
 425                 if (rtex->flushed_depth_texture) {
 426                         buf = rtex->flushed_depth_texture->resource.cs_buf;
 427                 } else {
 428                         buf = si_resource(transfer->resource)->cs_buf;
 429                 }
 430         }
 431         rctx->ws->buffer_unmap(buf);
 432
 433         if (rtransfer->staging_texture) {
 434                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 435                         r600_copy_from_staging_texture(ctx, rtransfer);
 436                 }
 437                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 438         }
 439
 440         if (rtex->depth && !rtex->is_flushing_texture) {
 441                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 442                         r600_blit_push_depth(ctx, rtex);
 443         }
 444
 445         pipe_resource_reference(&transfer->resource, NULL);
 446         FREE(transfer);
 447 }
 448
 449 static const struct u_resource_vtbl r600_texture_vtbl =
 450 {
 451         r600_texture_get_handle,        /* get_handle */
 452         r600_texture_destroy,           /* resource_destroy */
 453         si_texture_transfer_map,        /* transfer_map */
 454         u_default_transfer_flush_region,/* transfer_flush_region */
 455         si_texture_transfer_unmap,      /* transfer_unmap */
 456         NULL    /* transfer_inline_write */
 457 };
 458
 459 static struct r600_resource_texture *
 460 r600_texture_create_object(struct pipe_screen *screen,
 461                            const struct pipe_resource *base,
 462                            unsigned array_mode,
 463                            unsigned pitch_in_bytes_override,
 464                            unsigned max_buffer_size,
 465                            struct pb_buffer *buf,
 466                            boolean alloc_bo,
 467                            struct radeon_surface *surface)
 468 {
 469         struct r600_resource_texture *rtex;
 470         struct si_resource *resource;
 471         struct r600_screen *rscreen = (struct r600_screen*)screen;
 472         int r;
 473
 474         rtex = CALLOC_STRUCT(r600_resource_texture);
 475         if (rtex == NULL)
 476                 return NULL;
 477
 478         resource = &rtex->resource;
 479         resource->b.b = *base;
 480         resource->b.vtbl = &r600_texture_vtbl;
 481         pipe_reference_init(&resource->b.b.reference, 1);
 482         resource->b.b.screen = screen;
 483         rtex->pitch_override = pitch_in_bytes_override;
 484         rtex->real_format = base->format;
 485
 486         /* only mark depth textures the HW can hit as depth textures */
 487         if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
 488                 rtex->depth = 1;
 489
 490         rtex->surface = *surface;
 491         r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
 492         if (r) {
 493                 FREE(rtex);
 494                 return NULL;
 495         }
 496
 497         /* Now create the backing buffer. */
 498         if (!buf && alloc_bo) {
 499                 unsigned base_align = rtex->surface.bo_alignment;
 500                 unsigned size = rtex->surface.bo_size;
 501
 502                 base_align = rtex->surface.bo_alignment;
 503                 if (!si_init_resource(rscreen, resource, size, base_align, base->bind, base->usage)) {
 504                         FREE(rtex);
 505                         return NULL;
 506                 }
 507         } else if (buf) {
 508                 resource->buf = buf;
 509                 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
 510                 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
 511         }
 512
 513         return rtex;
 514 }
 515
 516 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 517                                         const struct pipe_resource *templ)
 518 {
 519         struct r600_screen *rscreen = (struct r600_screen*)screen;
 520         struct radeon_surface surface;
 521         unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
 522         int r;
 523
 524 #if 0
 525         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 526             !(templ->bind & PIPE_BIND_SCANOUT)) {
 527                 if (permit_hardware_blit(screen, templ)) {
 528                         array_mode = V_009910_ARRAY_2D_TILED_THIN1;
 529                 }
 530         }
 531 #endif
 532
 533         r = r600_init_surface(rscreen, &surface, templ, array_mode,
 534                               templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
 535         if (r) {
 536                 return NULL;
 537         }
 538         r = rscreen->ws->surface_best(rscreen->ws, &surface);
 539         if (r) {
 540                 return NULL;
 541         }
 542         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 543                                                                   0, 0, NULL, TRUE, &surface);
 544 }
 545
 546 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 547                                                 struct pipe_resource *texture,
 548                                                 const struct pipe_surface *surf_tmpl)
 549 {
 550         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 551         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 552         unsigned level = surf_tmpl->u.tex.level;
 553
 554         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 555         if (surface == NULL)
 556                 return NULL;
 557         /* XXX no offset */
 558 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 559         pipe_reference_init(&surface->base.reference, 1);
 560         pipe_resource_reference(&surface->base.texture, texture);
 561         surface->base.context = pipe;
 562         surface->base.format = surf_tmpl->format;
 563         surface->base.width = rtex->surface.level[level].npix_x;
 564         surface->base.height = rtex->surface.level[level].npix_y;
 565         surface->base.texture = texture;
 566         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 567         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 568         surface->base.u.tex.level = level;
 569
 570         return &surface->base;
 571 }
 572
 573 static void r600_surface_destroy(struct pipe_context *pipe,
 574                                  struct pipe_surface *surface)
 575 {
 576         pipe_resource_reference(&surface->texture, NULL);
 577         FREE(surface);
 578 }
 579
 580 struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
 581                                              const struct pipe_resource *templ,
 582                                              struct winsys_handle *whandle)
 583 {
 584         struct r600_screen *rscreen = (struct r600_screen*)screen;
 585         struct pb_buffer *buf = NULL;
 586         unsigned stride = 0;
 587         unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
 588         enum radeon_bo_layout micro, macro;
 589         struct radeon_surface surface;
 590         int r;
 591
 592         /* Support only 2D textures without mipmaps */
 593         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 594               templ->depth0 != 1 || templ->last_level != 0)
 595                 return NULL;
 596
 597         buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
 598         if (!buf)
 599                 return NULL;
 600
 601         rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
 602                                        &surface.bankw, &surface.bankh,
 603                                        &surface.tile_split,
 604                                        &surface.stencil_tile_split,
 605                                        &surface.mtilea);
 606
 607         if (macro == RADEON_LAYOUT_TILED)
 608                 array_mode = V_009910_ARRAY_2D_TILED_THIN1;
 609         else if (micro == RADEON_LAYOUT_TILED)
 610                 array_mode = V_009910_ARRAY_1D_TILED_THIN1;
 611         else
 612                 array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
 613
 614         r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
 615         if (r) {
 616                 return NULL;
 617         }
 618         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 619                                                                   stride, 0, buf, FALSE, &surface);
 620 }
 621
 622 int r600_texture_depth_flush(struct pipe_context *ctx,
 623                              struct pipe_resource *texture, boolean just_create)
 624 {
 625         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 626         struct pipe_resource resource;
 627
 628         if (rtex->flushed_depth_texture)
 629                 goto out;
 630
 631         resource.target = texture->target;
 632         resource.format = texture->format;
 633         resource.width0 = texture->width0;
 634         resource.height0 = texture->height0;
 635         resource.depth0 = texture->depth0;
 636         resource.array_size = texture->array_size;
 637         resource.last_level = texture->last_level;
 638         resource.nr_samples = texture->nr_samples;
 639         resource.usage = PIPE_USAGE_DYNAMIC;
 640         resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
 641         resource.flags = R600_RESOURCE_FLAG_TRANSFER | R600_RESOURCE_FLAG_FLUSHED_DEPTH | texture->flags;
 642
 643         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 644         if (rtex->flushed_depth_texture == NULL) {
 645                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 646                 return -ENOMEM;
 647         }
 648
 649         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 650 out:
 651         if (just_create)
 652                 return 0;
 653
 654         /* XXX: only do this if the depth texture has actually changed:
 655          */
 656         si_blit_uncompress_depth(ctx, rtex);
 657         return 0;
 658 }
 659
 660 void si_init_surface_functions(struct r600_context *r600)
 661 {
 662         r600->context.create_surface = r600_create_surface;
 663         r600->context.surface_destroy = r600_surface_destroy;
 664 }