src/gallium/drivers/radeonsi/radeonsi_compute.c

   1 #include "util/u_memory.h"
   2
   3 #include "../radeon/r600_cs.h"
   4 #include "radeonsi_pipe.h"
   5 #include "radeonsi_shader.h"
   6
   7 #include "radeon_llvm_util.h"
   8
   9 #define MAX_GLOBAL_BUFFERS 20
  10
  11 struct si_pipe_compute {
  12         struct r600_context *ctx;
  13
  14         unsigned local_size;
  15         unsigned private_size;
  16         unsigned input_size;
  17         unsigned num_kernels;
  18         struct si_pipe_shader *kernels;
  19         unsigned num_user_sgprs;
  20
  21         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  22
  23 };
  24
  25 static void *radeonsi_create_compute_state(
  26         struct pipe_context *ctx,
  27         const struct pipe_compute_state *cso)
  28 {
  29         struct r600_context *rctx = (struct r600_context *)ctx;
  30         struct si_pipe_compute *program =
  31                                         CALLOC_STRUCT(si_pipe_compute);
  32         const struct pipe_llvm_program_header *header;
  33         const unsigned char *code;
  34         unsigned i;
  35
  36         header = cso->prog;
  37         code = cso->prog + sizeof(struct pipe_llvm_program_header);
  38
  39         program->ctx = rctx;
  40         program->local_size = cso->req_local_mem;
  41         program->private_size = cso->req_private_mem;
  42         program->input_size = cso->req_input_mem;
  43
  44         program->num_kernels = radeon_llvm_get_num_kernels(code,
  45                                                         header->num_bytes);
  46         program->kernels = CALLOC(sizeof(struct si_pipe_shader),
  47                                                         program->num_kernels);
  48         for (i = 0; i < program->num_kernels; i++) {
  49                 LLVMModuleRef mod = radeon_llvm_get_kernel_module(i, code,
  50                                                         header->num_bytes);
  51                 si_compile_llvm(rctx, &program->kernels[i], mod);
  52         }
  53
  54         return program;
  55 }
  56
  57 static void radeonsi_bind_compute_state(struct pipe_context *ctx, void *state)
  58 {
  59         struct r600_context *rctx = (struct r600_context*)ctx;
  60         rctx->cs_shader_state.program = (struct si_pipe_compute*)state;
  61 }
  62
  63 static void radeonsi_set_global_binding(
  64         struct pipe_context *ctx, unsigned first, unsigned n,
  65         struct pipe_resource **resources,
  66         uint32_t **handles)
  67 {
  68         unsigned i;
  69         struct r600_context *rctx = (struct r600_context*)ctx;
  70         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  71
  72         if (!resources) {
  73                 for (i = first; i < first + n; i++) {
  74                         program->global_buffers[i] = NULL;
  75                 }
  76                 return;
  77         }
  78
  79         for (i = first; i < first + n; i++) {
  80                 uint64_t va;
  81                 program->global_buffers[i] = resources[i];
  82                 va = r600_resource_va(ctx->screen, resources[i]);
  83                 memcpy(handles[i], &va, sizeof(va));
  84         }
  85 }
  86
  87 static void radeonsi_launch_grid(
  88                 struct pipe_context *ctx,
  89                 const uint *block_layout, const uint *grid_layout,
  90                 uint32_t pc, const void *input)
  91 {
  92         struct r600_context *rctx = (struct r600_context*)ctx;
  93         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  94         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
  95         struct r600_resource *kernel_args_buffer = NULL;
  96         unsigned kernel_args_size;
  97         unsigned num_work_size_bytes = 36;
  98         uint32_t kernel_args_offset = 0;
  99         uint32_t *kernel_args;
 100         uint64_t kernel_args_va;
 101         uint64_t shader_va;
 102         unsigned arg_user_sgpr_count = 2;
 103         unsigned i;
 104         struct si_pipe_shader *shader = &program->kernels[pc];
 105
 106         pm4->compute_pkt = true;
 107         si_cmd_context_control(pm4);
 108
 109         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 110         si_pm4_cmd_add(pm4, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) |
 111                             EVENT_INDEX(0x7) |
 112                             EVENT_WRITE_INV_L2);
 113         si_pm4_cmd_end(pm4, false);
 114
 115         si_pm4_inval_texture_cache(pm4);
 116         si_pm4_inval_shader_cache(pm4);
 117         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 118
 119         /* Upload the kernel arguments */
 120
 121         /* The extra num_work_size_bytes are for work group / work item size information */
 122         kernel_args_size = program->input_size + num_work_size_bytes;
 123         kernel_args = MALLOC(kernel_args_size);
 124         for (i = 0; i < 3; i++) {
 125                 kernel_args[i] = grid_layout[i];
 126                 kernel_args[i + 3] = grid_layout[i] * block_layout[i];
 127                 kernel_args[i + 6] = block_layout[i];
 128         }
 129
 130         memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
 131
 132         r600_upload_const_buffer(rctx, &kernel_args_buffer, (uint8_t*)kernel_args,
 133                                         kernel_args_size, &kernel_args_offset);
 134         kernel_args_va = r600_resource_va(ctx->screen,
 135                                 (struct pipe_resource*)kernel_args_buffer);
 136         kernel_args_va += kernel_args_offset;
 137
 138         si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ);
 139
 140         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 141         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 142
 143         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 144         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 145         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 146
 147         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 148                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 149         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 150                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 151         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 152                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 153
 154         /* Global buffers */
 155         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 156                 struct r600_resource *buffer =
 157                                 (struct r600_resource*)program->global_buffers[i];
 158                 if (!buffer) {
 159                         continue;
 160                 }
 161                 si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE);
 162         }
 163
 164         /* XXX: This should be:
 165          * (number of compute units) * 4 * (waves per simd) - 1 */
 166         si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
 167
 168         shader_va = r600_resource_va(ctx->screen, (void *)shader->bo);
 169         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
 170         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
 171         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 172
 173         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
 174                 /* We always use at least 3 VGPRS, these come from
 175                  * TIDIG_COMP_CNT.
 176                  * XXX: The compiler should account for this.
 177                  */
 178                 S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
 179                 /* We always use at least 4 + arg_user_sgpr_count.  The 4 extra
 180                  * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
 181                  * XXX: The compiler should account for this.
 182                  */
 183                 |  S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
 184                                         shader->num_sgprs)) - 1) / 8))
 185                 ;
 186
 187         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
 188                 S_00B84C_SCRATCH_EN(0)
 189                 | S_00B84C_USER_SGPR(arg_user_sgpr_count)
 190                 | S_00B84C_TGID_X_EN(1)
 191                 | S_00B84C_TGID_Y_EN(1)
 192                 | S_00B84C_TGID_Z_EN(1)
 193                 | S_00B84C_TG_SIZE_EN(1)
 194                 | S_00B84C_TIDIG_COMP_CNT(2)
 195                 | S_00B84C_LDS_SIZE(shader->lds_size)
 196                 | S_00B84C_EXCP_EN(0))
 197                 ;
 198         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 199
 200         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 201                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 202                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 203                 ;
 204
 205         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 206                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 207                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 208                 ;
 209
 210         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 211         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 212         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 213         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 214         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 215         si_pm4_cmd_end(pm4, false);
 216
 217         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 218         si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
 219         si_pm4_cmd_end(pm4, false);
 220
 221         si_pm4_inval_texture_cache(pm4);
 222         si_pm4_inval_shader_cache(pm4);
 223         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 224
 225         si_pm4_emit(rctx, pm4);
 226
 227 #if 0
 228         fprintf(stderr, "cdw: %i\n", rctx->cs->cdw);
 229         for (i = 0; i < rctx->cs->cdw; i++) {
 230                 fprintf(stderr, "%4i : 0x%08X\n", i, rctx->cs->buf[i]);
 231         }
 232 #endif
 233
 234         FREE(pm4);
 235         FREE(kernel_args);
 236 }
 237
 238
 239 static void si_delete_compute_state(struct pipe_context *ctx, void* state){}
 240 static void si_set_compute_resources(struct pipe_context * ctx_,
 241                 unsigned start, unsigned count,
 242                 struct pipe_surface ** surfaces) { }
 243
 244 void si_init_compute_functions(struct r600_context *rctx)
 245 {
 246         rctx->b.b.create_compute_state = radeonsi_create_compute_state;
 247         rctx->b.b.delete_compute_state = si_delete_compute_state;
 248         rctx->b.b.bind_compute_state = radeonsi_bind_compute_state;
 249 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 250         rctx->b.b.set_compute_resources = si_set_compute_resources;
 251         rctx->b.b.set_global_binding = radeonsi_set_global_binding;
 252         rctx->b.b.launch_grid = radeonsi_launch_grid;
 253 }