1 #include "util/u_memory.h"
3 #include "../radeon/r600_cs.h"
4 #include "radeonsi_pipe.h"
5 #include "radeonsi_shader.h"
7 #include "radeon_llvm_util.h"
9 #define MAX_GLOBAL_BUFFERS 20
11 struct si_pipe_compute
{
12 struct r600_context
*ctx
;
15 unsigned private_size
;
18 struct si_pipe_shader
*kernels
;
19 unsigned num_user_sgprs
;
21 struct pipe_resource
*global_buffers
[MAX_GLOBAL_BUFFERS
];
25 static void *radeonsi_create_compute_state(
26 struct pipe_context
*ctx
,
27 const struct pipe_compute_state
*cso
)
29 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
30 struct si_pipe_compute
*program
=
31 CALLOC_STRUCT(si_pipe_compute
);
32 const struct pipe_llvm_program_header
*header
;
33 const unsigned char *code
;
37 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
40 program
->local_size
= cso
->req_local_mem
;
41 program
->private_size
= cso
->req_private_mem
;
42 program
->input_size
= cso
->req_input_mem
;
44 program
->num_kernels
= radeon_llvm_get_num_kernels(code
,
46 program
->kernels
= CALLOC(sizeof(struct si_pipe_shader
),
47 program
->num_kernels
);
48 for (i
= 0; i
< program
->num_kernels
; i
++) {
49 LLVMModuleRef mod
= radeon_llvm_get_kernel_module(i
, code
,
51 si_compile_llvm(rctx
, &program
->kernels
[i
], mod
);
52 LLVMDisposeModule(mod
);
58 static void radeonsi_bind_compute_state(struct pipe_context
*ctx
, void *state
)
60 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
61 rctx
->cs_shader_state
.program
= (struct si_pipe_compute
*)state
;
64 static void radeonsi_set_global_binding(
65 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
66 struct pipe_resource
**resources
,
70 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
71 struct si_pipe_compute
*program
= rctx
->cs_shader_state
.program
;
74 for (i
= first
; i
< first
+ n
; i
++) {
75 program
->global_buffers
[i
] = NULL
;
80 for (i
= first
; i
< first
+ n
; i
++) {
82 program
->global_buffers
[i
] = resources
[i
];
83 va
= r600_resource_va(ctx
->screen
, resources
[i
]);
84 memcpy(handles
[i
], &va
, sizeof(va
));
88 static void radeonsi_launch_grid(
89 struct pipe_context
*ctx
,
90 const uint
*block_layout
, const uint
*grid_layout
,
91 uint32_t pc
, const void *input
)
93 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
94 struct si_pipe_compute
*program
= rctx
->cs_shader_state
.program
;
95 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
96 struct r600_resource
*kernel_args_buffer
= NULL
;
97 unsigned kernel_args_size
;
98 unsigned num_work_size_bytes
= 36;
99 uint32_t kernel_args_offset
= 0;
100 uint32_t *kernel_args
;
101 uint64_t kernel_args_va
;
103 unsigned arg_user_sgpr_count
= 2;
105 struct si_pipe_shader
*shader
= &program
->kernels
[pc
];
108 pm4
->compute_pkt
= true;
109 si_cmd_context_control(pm4
);
111 si_pm4_cmd_begin(pm4
, PKT3_EVENT_WRITE
);
112 si_pm4_cmd_add(pm4
, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH
) |
115 si_pm4_cmd_end(pm4
, false);
117 si_pm4_inval_texture_cache(pm4
);
118 si_pm4_inval_shader_cache(pm4
);
119 si_cmd_surface_sync(pm4
, pm4
->cp_coher_cntl
);
121 /* Upload the kernel arguments */
123 /* The extra num_work_size_bytes are for work group / work item size information */
124 kernel_args_size
= program
->input_size
+ num_work_size_bytes
;
125 kernel_args
= MALLOC(kernel_args_size
);
126 for (i
= 0; i
< 3; i
++) {
127 kernel_args
[i
] = grid_layout
[i
];
128 kernel_args
[i
+ 3] = grid_layout
[i
] * block_layout
[i
];
129 kernel_args
[i
+ 6] = block_layout
[i
];
132 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), input
, program
->input_size
);
134 r600_upload_const_buffer(rctx
, &kernel_args_buffer
, (uint8_t*)kernel_args
,
135 kernel_args_size
, &kernel_args_offset
);
136 kernel_args_va
= r600_resource_va(ctx
->screen
,
137 (struct pipe_resource
*)kernel_args_buffer
);
138 kernel_args_va
+= kernel_args_offset
;
140 si_pm4_add_bo(pm4
, kernel_args_buffer
, RADEON_USAGE_READ
);
142 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
, kernel_args_va
);
143 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) | S_008F04_STRIDE(0));
145 si_pm4_set_reg(pm4
, R_00B810_COMPUTE_START_X
, 0);
146 si_pm4_set_reg(pm4
, R_00B814_COMPUTE_START_Y
, 0);
147 si_pm4_set_reg(pm4
, R_00B818_COMPUTE_START_Z
, 0);
149 si_pm4_set_reg(pm4
, R_00B81C_COMPUTE_NUM_THREAD_X
,
150 S_00B81C_NUM_THREAD_FULL(block_layout
[0]));
151 si_pm4_set_reg(pm4
, R_00B820_COMPUTE_NUM_THREAD_Y
,
152 S_00B820_NUM_THREAD_FULL(block_layout
[1]));
153 si_pm4_set_reg(pm4
, R_00B824_COMPUTE_NUM_THREAD_Z
,
154 S_00B824_NUM_THREAD_FULL(block_layout
[2]));
157 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
158 struct r600_resource
*buffer
=
159 (struct r600_resource
*)program
->global_buffers
[i
];
163 si_pm4_add_bo(pm4
, buffer
, RADEON_USAGE_READWRITE
);
166 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
167 * and is now per pipe, so it should be handled in the
168 * kernel if we want to use something other than the default value,
169 * which is now 0x22f.
171 if (rctx
->b
.chip_class
<= SI
) {
172 /* XXX: This should be:
173 * (number of compute units) * 4 * (waves per simd) - 1 */
175 si_pm4_set_reg(pm4
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
176 0x190 /* Default value */);
179 shader_va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
180 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
);
181 si_pm4_set_reg(pm4
, R_00B830_COMPUTE_PGM_LO
, (shader_va
>> 8) & 0xffffffff);
182 si_pm4_set_reg(pm4
, R_00B834_COMPUTE_PGM_HI
, shader_va
>> 40);
184 si_pm4_set_reg(pm4
, R_00B848_COMPUTE_PGM_RSRC1
,
185 /* We always use at least 3 VGPRS, these come from
187 * XXX: The compiler should account for this.
189 S_00B848_VGPRS((MAX2(3, shader
->num_vgprs
) - 1) / 4)
190 /* We always use at least 4 + arg_user_sgpr_count. The 4 extra
191 * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
192 * XXX: The compiler should account for this.
194 | S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count
,
195 shader
->num_sgprs
)) - 1) / 8))
198 lds_blocks
= shader
->lds_size
;
199 /* XXX: We are over allocating LDS. For SI, the shader reports LDS in
200 * blocks of 256 bytes, so if there are 4 bytes lds allocated in
201 * the shader and 4 bytes allocated by the state tracker, then
202 * we will set LDS_SIZE to 512 bytes rather than 256.
204 if (rctx
->b
.chip_class
<= SI
) {
205 lds_blocks
+= align(program
->local_size
, 256) >> 8;
207 lds_blocks
+= align(program
->local_size
, 512) >> 9;
210 assert(lds_blocks
<= 0xFF);
212 si_pm4_set_reg(pm4
, R_00B84C_COMPUTE_PGM_RSRC2
,
213 S_00B84C_SCRATCH_EN(0)
214 | S_00B84C_USER_SGPR(arg_user_sgpr_count
)
215 | S_00B84C_TGID_X_EN(1)
216 | S_00B84C_TGID_Y_EN(1)
217 | S_00B84C_TGID_Z_EN(1)
218 | S_00B84C_TG_SIZE_EN(1)
219 | S_00B84C_TIDIG_COMP_CNT(2)
220 | S_00B84C_LDS_SIZE(lds_blocks
)
221 | S_00B84C_EXCP_EN(0))
223 si_pm4_set_reg(pm4
, R_00B854_COMPUTE_RESOURCE_LIMITS
, 0);
225 si_pm4_set_reg(pm4
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
,
226 S_00B858_SH0_CU_EN(0xffff /* Default value */)
227 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
230 si_pm4_set_reg(pm4
, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1
,
231 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
232 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
235 si_pm4_cmd_begin(pm4
, PKT3_DISPATCH_DIRECT
);
236 si_pm4_cmd_add(pm4
, grid_layout
[0]); /* Thread groups DIM_X */
237 si_pm4_cmd_add(pm4
, grid_layout
[1]); /* Thread groups DIM_Y */
238 si_pm4_cmd_add(pm4
, grid_layout
[2]); /* Thread gropus DIM_Z */
239 si_pm4_cmd_add(pm4
, 1); /* DISPATCH_INITIATOR */
240 si_pm4_cmd_end(pm4
, false);
242 si_pm4_cmd_begin(pm4
, PKT3_EVENT_WRITE
);
243 si_pm4_cmd_add(pm4
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(0x4)));
244 si_pm4_cmd_end(pm4
, false);
246 si_pm4_inval_texture_cache(pm4
);
247 si_pm4_inval_shader_cache(pm4
);
248 si_cmd_surface_sync(pm4
, pm4
->cp_coher_cntl
);
250 si_pm4_emit(rctx
, pm4
);
253 fprintf(stderr
, "cdw: %i\n", rctx
->cs
->cdw
);
254 for (i
= 0; i
< rctx
->cs
->cdw
; i
++) {
255 fprintf(stderr
, "%4i : 0x%08X\n", i
, rctx
->cs
->buf
[i
]);
264 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
265 struct si_pipe_compute
*program
= (struct si_pipe_compute
*)state
;
271 if (program
->kernels
) {
272 FREE(program
->kernels
);
275 //And then free the program itself.
279 static void si_set_compute_resources(struct pipe_context
* ctx_
,
280 unsigned start
, unsigned count
,
281 struct pipe_surface
** surfaces
) { }
283 void si_init_compute_functions(struct r600_context
*rctx
)
285 rctx
->b
.b
.create_compute_state
= radeonsi_create_compute_state
;
286 rctx
->b
.b
.delete_compute_state
= si_delete_compute_state
;
287 rctx
->b
.b
.bind_compute_state
= radeonsi_bind_compute_state
;
288 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
289 rctx
->b
.b
.set_compute_resources
= si_set_compute_resources
;
290 rctx
->b
.b
.set_global_binding
= radeonsi_set_global_binding
;
291 rctx
->b
.b
.launch_grid
= radeonsi_launch_grid
;