src/gallium/drivers/radeonsi/radeonsi_compute.c

   1 #include "util/u_memory.h"
   2
   3 #include "radeonsi_pipe.h"
   4 #include "radeonsi_shader.h"
   5
   6 #include "radeon_llvm_util.h"
   7
   8 #define MAX_GLOBAL_BUFFERS 20
   9
  10 struct si_pipe_compute {
  11         struct r600_context *ctx;
  12
  13         unsigned local_size;
  14         unsigned private_size;
  15         unsigned input_size;
  16         unsigned num_kernels;
  17         struct si_pipe_shader *kernels;
  18         unsigned num_user_sgprs;
  19
  20         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  21
  22 };
  23
  24 static void *radeonsi_create_compute_state(
  25         struct pipe_context *ctx,
  26         const struct pipe_compute_state *cso)
  27 {
  28         struct r600_context *rctx = (struct r600_context *)ctx;
  29         struct si_pipe_compute *program =
  30                                         CALLOC_STRUCT(si_pipe_compute);
  31         const struct pipe_llvm_program_header *header;
  32         const unsigned char *code;
  33         unsigned i;
  34
  35         header = cso->prog;
  36         code = cso->prog + sizeof(struct pipe_llvm_program_header);
  37
  38         program->ctx = rctx;
  39         program->local_size = cso->req_local_mem;
  40         program->private_size = cso->req_private_mem;
  41         program->input_size = cso->req_input_mem;
  42
  43         program->num_kernels = radeon_llvm_get_num_kernels(code,
  44                                                         header->num_bytes);
  45         program->kernels = CALLOC(sizeof(struct si_pipe_shader),
  46                                                         program->num_kernels);
  47         for (i = 0; i < program->num_kernels; i++) {
  48                 LLVMModuleRef mod = radeon_llvm_get_kernel_module(i, code,
  49                                                         header->num_bytes);
  50                 si_compile_llvm(rctx, &program->kernels[i], mod);
  51         }
  52
  53         return program;
  54 }
  55
  56 static void radeonsi_bind_compute_state(struct pipe_context *ctx, void *state)
  57 {
  58         struct r600_context *rctx = (struct r600_context*)ctx;
  59         rctx->cs_shader_state.program = (struct si_pipe_compute*)state;
  60 }
  61
  62 static void radeonsi_set_global_binding(
  63         struct pipe_context *ctx, unsigned first, unsigned n,
  64         struct pipe_resource **resources,
  65         uint32_t **handles)
  66 {
  67         unsigned i;
  68         struct r600_context *rctx = (struct r600_context*)ctx;
  69         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  70
  71         if (!resources) {
  72                 for (i = first; i < first + n; i++) {
  73                         program->global_buffers[i] = NULL;
  74                 }
  75                 return;
  76         }
  77
  78         for (i = first; i < first + n; i++) {
  79                 uint64_t va;
  80                 program->global_buffers[i] = resources[i];
  81                 va = r600_resource_va(ctx->screen, resources[i]);
  82                 memcpy(handles[i], &va, sizeof(va));
  83         }
  84 }
  85
  86 static void radeonsi_launch_grid(
  87                 struct pipe_context *ctx,
  88                 const uint *block_layout, const uint *grid_layout,
  89                 uint32_t pc, const void *input)
  90 {
  91         struct r600_context *rctx = (struct r600_context*)ctx;
  92         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  93         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
  94         struct si_resource *input_buffer = NULL;
  95         uint32_t input_offset = 0;
  96         uint64_t input_va;
  97         uint64_t shader_va;
  98         unsigned arg_user_sgpr_count = 2;
  99         unsigned i;
 100         struct si_pipe_shader *shader = &program->kernels[pc];
 101
 102         pm4->compute_pkt = true;
 103         si_cmd_context_control(pm4);
 104
 105         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 106         si_pm4_cmd_add(pm4, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) |
 107                             EVENT_INDEX(0x7) |
 108                             EVENT_WRITE_INV_L2);
 109         si_pm4_cmd_end(pm4, false);
 110
 111         si_pm4_inval_texture_cache(pm4);
 112         si_pm4_inval_shader_cache(pm4);
 113         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 114
 115         /* Upload the input data */
 116         r600_upload_const_buffer(rctx, &input_buffer, input,
 117                                         program->input_size, &input_offset);
 118         input_va = r600_resource_va(ctx->screen, (struct pipe_resource*)input_buffer);
 119         input_va += input_offset;
 120
 121         si_pm4_add_bo(pm4, input_buffer, RADEON_USAGE_READ);
 122
 123         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, input_va);
 124         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (input_va >> 32) | S_008F04_STRIDE(0));
 125
 126         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 127         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 128         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 129
 130         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 131                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 132         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 133                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 134         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 135                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 136
 137         /* Global buffers */
 138         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 139                 struct si_resource *buffer =
 140                                 (struct si_resource*)program->global_buffers[i];
 141                 if (!buffer) {
 142                         continue;
 143                 }
 144                 si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE);
 145         }
 146
 147         /* XXX: This should be:
 148          * (number of compute units) * 4 * (waves per simd) - 1 */
 149         si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
 150
 151         shader_va = r600_resource_va(ctx->screen, (void *)shader->bo);
 152         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
 153         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
 154         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 155
 156         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
 157                 /* We always use at least 3 VGPRS, these come from
 158                  * TIDIG_COMP_CNT.
 159                  * XXX: The compiler should account for this.
 160                  */
 161                 S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
 162                 /* We always use at least 4 + arg_user_sgpr_count.  The 4 extra
 163                  * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
 164                  * XXX: The compiler should account for this.
 165                  */
 166                 |  S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
 167                                         shader->num_sgprs)) - 1) / 8))
 168                 ;
 169
 170         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
 171                 S_00B84C_SCRATCH_EN(0)
 172                 | S_00B84C_USER_SGPR(arg_user_sgpr_count)
 173                 | S_00B84C_TGID_X_EN(1)
 174                 | S_00B84C_TGID_Y_EN(1)
 175                 | S_00B84C_TGID_Z_EN(1)
 176                 | S_00B84C_TG_SIZE_EN(1)
 177                 | S_00B84C_TIDIG_COMP_CNT(2)
 178                 | S_00B84C_LDS_SIZE(0)
 179                 | S_00B84C_EXCP_EN(0))
 180                 ;
 181         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 182
 183         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 184                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 185                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 186                 ;
 187
 188         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 189                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 190                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 191                 ;
 192
 193         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 194         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 195         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 196         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 197         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 198         si_pm4_cmd_end(pm4, false);
 199
 200         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 201         si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
 202         si_pm4_cmd_end(pm4, false);
 203
 204         si_pm4_inval_texture_cache(pm4);
 205         si_pm4_inval_shader_cache(pm4);
 206         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 207
 208         si_pm4_emit(rctx, pm4);
 209
 210 #if 0
 211         fprintf(stderr, "cdw: %i\n", rctx->cs->cdw);
 212         for (i = 0; i < rctx->cs->cdw; i++) {
 213                 fprintf(stderr, "%4i : 0x%08X\n", i, rctx->cs->buf[i]);
 214         }
 215 #endif
 216
 217         rctx->ws->cs_flush(rctx->cs, RADEON_FLUSH_COMPUTE, 0);
 218         rctx->ws->buffer_wait(shader->bo->buf, 0);
 219
 220         FREE(pm4);
 221 }
 222
 223
 224 static void si_delete_compute_state(struct pipe_context *ctx, void* state){}
 225 static void si_set_compute_resources(struct pipe_context * ctx_,
 226                 unsigned start, unsigned count,
 227                 struct pipe_surface ** surfaces) { }
 228 static void si_set_cs_sampler_view(struct pipe_context *ctx_,
 229                 unsigned start_slot, unsigned count,
 230                 struct pipe_sampler_view **views) { }
 231
 232 static void si_bind_compute_sampler_states(
 233         struct pipe_context *ctx_,
 234         unsigned start_slot,
 235         unsigned num_samplers,
 236         void **samplers_) { }
 237 void si_init_compute_functions(struct r600_context *rctx)
 238 {
 239         rctx->context.create_compute_state = radeonsi_create_compute_state;
 240         rctx->context.delete_compute_state = si_delete_compute_state;
 241         rctx->context.bind_compute_state = radeonsi_bind_compute_state;
 242 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 243         rctx->context.set_compute_resources = si_set_compute_resources;
 244         rctx->context.set_compute_sampler_views = si_set_cs_sampler_view;
 245         rctx->context.bind_compute_sampler_states = si_bind_compute_sampler_states;
 246         rctx->context.set_global_binding = radeonsi_set_global_binding;
 247         rctx->context.launch_grid = radeonsi_launch_grid;
 248 }