src/gallium/drivers/radeonsi/radeonsi_compute.c

   1 #include "util/u_memory.h"
   2
   3 #include "radeonsi_pipe.h"
   4 #include "radeonsi_shader.h"
   5
   6 #include "radeon_llvm_util.h"
   7
   8 #define MAX_GLOBAL_BUFFERS 20
   9
  10 struct si_pipe_compute {
  11         struct r600_context *ctx;
  12
  13         unsigned local_size;
  14         unsigned private_size;
  15         unsigned input_size;
  16         unsigned num_kernels;
  17         struct si_pipe_shader *kernels;
  18         unsigned num_user_sgprs;
  19
  20         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  21
  22 };
  23
  24 static void *radeonsi_create_compute_state(
  25         struct pipe_context *ctx,
  26         const struct pipe_compute_state *cso)
  27 {
  28         struct r600_context *rctx = (struct r600_context *)ctx;
  29         struct si_pipe_compute *program =
  30                                         CALLOC_STRUCT(si_pipe_compute);
  31         const struct pipe_llvm_program_header *header;
  32         const unsigned char *code;
  33         unsigned i;
  34
  35         header = cso->prog;
  36         code = cso->prog + sizeof(struct pipe_llvm_program_header);
  37
  38         program->ctx = rctx;
  39         program->local_size = cso->req_local_mem;
  40         program->private_size = cso->req_private_mem;
  41         program->input_size = cso->req_input_mem;
  42
  43         program->num_kernels = radeon_llvm_get_num_kernels(code,
  44                                                         header->num_bytes);
  45         program->kernels = CALLOC(sizeof(struct si_pipe_shader),
  46                                                         program->num_kernels);
  47         for (i = 0; i < program->num_kernels; i++) {
  48                 LLVMModuleRef mod = radeon_llvm_get_kernel_module(i, code,
  49                                                         header->num_bytes);
  50                 si_compile_llvm(rctx, &program->kernels[i], mod);
  51         }
  52
  53         return program;
  54 }
  55
  56 static void radeonsi_bind_compute_state(struct pipe_context *ctx, void *state)
  57 {
  58         struct r600_context *rctx = (struct r600_context*)ctx;
  59         rctx->cs_shader_state.program = (struct si_pipe_compute*)state;
  60 }
  61
  62 static void radeonsi_set_global_binding(
  63         struct pipe_context *ctx, unsigned first, unsigned n,
  64         struct pipe_resource **resources,
  65         uint32_t **handles)
  66 {
  67         unsigned i;
  68         struct r600_context *rctx = (struct r600_context*)ctx;
  69         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  70
  71         if (!resources) {
  72                 for (i = first; i < first + n; i++) {
  73                         program->global_buffers[i] = NULL;
  74                 }
  75                 return;
  76         }
  77
  78         for (i = first; i < first + n; i++) {
  79                 uint64_t va;
  80                 program->global_buffers[i] = resources[i];
  81                 va = r600_resource_va(ctx->screen, resources[i]);
  82                 memcpy(handles[i], &va, sizeof(va));
  83         }
  84 }
  85
  86 static void radeonsi_launch_grid(
  87                 struct pipe_context *ctx,
  88                 const uint *block_layout, const uint *grid_layout,
  89                 uint32_t pc, const void *input)
  90 {
  91         struct r600_context *rctx = (struct r600_context*)ctx;
  92         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  93         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
  94         uint64_t shader_va;
  95         unsigned arg_user_sgpr_count;
  96         unsigned i;
  97         struct si_pipe_shader *shader = &program->kernels[pc];
  98
  99         pm4->compute_pkt = true;
 100         si_cmd_context_control(pm4);
 101
 102         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 103         si_pm4_cmd_add(pm4, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) |
 104                             EVENT_INDEX(0x7) |
 105                             EVENT_WRITE_INV_L2);
 106         si_pm4_cmd_end(pm4, false);
 107
 108         si_pm4_inval_texture_cache(pm4);
 109         si_pm4_inval_shader_cache(pm4);
 110         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 111
 112         arg_user_sgpr_count = program->input_size / 4;
 113         if (program->input_size % 4 != 0) {
 114                 arg_user_sgpr_count++;
 115         }
 116
 117         /* XXX: We should store arguments in memory if we run out of user sgprs.
 118          */
 119         assert(arg_user_sgpr_count < 16);
 120
 121         for (i = 0; i < arg_user_sgpr_count; i++) {
 122                 uint32_t *args = (uint32_t*)input;
 123                 si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 +
 124                                         (i * 4),
 125                                         args[i]);
 126         }
 127
 128         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 129         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 130         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 131
 132         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 133                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 134         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 135                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 136         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 137                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 138
 139         /* Global buffers */
 140         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 141                 struct si_resource *buffer =
 142                                 (struct si_resource*)program->global_buffers[i];
 143                 if (!buffer) {
 144                         continue;
 145                 }
 146                 si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE);
 147         }
 148
 149         /* XXX: This should be:
 150          * (number of compute units) * 4 * (waves per simd) - 1 */
 151         si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
 152
 153         shader_va = r600_resource_va(ctx->screen, (void *)shader->bo);
 154         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
 155         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
 156         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 157
 158         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
 159                 /* We always use at least 3 VGPRS, these come from
 160                  * TIDIG_COMP_CNT.
 161                  * XXX: The compiler should account for this.
 162                  */
 163                 S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
 164                 /* We always use at least 4 + arg_user_sgpr_count.  The 4 extra
 165                  * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
 166                  * XXX: The compiler should account for this.
 167                  */
 168                 |  S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
 169                                         shader->num_sgprs)) - 1) / 8))
 170                 ;
 171
 172         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
 173                 S_00B84C_SCRATCH_EN(0)
 174                 | S_00B84C_USER_SGPR(arg_user_sgpr_count)
 175                 | S_00B84C_TGID_X_EN(1)
 176                 | S_00B84C_TGID_Y_EN(1)
 177                 | S_00B84C_TGID_Z_EN(1)
 178                 | S_00B84C_TG_SIZE_EN(1)
 179                 | S_00B84C_TIDIG_COMP_CNT(2)
 180                 | S_00B84C_LDS_SIZE(0)
 181                 | S_00B84C_EXCP_EN(0))
 182                 ;
 183         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 184
 185         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 186                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 187                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 188                 ;
 189
 190         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 191                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 192                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 193                 ;
 194
 195         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 196         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 197         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 198         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 199         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 200         si_pm4_cmd_end(pm4, false);
 201
 202         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 203         si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
 204         si_pm4_cmd_end(pm4, false);
 205
 206         si_pm4_inval_texture_cache(pm4);
 207         si_pm4_inval_shader_cache(pm4);
 208         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 209
 210         si_pm4_emit(rctx, pm4);
 211
 212 #if 0
 213         fprintf(stderr, "cdw: %i\n", rctx->cs->cdw);
 214         for (i = 0; i < rctx->cs->cdw; i++) {
 215                 fprintf(stderr, "%4i : 0x%08X\n", i, rctx->cs->buf[i]);
 216         }
 217 #endif
 218
 219         rctx->ws->cs_flush(rctx->cs, RADEON_FLUSH_COMPUTE, 0);
 220         rctx->ws->buffer_wait(shader->bo->buf, 0);
 221
 222         FREE(pm4);
 223 }
 224
 225
 226 static void si_delete_compute_state(struct pipe_context *ctx, void* state){}
 227 static void si_set_compute_resources(struct pipe_context * ctx_,
 228                 unsigned start, unsigned count,
 229                 struct pipe_surface ** surfaces) { }
 230 static void si_set_cs_sampler_view(struct pipe_context *ctx_,
 231                 unsigned start_slot, unsigned count,
 232                 struct pipe_sampler_view **views) { }
 233
 234 static void si_bind_compute_sampler_states(
 235         struct pipe_context *ctx_,
 236         unsigned start_slot,
 237         unsigned num_samplers,
 238         void **samplers_) { }
 239 void si_init_compute_functions(struct r600_context *rctx)
 240 {
 241         rctx->context.create_compute_state = radeonsi_create_compute_state;
 242         rctx->context.delete_compute_state = si_delete_compute_state;
 243         rctx->context.bind_compute_state = radeonsi_bind_compute_state;
 244 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 245         rctx->context.set_compute_resources = si_set_compute_resources;
 246         rctx->context.set_compute_sampler_views = si_set_cs_sampler_view;
 247         rctx->context.bind_compute_sampler_states = si_bind_compute_sampler_states;
 248         rctx->context.set_global_binding = radeonsi_set_global_binding;
 249         rctx->context.launch_grid = radeonsi_launch_grid;
 250 }