src/gallium/drivers/radeonsi/radeonsi_compute.c

   1 #include "util/u_memory.h"
   2
   3 #include "radeonsi_pipe.h"
   4 #include "radeonsi_shader.h"
   5
   6 #include "radeon_llvm_util.h"
   7
   8 struct si_pipe_compute {
   9         struct r600_context *ctx;
  10
  11         unsigned local_size;
  12         unsigned private_size;
  13         unsigned input_size;
  14         unsigned num_kernels;
  15         struct si_pipe_shader *kernels;
  16         unsigned num_user_sgprs;
  17
  18         struct si_pm4_state *pm4_buffers;
  19
  20 };
  21
  22 static void *radeonsi_create_compute_state(
  23         struct pipe_context *ctx,
  24         const struct pipe_compute_state *cso)
  25 {
  26         struct r600_context *rctx = (struct r600_context *)ctx;
  27         struct si_pipe_compute *program =
  28                                         CALLOC_STRUCT(si_pipe_compute);
  29         const struct pipe_llvm_program_header *header;
  30         const unsigned char *code;
  31         unsigned i;
  32
  33         header = cso->prog;
  34         code = cso->prog + sizeof(struct pipe_llvm_program_header);
  35
  36         program->ctx = rctx;
  37         program->local_size = cso->req_local_mem;
  38         program->private_size = cso->req_private_mem;
  39         program->input_size = cso->req_input_mem;
  40
  41         program->num_kernels = radeon_llvm_get_num_kernels(code,
  42                                                         header->num_bytes);
  43         program->kernels = CALLOC(sizeof(struct si_pipe_shader),
  44                                                         program->num_kernels);
  45         for (i = 0; i < program->num_kernels; i++) {
  46                 LLVMModuleRef mod = radeon_llvm_get_kernel_module(i, code,
  47                                                         header->num_bytes);
  48                 si_compile_llvm(rctx, &program->kernels[i], mod);
  49         }
  50
  51         return program;
  52 }
  53
  54 static void radeonsi_bind_compute_state(struct pipe_context *ctx, void *state)
  55 {
  56         struct r600_context *rctx = (struct r600_context*)ctx;
  57         rctx->cs_shader_state.program = (struct si_pipe_compute*)state;
  58 }
  59
  60 static void radeonsi_set_global_binding(
  61         struct pipe_context *ctx, unsigned first, unsigned n,
  62         struct pipe_resource **resources,
  63         uint32_t **handles)
  64 {
  65         unsigned i;
  66         struct r600_context *rctx = (struct r600_context*)ctx;
  67         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  68         struct si_pm4_state *pm4;
  69
  70         if (!program->pm4_buffers) {
  71                 program->pm4_buffers = CALLOC_STRUCT(si_pm4_state);
  72         }
  73         pm4 = program->pm4_buffers;
  74         pm4->compute_pkt = true;
  75
  76         if (!resources) {
  77                 return;
  78         }
  79
  80         for (i = first; i < first + n; i++) {
  81                 uint64_t va = r600_resource_va(ctx->screen, resources[i]);
  82                 si_pm4_add_bo(pm4, (struct si_resource*)resources[i],
  83                                 RADEON_USAGE_READWRITE);
  84                 memcpy(handles[i], &va, sizeof(va));
  85         }
  86 }
  87
  88 static void radeonsi_launch_grid(
  89                 struct pipe_context *ctx,
  90                 const uint *block_layout, const uint *grid_layout,
  91                 uint32_t pc, const void *input)
  92 {
  93         struct r600_context *rctx = (struct r600_context*)ctx;
  94         struct si_pipe_compute *program = rctx->cs_shader_state.program;
  95         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
  96         uint64_t shader_va;
  97         unsigned arg_user_sgpr_count;
  98         unsigned i;
  99         struct si_pipe_shader *shader = &program->kernels[pc];
 100
 101         pm4->compute_pkt = true;
 102         si_cmd_context_control(pm4);
 103
 104         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 105         si_pm4_cmd_add(pm4, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) |
 106                             EVENT_INDEX(0x7) |
 107                             EVENT_WRITE_INV_L2);
 108         si_pm4_cmd_end(pm4, false);
 109
 110         si_pm4_inval_texture_cache(pm4);
 111         si_pm4_inval_shader_cache(pm4);
 112         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 113
 114         arg_user_sgpr_count = program->input_size / 4;
 115         if (program->input_size % 4 != 0) {
 116                 arg_user_sgpr_count++;
 117         }
 118
 119         /* XXX: We should store arguments in memory if we run out of user sgprs.
 120          */
 121         assert(arg_user_sgpr_count < 16);
 122
 123         for (i = 0; i < arg_user_sgpr_count; i++) {
 124                 uint32_t *args = (uint32_t*)input;
 125                 si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 +
 126                                         (i * 4),
 127                                         args[i]);
 128         }
 129
 130         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 131         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 132         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 133
 134         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 135                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 136         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 137                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 138         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 139                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 140
 141         /* XXX: This should be:
 142          * (number of compute units) * 4 * (waves per simd) - 1 */
 143         si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
 144
 145         shader_va = r600_resource_va(ctx->screen, (void *)shader->bo);
 146         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
 147         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
 148         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 149
 150         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
 151                 /* We always use at least 3 VGPRS, these come from
 152                  * TIDIG_COMP_CNT.
 153                  * XXX: The compiler should account for this.
 154                  */
 155                 S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
 156                 /* We always use at least 4 + arg_user_sgpr_count.  The 4 extra
 157                  * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
 158                  * XXX: The compiler should account for this.
 159                  */
 160                 |  S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
 161                                         shader->num_sgprs)) - 1) / 8))
 162                 ;
 163
 164         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
 165                 S_00B84C_SCRATCH_EN(0)
 166                 | S_00B84C_USER_SGPR(arg_user_sgpr_count)
 167                 | S_00B84C_TGID_X_EN(1)
 168                 | S_00B84C_TGID_Y_EN(1)
 169                 | S_00B84C_TGID_Z_EN(1)
 170                 | S_00B84C_TG_SIZE_EN(1)
 171                 | S_00B84C_TIDIG_COMP_CNT(2)
 172                 | S_00B84C_LDS_SIZE(0)
 173                 | S_00B84C_EXCP_EN(0))
 174                 ;
 175         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 176
 177         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 178                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 179                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 180                 ;
 181
 182         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 183                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 184                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 185                 ;
 186
 187         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 188         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 189         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 190         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 191         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 192         si_pm4_cmd_end(pm4, false);
 193
 194         si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
 195         si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
 196         si_pm4_cmd_end(pm4, false);
 197
 198         si_pm4_inval_texture_cache(pm4);
 199         si_pm4_inval_shader_cache(pm4);
 200         si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
 201
 202         si_pm4_emit(rctx, program->pm4_buffers);
 203         si_pm4_emit(rctx, pm4);
 204
 205 #if 0
 206         fprintf(stderr, "cdw: %i\n", rctx->cs->cdw);
 207         for (i = 0; i < rctx->cs->cdw; i++) {
 208                 fprintf(stderr, "%4i : 0x%08X\n", i, rctx->cs->buf[i]);
 209         }
 210 #endif
 211
 212         rctx->ws->cs_flush(rctx->cs, RADEON_FLUSH_COMPUTE, 0);
 213         rctx->ws->buffer_wait(shader->bo->buf, 0);
 214
 215         FREE(pm4);
 216 }
 217
 218
 219 static void si_delete_compute_state(struct pipe_context *ctx, void* state){}
 220 static void si_set_compute_resources(struct pipe_context * ctx_,
 221                 unsigned start, unsigned count,
 222                 struct pipe_surface ** surfaces) { }
 223 static void si_set_cs_sampler_view(struct pipe_context *ctx_,
 224                 unsigned start_slot, unsigned count,
 225                 struct pipe_sampler_view **views) { }
 226
 227 static void si_bind_compute_sampler_states(
 228         struct pipe_context *ctx_,
 229         unsigned start_slot,
 230         unsigned num_samplers,
 231         void **samplers_) { }
 232 void si_init_compute_functions(struct r600_context *rctx)
 233 {
 234         rctx->context.create_compute_state = radeonsi_create_compute_state;
 235         rctx->context.delete_compute_state = si_delete_compute_state;
 236         rctx->context.bind_compute_state = radeonsi_bind_compute_state;
 237 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 238         rctx->context.set_compute_resources = si_set_compute_resources;
 239         rctx->context.set_compute_sampler_views = si_set_cs_sampler_view;
 240         rctx->context.bind_compute_sampler_states = si_bind_compute_sampler_states;
 241         rctx->context.set_global_binding = radeonsi_set_global_binding;
 242         rctx->context.launch_grid = radeonsi_launch_grid;
 243 }