src/gallium/drivers/radeonsi/radeonsi_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_simple_shaders.h"
  41 #include "util/u_upload_mgr.h"
  42 #include "vl/vl_decoder.h"
  43 #include "vl/vl_video_buffer.h"
  44 #include "os/os_time.h"
  45 #include "pipebuffer/pb_buffer.h"
  46 #include "radeonsi_pipe.h"
  47 #include "radeon/radeon_uvd.h"
  48 #include "r600.h"
  49 #include "sid.h"
  50 #include "r600_resource.h"
  51 #include "radeonsi_pipe.h"
  52 #include "r600_hw_context_priv.h"
  53 #include "si_state.h"
  54
  55 /*
  56  * pipe_context
  57  */
  58 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  59 {
  60         struct r600_screen *rscreen = rctx->screen;
  61         struct r600_fence *fence = NULL;
  62
  63         pipe_mutex_lock(rscreen->fences.mutex);
  64
  65         if (!rscreen->fences.bo) {
  66                 /* Create the shared buffer object */
  67                 rscreen->fences.bo = si_resource_create_custom(&rscreen->screen,
  68                                                                PIPE_USAGE_STAGING,
  69                                                                4096);
  70                 if (!rscreen->fences.bo) {
  71                         R600_ERR("r600: failed to create bo for fence objects\n");
  72                         goto out;
  73                 }
  74                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  75                                                            rctx->cs,
  76                                                            PIPE_TRANSFER_READ_WRITE);
  77         }
  78
  79         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  80                 struct r600_fence *entry;
  81
  82                 /* Try to find a freed fence that has been signalled */
  83                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  84                         if (rscreen->fences.data[entry->index] != 0) {
  85                                 LIST_DELINIT(&entry->head);
  86                                 fence = entry;
  87                                 break;
  88                         }
  89                 }
  90         }
  91
  92         if (!fence) {
  93                 /* Allocate a new fence */
  94                 struct r600_fence_block *block;
  95                 unsigned index;
  96
  97                 if ((rscreen->fences.next_index + 1) >= 1024) {
  98                         R600_ERR("r600: too many concurrent fences\n");
  99                         goto out;
 100                 }
 101
 102                 index = rscreen->fences.next_index++;
 103
 104                 if (!(index % FENCE_BLOCK_SIZE)) {
 105                         /* Allocate a new block */
 106                         block = CALLOC_STRUCT(r600_fence_block);
 107                         if (block == NULL)
 108                                 goto out;
 109
 110                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 111                 } else {
 112                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 113                 }
 114
 115                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 116                 fence->index = index;
 117         }
 118
 119         pipe_reference_init(&fence->reference, 1);
 120
 121         rscreen->fences.data[fence->index] = 0;
 122         si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 123
 124         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 125         fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
 126
 127         /* Add the fence as a dummy relocation. */
 128         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 129
 130 out:
 131         pipe_mutex_unlock(rscreen->fences.mutex);
 132         return fence;
 133 }
 134
 135
 136 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 137                     unsigned flags)
 138 {
 139         struct r600_context *rctx = (struct r600_context *)ctx;
 140         struct r600_fence **rfence = (struct r600_fence**)fence;
 141         struct pipe_query *render_cond = NULL;
 142         boolean render_cond_cond = FALSE;
 143         unsigned render_cond_mode = 0;
 144
 145         if (rfence)
 146                 *rfence = r600_create_fence(rctx);
 147
 148         /* Disable render condition. */
 149         if (rctx->current_render_cond) {
 150                 render_cond = rctx->current_render_cond;
 151                 render_cond_cond = rctx->current_render_cond_cond;
 152                 render_cond_mode = rctx->current_render_cond_mode;
 153                 ctx->render_condition(ctx, NULL, FALSE, 0);
 154         }
 155
 156         si_context_flush(rctx, flags);
 157
 158         /* Re-enable render condition. */
 159         if (render_cond) {
 160                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
 161         }
 162 }
 163
 164 static void r600_flush_from_st(struct pipe_context *ctx,
 165                                struct pipe_fence_handle **fence,
 166                                unsigned flags)
 167 {
 168         radeonsi_flush(ctx, fence,
 169                        flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
 170 }
 171
 172 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 173 {
 174         radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
 175 }
 176
 177 static void r600_destroy_context(struct pipe_context *context)
 178 {
 179         struct r600_context *rctx = (struct r600_context *)context;
 180
 181         si_resource_reference(&rctx->border_color_table, NULL);
 182
 183         if (rctx->dummy_pixel_shader) {
 184                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 185         }
 186         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth_stencil);
 187         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth);
 188         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_stencil);
 189         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_inplace);
 190         util_unreference_framebuffer_state(&rctx->framebuffer);
 191
 192         util_blitter_destroy(rctx->blitter);
 193
 194         if (rctx->uploader) {
 195                 u_upload_destroy(rctx->uploader);
 196         }
 197         util_slab_destroy(&rctx->pool_transfers);
 198         FREE(rctx);
 199 }
 200
 201 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 202 {
 203         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 204         struct r600_screen* rscreen = (struct r600_screen *)screen;
 205
 206         if (rctx == NULL)
 207                 return NULL;
 208
 209         rctx->context.screen = screen;
 210         rctx->context.priv = priv;
 211         rctx->context.destroy = r600_destroy_context;
 212         rctx->context.flush = r600_flush_from_st;
 213
 214         /* Easy accessing of screen/winsys. */
 215         rctx->screen = rscreen;
 216         rctx->ws = rscreen->ws;
 217         rctx->family = rscreen->family;
 218         rctx->chip_class = rscreen->chip_class;
 219
 220         si_init_blit_functions(rctx);
 221         r600_init_query_functions(rctx);
 222         r600_init_context_resource_functions(rctx);
 223         si_init_surface_functions(rctx);
 224         si_init_compute_functions(rctx);
 225
 226         if (rscreen->info.has_uvd) {
 227                 rctx->context.create_video_decoder = radeonsi_uvd_create_decoder;
 228                 rctx->context.create_video_buffer = radeonsi_video_buffer_create;
 229         } else {
 230                 rctx->context.create_video_decoder = vl_create_decoder;
 231                 rctx->context.create_video_buffer = vl_video_buffer_create;
 232         }
 233
 234         switch (rctx->chip_class) {
 235         case SI:
 236                 si_init_state_functions(rctx);
 237                 LIST_INITHEAD(&rctx->active_query_list);
 238                 rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
 239                 rctx->max_db = 8;
 240                 si_init_config(rctx);
 241                 break;
 242         case CIK:
 243                 si_init_state_functions(rctx);
 244                 LIST_INITHEAD(&rctx->active_query_list);
 245                 rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
 246                 rctx->max_db = 8;
 247                 si_init_config(rctx);
 248                 break;
 249         default:
 250                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 251                 r600_destroy_context(&rctx->context);
 252                 return NULL;
 253         }
 254
 255         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 256
 257         util_slab_create(&rctx->pool_transfers,
 258                          sizeof(struct pipe_transfer), 64,
 259                          UTIL_SLAB_SINGLETHREADED);
 260
 261         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 262                                          PIPE_BIND_INDEX_BUFFER |
 263                                          PIPE_BIND_CONSTANT_BUFFER);
 264         if (!rctx->uploader) {
 265                 r600_destroy_context(&rctx->context);
 266                 return NULL;
 267         }
 268
 269         rctx->blitter = util_blitter_create(&rctx->context);
 270         if (rctx->blitter == NULL) {
 271                 r600_destroy_context(&rctx->context);
 272                 return NULL;
 273         }
 274
 275         si_get_backend_mask(rctx); /* this emits commands and must be last */
 276
 277         rctx->dummy_pixel_shader =
 278                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 279                                                      TGSI_SEMANTIC_GENERIC,
 280                                                      TGSI_INTERPOLATE_CONSTANT);
 281         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 282
 283         return &rctx->context;
 284 }
 285
 286 /*
 287  * pipe_screen
 288  */
 289 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 290 {
 291         return "X.Org";
 292 }
 293
 294 const char *r600_get_llvm_processor_name(enum radeon_family family)
 295 {
 296         switch (family) {
 297                 case CHIP_TAHITI: return "tahiti";
 298                 case CHIP_PITCAIRN: return "pitcairn";
 299                 case CHIP_VERDE: return "verde";
 300                 case CHIP_OLAND: return "oland";
 301                 case CHIP_HAINAN: return "hainan";
 302                 case CHIP_BONAIRE: return "bonaire";
 303                 case CHIP_KABINI: return "kabini";
 304                 case CHIP_KAVERI: return "kaveri";
 305                 default: return "";
 306         }
 307 }
 308
 309 static const char *r600_get_family_name(enum radeon_family family)
 310 {
 311         switch(family) {
 312         case CHIP_TAHITI: return "AMD TAHITI";
 313         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 314         case CHIP_VERDE: return "AMD CAPE VERDE";
 315         case CHIP_OLAND: return "AMD OLAND";
 316         case CHIP_HAINAN: return "AMD HAINAN";
 317         case CHIP_BONAIRE: return "AMD BONAIRE";
 318         case CHIP_KAVERI: return "AMD KAVERI";
 319         case CHIP_KABINI: return "AMD KABINI";
 320         default: return "AMD unknown";
 321         }
 322 }
 323
 324 static const char* r600_get_name(struct pipe_screen* pscreen)
 325 {
 326         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 327
 328         return r600_get_family_name(rscreen->family);
 329 }
 330
 331 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 332 {
 333         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 334
 335         switch (param) {
 336         /* Supported features (boolean caps). */
 337         case PIPE_CAP_TWO_SIDED_STENCIL:
 338         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 339         case PIPE_CAP_ANISOTROPIC_FILTER:
 340         case PIPE_CAP_POINT_SPRITE:
 341         case PIPE_CAP_OCCLUSION_QUERY:
 342         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 343         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 344         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 345         case PIPE_CAP_TEXTURE_SWIZZLE:
 346         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 347         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 348         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 349         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 350         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 351         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 352         case PIPE_CAP_SM3:
 353         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 354         case PIPE_CAP_PRIMITIVE_RESTART:
 355         case PIPE_CAP_CONDITIONAL_RENDER:
 356         case PIPE_CAP_TEXTURE_BARRIER:
 357         case PIPE_CAP_INDEP_BLEND_ENABLE:
 358         case PIPE_CAP_INDEP_BLEND_FUNC:
 359         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 360         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 361         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 362         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 363         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 364         case PIPE_CAP_USER_INDEX_BUFFERS:
 365         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 366         case PIPE_CAP_START_INSTANCE:
 367         case PIPE_CAP_NPOT_TEXTURES:
 368         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 369         case PIPE_CAP_TGSI_INSTANCEID:
 370         case PIPE_CAP_COMPUTE:
 371                 return 1;
 372         case PIPE_CAP_TGSI_TEXCOORD:
 373                 return 0;
 374
 375         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 376                 return 64;
 377
 378         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 379                 return 256;
 380
 381         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 382                 return 130;
 383
 384         /* Unsupported features. */
 385         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 386         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 387         case PIPE_CAP_SCALED_RESOLVE:
 388         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 389         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 390         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 391         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 392         case PIPE_CAP_USER_VERTEX_BUFFERS:
 393         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 394         case PIPE_CAP_QUERY_TIMESTAMP:
 395         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 396         case PIPE_CAP_CUBE_MAP_ARRAY:
 397         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 398         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 399         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 400         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 401                 return 0;
 402
 403         /* Stream output. */
 404 #if 0
 405         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 406                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 407         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 408                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
 409         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 410         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 411                 return 16*4;
 412 #endif
 413         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 414         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 415         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 416         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 417                 return 0;
 418
 419         /* Texturing. */
 420         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 421         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 422         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 423                         return 15;
 424         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 425                 return 16384;
 426         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 427                 return 32;
 428
 429         /* Render targets. */
 430         case PIPE_CAP_MAX_RENDER_TARGETS:
 431                 /* FIXME some r6xx are buggy and can only do 4 */
 432                 return 8;
 433
 434         /* Timer queries, present when the clock frequency is non zero. */
 435         case PIPE_CAP_QUERY_TIME_ELAPSED:
 436                 return rscreen->info.r600_clock_crystal_freq != 0;
 437
 438         case PIPE_CAP_MIN_TEXEL_OFFSET:
 439                 return -8;
 440
 441         case PIPE_CAP_MAX_TEXEL_OFFSET:
 442                 return 7;
 443         case PIPE_CAP_ENDIANNESS:
 444                 return PIPE_ENDIAN_LITTLE;
 445         }
 446         return 0;
 447 }
 448
 449 static float r600_get_paramf(struct pipe_screen* pscreen,
 450                              enum pipe_capf param)
 451 {
 452         switch (param) {
 453         case PIPE_CAPF_MAX_LINE_WIDTH:
 454         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 455         case PIPE_CAPF_MAX_POINT_WIDTH:
 456         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 457                 return 16384.0f;
 458         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 459                 return 16.0f;
 460         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 461                 return 16.0f;
 462         case PIPE_CAPF_GUARD_BAND_LEFT:
 463         case PIPE_CAPF_GUARD_BAND_TOP:
 464         case PIPE_CAPF_GUARD_BAND_RIGHT:
 465         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 466                 return 0.0f;
 467         }
 468         return 0.0f;
 469 }
 470
 471 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 472 {
 473         switch(shader)
 474         {
 475         case PIPE_SHADER_FRAGMENT:
 476         case PIPE_SHADER_VERTEX:
 477                 break;
 478         case PIPE_SHADER_GEOMETRY:
 479                 /* TODO: support and enable geometry programs */
 480                 return 0;
 481         case PIPE_SHADER_COMPUTE:
 482                 switch (param) {
 483                 case PIPE_SHADER_CAP_PREFERRED_IR:
 484                         return PIPE_SHADER_IR_LLVM;
 485                 default:
 486                         return 0;
 487                 }
 488         default:
 489                 /* TODO: support tessellation */
 490                 return 0;
 491         }
 492
 493         switch (param) {
 494         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 495         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 496         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 497         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 498                 return 16384;
 499         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 500                 return 32;
 501         case PIPE_SHADER_CAP_MAX_INPUTS:
 502                 return 32;
 503         case PIPE_SHADER_CAP_MAX_TEMPS:
 504                 return 256; /* Max native temporaries. */
 505         case PIPE_SHADER_CAP_MAX_ADDRS:
 506                 /* FIXME Isn't this equal to TEMPS? */
 507                 return 1; /* Max native address registers */
 508         case PIPE_SHADER_CAP_MAX_CONSTS:
 509                 return 4096; /* actually only memory limits this */
 510         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 511                 return 1;
 512         case PIPE_SHADER_CAP_MAX_PREDS:
 513                 return 0; /* FIXME */
 514         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 515                 return 1;
 516         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 517                 return 0;
 518         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 519         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 520         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 521         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 522                 return 1;
 523         case PIPE_SHADER_CAP_INTEGERS:
 524                 return 1;
 525         case PIPE_SHADER_CAP_SUBROUTINES:
 526                 return 0;
 527         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 528                 return 16;
 529         case PIPE_SHADER_CAP_PREFERRED_IR:
 530                 return PIPE_SHADER_IR_TGSI;
 531         }
 532         return 0;
 533 }
 534
 535 static int r600_get_video_param(struct pipe_screen *screen,
 536                                 enum pipe_video_profile profile,
 537                                 enum pipe_video_cap param)
 538 {
 539         switch (param) {
 540         case PIPE_VIDEO_CAP_SUPPORTED:
 541                 return vl_profile_supported(screen, profile);
 542         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 543                 return 1;
 544         case PIPE_VIDEO_CAP_MAX_WIDTH:
 545         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 546                 return vl_video_buffer_max_size(screen);
 547         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 548                 return PIPE_FORMAT_NV12;
 549         default:
 550                 return 0;
 551         }
 552 }
 553
 554 static int r600_get_compute_param(struct pipe_screen *screen,
 555         enum pipe_compute_cap param,
 556         void *ret)
 557 {
 558         struct r600_screen *rscreen = (struct r600_screen *)screen;
 559         //TODO: select these params by asic
 560         switch (param) {
 561         case PIPE_COMPUTE_CAP_IR_TARGET: {
 562                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 563                 if (ret) {
 564                         sprintf(ret, "%s-r600--", gpu);
 565                 }
 566                 return (8 + strlen(gpu)) * sizeof(char);
 567         }
 568         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 569                 if (ret) {
 570                         uint64_t * grid_dimension = ret;
 571                         grid_dimension[0] = 3;
 572                 }
 573                 return 1 * sizeof(uint64_t);
 574         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 575                 if (ret) {
 576                         uint64_t * grid_size = ret;
 577                         grid_size[0] = 65535;
 578                         grid_size[1] = 65535;
 579                         grid_size[2] = 1;
 580                 }
 581                 return 3 * sizeof(uint64_t) ;
 582
 583         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 584                 if (ret) {
 585                         uint64_t * block_size = ret;
 586                         block_size[0] = 256;
 587                         block_size[1] = 256;
 588                         block_size[2] = 256;
 589                 }
 590                 return 3 * sizeof(uint64_t);
 591         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 592                 if (ret) {
 593                         uint64_t * max_threads_per_block = ret;
 594                         *max_threads_per_block = 256;
 595                 }
 596                 return sizeof(uint64_t);
 597
 598         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 599                 if (ret) {
 600                         uint64_t *max_global_size = ret;
 601                         /* XXX: Not sure what to put here. */
 602                         *max_global_size = 2000000000;
 603                 }
 604                 return sizeof(uint64_t);
 605
 606         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 607                 if (ret) {
 608                         uint64_t max_global_size;
 609                         uint64_t *max_mem_alloc_size = ret;
 610                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 611                         *max_mem_alloc_size = max_global_size / 4;
 612                 }
 613                 return sizeof(uint64_t);
 614         default:
 615                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 616                 return 0;
 617         }
 618 }
 619
 620 static void r600_destroy_screen(struct pipe_screen* pscreen)
 621 {
 622         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 623
 624         if (rscreen == NULL)
 625                 return;
 626
 627         if (rscreen->fences.bo) {
 628                 struct r600_fence_block *entry, *tmp;
 629
 630                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 631                         LIST_DEL(&entry->head);
 632                         FREE(entry);
 633                 }
 634
 635                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 636                 si_resource_reference(&rscreen->fences.bo, NULL);
 637         }
 638
 639 #if R600_TRACE_CS
 640         if (rscreen->trace_bo) {
 641                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 642                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 643         }
 644 #endif
 645
 646         pipe_mutex_destroy(rscreen->fences.mutex);
 647
 648         rscreen->ws->destroy(rscreen->ws);
 649         FREE(rscreen);
 650 }
 651
 652 static void r600_fence_reference(struct pipe_screen *pscreen,
 653                                  struct pipe_fence_handle **ptr,
 654                                  struct pipe_fence_handle *fence)
 655 {
 656         struct r600_fence **oldf = (struct r600_fence**)ptr;
 657         struct r600_fence *newf = (struct r600_fence*)fence;
 658
 659         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 660                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 661                 pipe_mutex_lock(rscreen->fences.mutex);
 662                 si_resource_reference(&(*oldf)->sleep_bo, NULL);
 663                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 664                 pipe_mutex_unlock(rscreen->fences.mutex);
 665         }
 666
 667         *ptr = fence;
 668 }
 669
 670 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 671                                     struct pipe_fence_handle *fence)
 672 {
 673         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 674         struct r600_fence *rfence = (struct r600_fence*)fence;
 675
 676         return rscreen->fences.data[rfence->index] != 0;
 677 }
 678
 679 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 680                                  struct pipe_fence_handle *fence,
 681                                  uint64_t timeout)
 682 {
 683         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 684         struct r600_fence *rfence = (struct r600_fence*)fence;
 685         int64_t start_time = 0;
 686         unsigned spins = 0;
 687
 688         if (timeout != PIPE_TIMEOUT_INFINITE) {
 689                 start_time = os_time_get();
 690
 691                 /* Convert to microseconds. */
 692                 timeout /= 1000;
 693         }
 694
 695         while (rscreen->fences.data[rfence->index] == 0) {
 696                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 697                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 698                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 699                         break;
 700                 }
 701
 702                 /* The dummy BO will be busy until the CS including the fence has completed, or
 703                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 704                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 705                         break;
 706
 707                 if (++spins % 256)
 708                         continue;
 709 #ifdef PIPE_OS_UNIX
 710                 sched_yield();
 711 #else
 712                 os_time_sleep(10);
 713 #endif
 714                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 715                     os_time_get() - start_time >= timeout) {
 716                         break;
 717                 }
 718         }
 719
 720         return rscreen->fences.data[rfence->index] != 0;
 721 }
 722
 723 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 724 {
 725         switch (tiling_config & 0xf) {
 726         case 0:
 727                 rscreen->tiling_info.num_channels = 1;
 728                 break;
 729         case 1:
 730                 rscreen->tiling_info.num_channels = 2;
 731                 break;
 732         case 2:
 733                 rscreen->tiling_info.num_channels = 4;
 734                 break;
 735         case 3:
 736                 rscreen->tiling_info.num_channels = 8;
 737                 break;
 738         default:
 739                 return -EINVAL;
 740         }
 741
 742         switch ((tiling_config & 0xf0) >> 4) {
 743         case 0:
 744                 rscreen->tiling_info.num_banks = 4;
 745                 break;
 746         case 1:
 747                 rscreen->tiling_info.num_banks = 8;
 748                 break;
 749         case 2:
 750                 rscreen->tiling_info.num_banks = 16;
 751                 break;
 752         default:
 753                 return -EINVAL;
 754         }
 755
 756         switch ((tiling_config & 0xf00) >> 8) {
 757         case 0:
 758                 rscreen->tiling_info.group_bytes = 256;
 759                 break;
 760         case 1:
 761                 rscreen->tiling_info.group_bytes = 512;
 762                 break;
 763         default:
 764                 return -EINVAL;
 765         }
 766         return 0;
 767 }
 768
 769 static int r600_init_tiling(struct r600_screen *rscreen)
 770 {
 771         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 772
 773         /* set default group bytes, overridden by tiling info ioctl */
 774         rscreen->tiling_info.group_bytes = 512;
 775
 776         if (!tiling_config)
 777                 return 0;
 778
 779         return evergreen_interpret_tiling(rscreen, tiling_config);
 780 }
 781
 782 static unsigned radeon_family_from_device(unsigned device)
 783 {
 784         switch (device) {
 785 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 786 #include "pci_ids/radeonsi_pci_ids.h"
 787 #undef CHIPSET
 788         default:
 789                 return CHIP_UNKNOWN;
 790         }
 791 }
 792
 793 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 794 {
 795         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 796         if (rscreen == NULL) {
 797                 return NULL;
 798         }
 799
 800         rscreen->ws = ws;
 801         ws->query_info(ws, &rscreen->info);
 802
 803         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 804         if (rscreen->family == CHIP_UNKNOWN) {
 805                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 806                 FREE(rscreen);
 807                 return NULL;
 808         }
 809
 810         /* setup class */
 811         if (rscreen->family >= CHIP_BONAIRE) {
 812                 rscreen->chip_class = CIK;
 813         } else if (rscreen->family >= CHIP_TAHITI) {
 814                 rscreen->chip_class = SI;
 815         } else {
 816                 fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family);
 817                 FREE(rscreen);
 818                 return NULL;
 819         }
 820
 821         if (r600_init_tiling(rscreen)) {
 822                 FREE(rscreen);
 823                 return NULL;
 824         }
 825
 826         rscreen->screen.destroy = r600_destroy_screen;
 827         rscreen->screen.get_name = r600_get_name;
 828         rscreen->screen.get_vendor = r600_get_vendor;
 829         rscreen->screen.get_param = r600_get_param;
 830         rscreen->screen.get_shader_param = r600_get_shader_param;
 831         rscreen->screen.get_paramf = r600_get_paramf;
 832         rscreen->screen.get_compute_param = r600_get_compute_param;
 833         rscreen->screen.is_format_supported = si_is_format_supported;
 834         rscreen->screen.context_create = r600_create_context;
 835         rscreen->screen.fence_reference = r600_fence_reference;
 836         rscreen->screen.fence_signalled = r600_fence_signalled;
 837         rscreen->screen.fence_finish = r600_fence_finish;
 838         r600_init_screen_resource_functions(&rscreen->screen);
 839
 840         if (rscreen->info.has_uvd) {
 841                 rscreen->screen.get_video_param = ruvd_get_video_param;
 842                 rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
 843         } else {
 844                 rscreen->screen.get_video_param = r600_get_video_param;
 845                 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 846         }
 847
 848         util_format_s3tc_init();
 849
 850         rscreen->fences.bo = NULL;
 851         rscreen->fences.data = NULL;
 852         rscreen->fences.next_index = 0;
 853         LIST_INITHEAD(&rscreen->fences.pool);
 854         LIST_INITHEAD(&rscreen->fences.blocks);
 855         pipe_mutex_init(rscreen->fences.mutex);
 856
 857 #if R600_TRACE_CS
 858         rscreen->cs_count = 0;
 859         if (rscreen->info.drm_minor >= 28) {
 860                 rscreen->trace_bo = (struct si_resource*)pipe_buffer_create(&rscreen->screen,
 861                                                                                 PIPE_BIND_CUSTOM,
 862                                                                                 PIPE_USAGE_STAGING,
 863                                                                                 4096);
 864                 if (rscreen->trace_bo) {
 865                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 866                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 867                 }
 868         }
 869 #endif
 870
 871         return &rscreen->screen;
 872 }