src/gallium/drivers/radeonsi/radeonsi_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_simple_shaders.h"
  41 #include "util/u_upload_mgr.h"
  42 #include "vl/vl_decoder.h"
  43 #include "vl/vl_video_buffer.h"
  44 #include "os/os_time.h"
  45 #include "pipebuffer/pb_buffer.h"
  46 #include "radeonsi_pipe.h"
  47 #include "radeon/radeon_uvd.h"
  48 #include "r600.h"
  49 #include "sid.h"
  50 #include "r600_resource.h"
  51 #include "radeonsi_pipe.h"
  52 #include "r600_hw_context_priv.h"
  53 #include "si_state.h"
  54
  55 /*
  56  * pipe_context
  57  */
  58 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  59 {
  60         struct r600_screen *rscreen = rctx->screen;
  61         struct r600_fence *fence = NULL;
  62
  63         pipe_mutex_lock(rscreen->fences.mutex);
  64
  65         if (!rscreen->fences.bo) {
  66                 /* Create the shared buffer object */
  67                 rscreen->fences.bo = si_resource_create_custom(&rscreen->screen,
  68                                                                PIPE_USAGE_STAGING,
  69                                                                4096);
  70                 if (!rscreen->fences.bo) {
  71                         R600_ERR("r600: failed to create bo for fence objects\n");
  72                         goto out;
  73                 }
  74                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  75                                                            rctx->cs,
  76                                                            PIPE_TRANSFER_READ_WRITE);
  77         }
  78
  79         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  80                 struct r600_fence *entry;
  81
  82                 /* Try to find a freed fence that has been signalled */
  83                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  84                         if (rscreen->fences.data[entry->index] != 0) {
  85                                 LIST_DELINIT(&entry->head);
  86                                 fence = entry;
  87                                 break;
  88                         }
  89                 }
  90         }
  91
  92         if (!fence) {
  93                 /* Allocate a new fence */
  94                 struct r600_fence_block *block;
  95                 unsigned index;
  96
  97                 if ((rscreen->fences.next_index + 1) >= 1024) {
  98                         R600_ERR("r600: too many concurrent fences\n");
  99                         goto out;
 100                 }
 101
 102                 index = rscreen->fences.next_index++;
 103
 104                 if (!(index % FENCE_BLOCK_SIZE)) {
 105                         /* Allocate a new block */
 106                         block = CALLOC_STRUCT(r600_fence_block);
 107                         if (block == NULL)
 108                                 goto out;
 109
 110                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 111                 } else {
 112                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 113                 }
 114
 115                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 116                 fence->index = index;
 117         }
 118
 119         pipe_reference_init(&fence->reference, 1);
 120
 121         rscreen->fences.data[fence->index] = 0;
 122         si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 123
 124         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 125         fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
 126
 127         /* Add the fence as a dummy relocation. */
 128         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 129
 130 out:
 131         pipe_mutex_unlock(rscreen->fences.mutex);
 132         return fence;
 133 }
 134
 135
 136 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 137                     unsigned flags)
 138 {
 139         struct r600_context *rctx = (struct r600_context *)ctx;
 140         struct r600_fence **rfence = (struct r600_fence**)fence;
 141         struct pipe_query *render_cond = NULL;
 142         unsigned render_cond_mode = 0;
 143
 144         if (rfence)
 145                 *rfence = r600_create_fence(rctx);
 146
 147         /* Disable render condition. */
 148         if (rctx->current_render_cond) {
 149                 render_cond = rctx->current_render_cond;
 150                 render_cond_mode = rctx->current_render_cond_mode;
 151                 ctx->render_condition(ctx, NULL, 0);
 152         }
 153
 154         si_context_flush(rctx, flags);
 155
 156         /* Re-enable render condition. */
 157         if (render_cond) {
 158                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 159         }
 160 }
 161
 162 static void r600_flush_from_st(struct pipe_context *ctx,
 163                                struct pipe_fence_handle **fence,
 164                                enum pipe_flush_flags flags)
 165 {
 166         radeonsi_flush(ctx, fence,
 167                        flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
 168 }
 169
 170 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 171 {
 172         radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
 173 }
 174
 175 static void r600_destroy_context(struct pipe_context *context)
 176 {
 177         struct r600_context *rctx = (struct r600_context *)context;
 178
 179         si_resource_reference(&rctx->border_color_table, NULL);
 180
 181         if (rctx->dummy_pixel_shader) {
 182                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 183         }
 184         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth_stencil);
 185         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth);
 186         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_stencil);
 187         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_inplace);
 188         util_unreference_framebuffer_state(&rctx->framebuffer);
 189
 190         util_blitter_destroy(rctx->blitter);
 191
 192         if (rctx->uploader) {
 193                 u_upload_destroy(rctx->uploader);
 194         }
 195         util_slab_destroy(&rctx->pool_transfers);
 196         FREE(rctx);
 197 }
 198
 199 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 200 {
 201         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 202         struct r600_screen* rscreen = (struct r600_screen *)screen;
 203
 204         if (rctx == NULL)
 205                 return NULL;
 206
 207         rctx->context.screen = screen;
 208         rctx->context.priv = priv;
 209         rctx->context.destroy = r600_destroy_context;
 210         rctx->context.flush = r600_flush_from_st;
 211
 212         /* Easy accessing of screen/winsys. */
 213         rctx->screen = rscreen;
 214         rctx->ws = rscreen->ws;
 215         rctx->family = rscreen->family;
 216         rctx->chip_class = rscreen->chip_class;
 217
 218         si_init_blit_functions(rctx);
 219         r600_init_query_functions(rctx);
 220         r600_init_context_resource_functions(rctx);
 221         si_init_surface_functions(rctx);
 222         si_init_compute_functions(rctx);
 223
 224         if (rscreen->info.has_uvd) {
 225                 rctx->context.create_video_decoder = radeonsi_uvd_create_decoder;
 226                 rctx->context.create_video_buffer = radeonsi_video_buffer_create;
 227         } else {
 228                 rctx->context.create_video_decoder = vl_create_decoder;
 229                 rctx->context.create_video_buffer = vl_video_buffer_create;
 230         }
 231
 232         switch (rctx->chip_class) {
 233         case TAHITI:
 234                 si_init_state_functions(rctx);
 235                 LIST_INITHEAD(&rctx->active_query_list);
 236                 rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
 237                 rctx->max_db = 8;
 238                 si_init_config(rctx);
 239                 break;
 240         default:
 241                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 242                 r600_destroy_context(&rctx->context);
 243                 return NULL;
 244         }
 245
 246         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 247
 248         util_slab_create(&rctx->pool_transfers,
 249                          sizeof(struct pipe_transfer), 64,
 250                          UTIL_SLAB_SINGLETHREADED);
 251
 252         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 253                                          PIPE_BIND_INDEX_BUFFER |
 254                                          PIPE_BIND_CONSTANT_BUFFER);
 255         if (!rctx->uploader) {
 256                 r600_destroy_context(&rctx->context);
 257                 return NULL;
 258         }
 259
 260         rctx->blitter = util_blitter_create(&rctx->context);
 261         if (rctx->blitter == NULL) {
 262                 r600_destroy_context(&rctx->context);
 263                 return NULL;
 264         }
 265
 266         si_get_backend_mask(rctx); /* this emits commands and must be last */
 267
 268         rctx->dummy_pixel_shader =
 269                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 270                                                      TGSI_SEMANTIC_GENERIC,
 271                                                      TGSI_INTERPOLATE_CONSTANT);
 272         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 273
 274         return &rctx->context;
 275 }
 276
 277 /*
 278  * pipe_screen
 279  */
 280 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 281 {
 282         return "X.Org";
 283 }
 284
 285 const char *r600_get_llvm_processor_name(enum radeon_family family)
 286 {
 287         switch (family) {
 288                 case CHIP_TAHITI: return "tahiti";
 289                 case CHIP_PITCAIRN: return "pitcairn";
 290                 case CHIP_VERDE: return "verde";
 291                 case CHIP_OLAND: return "oland";
 292                 default: return "";
 293         }
 294 }
 295
 296 static const char *r600_get_family_name(enum radeon_family family)
 297 {
 298         switch(family) {
 299         case CHIP_TAHITI: return "AMD TAHITI";
 300         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 301         case CHIP_VERDE: return "AMD CAPE VERDE";
 302         case CHIP_OLAND: return "AMD OLAND";
 303         default: return "AMD unknown";
 304         }
 305 }
 306
 307 static const char* r600_get_name(struct pipe_screen* pscreen)
 308 {
 309         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 310
 311         return r600_get_family_name(rscreen->family);
 312 }
 313
 314 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 315 {
 316         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 317
 318         switch (param) {
 319         /* Supported features (boolean caps). */
 320         case PIPE_CAP_TWO_SIDED_STENCIL:
 321         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 322         case PIPE_CAP_ANISOTROPIC_FILTER:
 323         case PIPE_CAP_POINT_SPRITE:
 324         case PIPE_CAP_OCCLUSION_QUERY:
 325         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 326         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 327         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 328         case PIPE_CAP_TEXTURE_SWIZZLE:
 329         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 330         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 331         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 332         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 333         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 334         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 335         case PIPE_CAP_SM3:
 336         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 337         case PIPE_CAP_PRIMITIVE_RESTART:
 338         case PIPE_CAP_CONDITIONAL_RENDER:
 339         case PIPE_CAP_TEXTURE_BARRIER:
 340         case PIPE_CAP_INDEP_BLEND_ENABLE:
 341         case PIPE_CAP_INDEP_BLEND_FUNC:
 342         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 343         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 344         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 345         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 346         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 347         case PIPE_CAP_USER_INDEX_BUFFERS:
 348         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 349         case PIPE_CAP_START_INSTANCE:
 350         case PIPE_CAP_NPOT_TEXTURES:
 351         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 352         case PIPE_CAP_TGSI_INSTANCEID:
 353         case PIPE_CAP_COMPUTE:
 354                 return 1;
 355         case PIPE_CAP_TGSI_TEXCOORD:
 356                 return 0;
 357
 358         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 359                 return 64;
 360
 361         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 362                 return 256;
 363
 364         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 365                 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
 366
 367         /* Unsupported features. */
 368         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 369         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 370         case PIPE_CAP_SCALED_RESOLVE:
 371         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 372         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 373         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 374         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 375         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 376         case PIPE_CAP_USER_VERTEX_BUFFERS:
 377         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 378         case PIPE_CAP_QUERY_TIMESTAMP:
 379         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 380         case PIPE_CAP_CUBE_MAP_ARRAY:
 381         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 382         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 383         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 384                 return 0;
 385
 386         /* Stream output. */
 387 #if 0
 388         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 389                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 390         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 391                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
 392         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 393         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 394                 return 16*4;
 395 #endif
 396         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 397         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 398         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 399         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 400                 return 0;
 401
 402         /* Texturing. */
 403         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 404         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 405         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 406                         return 15;
 407         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 408                 return 16384;
 409         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 410                 return 32;
 411
 412         /* Render targets. */
 413         case PIPE_CAP_MAX_RENDER_TARGETS:
 414                 /* FIXME some r6xx are buggy and can only do 4 */
 415                 return 8;
 416
 417         /* Timer queries, present when the clock frequency is non zero. */
 418         case PIPE_CAP_QUERY_TIME_ELAPSED:
 419                 return rscreen->info.r600_clock_crystal_freq != 0;
 420
 421         case PIPE_CAP_MIN_TEXEL_OFFSET:
 422                 return -8;
 423
 424         case PIPE_CAP_MAX_TEXEL_OFFSET:
 425                 return 7;
 426         }
 427         return 0;
 428 }
 429
 430 static float r600_get_paramf(struct pipe_screen* pscreen,
 431                              enum pipe_capf param)
 432 {
 433         switch (param) {
 434         case PIPE_CAPF_MAX_LINE_WIDTH:
 435         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 436         case PIPE_CAPF_MAX_POINT_WIDTH:
 437         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 438                 return 16384.0f;
 439         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 440                 return 16.0f;
 441         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 442                 return 16.0f;
 443         case PIPE_CAPF_GUARD_BAND_LEFT:
 444         case PIPE_CAPF_GUARD_BAND_TOP:
 445         case PIPE_CAPF_GUARD_BAND_RIGHT:
 446         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 447                 return 0.0f;
 448         }
 449         return 0.0f;
 450 }
 451
 452 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 453 {
 454         switch(shader)
 455         {
 456         case PIPE_SHADER_FRAGMENT:
 457         case PIPE_SHADER_VERTEX:
 458                 break;
 459         case PIPE_SHADER_GEOMETRY:
 460                 /* TODO: support and enable geometry programs */
 461                 return 0;
 462         case PIPE_SHADER_COMPUTE:
 463                 switch (param) {
 464                 case PIPE_SHADER_CAP_PREFERRED_IR:
 465                         return PIPE_SHADER_IR_LLVM;
 466                 default:
 467                         return 0;
 468                 }
 469         default:
 470                 /* TODO: support tessellation */
 471                 return 0;
 472         }
 473
 474         switch (param) {
 475         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 476         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 477         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 478         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 479                 return 16384;
 480         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 481                 return 32;
 482         case PIPE_SHADER_CAP_MAX_INPUTS:
 483                 return 32;
 484         case PIPE_SHADER_CAP_MAX_TEMPS:
 485                 return 256; /* Max native temporaries. */
 486         case PIPE_SHADER_CAP_MAX_ADDRS:
 487                 /* FIXME Isn't this equal to TEMPS? */
 488                 return 1; /* Max native address registers */
 489         case PIPE_SHADER_CAP_MAX_CONSTS:
 490                 return 4096; /* actually only memory limits this */
 491         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 492                 return 1;
 493         case PIPE_SHADER_CAP_MAX_PREDS:
 494                 return 0; /* FIXME */
 495         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 496                 return 1;
 497         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 498                 return 0;
 499         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 500         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 501         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 502         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 503                 return 1;
 504         case PIPE_SHADER_CAP_INTEGERS:
 505                 return 1;
 506         case PIPE_SHADER_CAP_SUBROUTINES:
 507                 return 0;
 508         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 509                 return 16;
 510         case PIPE_SHADER_CAP_PREFERRED_IR:
 511                 return PIPE_SHADER_IR_TGSI;
 512         }
 513         return 0;
 514 }
 515
 516 static int r600_get_video_param(struct pipe_screen *screen,
 517                                 enum pipe_video_profile profile,
 518                                 enum pipe_video_cap param)
 519 {
 520         switch (param) {
 521         case PIPE_VIDEO_CAP_SUPPORTED:
 522                 return vl_profile_supported(screen, profile);
 523         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 524                 return 1;
 525         case PIPE_VIDEO_CAP_MAX_WIDTH:
 526         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 527                 return vl_video_buffer_max_size(screen);
 528         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 529                 return PIPE_FORMAT_NV12;
 530         default:
 531                 return 0;
 532         }
 533 }
 534
 535 static int r600_get_compute_param(struct pipe_screen *screen,
 536         enum pipe_compute_cap param,
 537         void *ret)
 538 {
 539         struct r600_screen *rscreen = (struct r600_screen *)screen;
 540         //TODO: select these params by asic
 541         switch (param) {
 542         case PIPE_COMPUTE_CAP_IR_TARGET: {
 543                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 544                 if (ret) {
 545                         sprintf(ret, "%s-r600--", gpu);
 546                 }
 547                 return (8 + strlen(gpu)) * sizeof(char);
 548         }
 549         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 550                 if (ret) {
 551                         uint64_t * grid_dimension = ret;
 552                         grid_dimension[0] = 3;
 553                 }
 554                 return 1 * sizeof(uint64_t);
 555         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 556                 if (ret) {
 557                         uint64_t * grid_size = ret;
 558                         grid_size[0] = 65535;
 559                         grid_size[1] = 65535;
 560                         grid_size[2] = 1;
 561                 }
 562                 return 3 * sizeof(uint64_t) ;
 563
 564         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 565                 if (ret) {
 566                         uint64_t * block_size = ret;
 567                         block_size[0] = 256;
 568                         block_size[1] = 256;
 569                         block_size[2] = 256;
 570                 }
 571                 return 3 * sizeof(uint64_t);
 572         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 573                 if (ret) {
 574                         uint64_t * max_threads_per_block = ret;
 575                         *max_threads_per_block = 256;
 576                 }
 577                 return sizeof(uint64_t);
 578
 579         default:
 580                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 581                 return 0;
 582         }
 583 }
 584
 585 static void r600_destroy_screen(struct pipe_screen* pscreen)
 586 {
 587         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 588
 589         if (rscreen == NULL)
 590                 return;
 591
 592         if (rscreen->fences.bo) {
 593                 struct r600_fence_block *entry, *tmp;
 594
 595                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 596                         LIST_DEL(&entry->head);
 597                         FREE(entry);
 598                 }
 599
 600                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 601                 si_resource_reference(&rscreen->fences.bo, NULL);
 602         }
 603
 604 #if R600_TRACE_CS
 605         if (rscreen->trace_bo) {
 606                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 607                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 608         }
 609 #endif
 610
 611         pipe_mutex_destroy(rscreen->fences.mutex);
 612
 613         rscreen->ws->destroy(rscreen->ws);
 614         FREE(rscreen);
 615 }
 616
 617 static void r600_fence_reference(struct pipe_screen *pscreen,
 618                                  struct pipe_fence_handle **ptr,
 619                                  struct pipe_fence_handle *fence)
 620 {
 621         struct r600_fence **oldf = (struct r600_fence**)ptr;
 622         struct r600_fence *newf = (struct r600_fence*)fence;
 623
 624         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 625                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 626                 pipe_mutex_lock(rscreen->fences.mutex);
 627                 si_resource_reference(&(*oldf)->sleep_bo, NULL);
 628                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 629                 pipe_mutex_unlock(rscreen->fences.mutex);
 630         }
 631
 632         *ptr = fence;
 633 }
 634
 635 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 636                                     struct pipe_fence_handle *fence)
 637 {
 638         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 639         struct r600_fence *rfence = (struct r600_fence*)fence;
 640
 641         return rscreen->fences.data[rfence->index] != 0;
 642 }
 643
 644 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 645                                  struct pipe_fence_handle *fence,
 646                                  uint64_t timeout)
 647 {
 648         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 649         struct r600_fence *rfence = (struct r600_fence*)fence;
 650         int64_t start_time = 0;
 651         unsigned spins = 0;
 652
 653         if (timeout != PIPE_TIMEOUT_INFINITE) {
 654                 start_time = os_time_get();
 655
 656                 /* Convert to microseconds. */
 657                 timeout /= 1000;
 658         }
 659
 660         while (rscreen->fences.data[rfence->index] == 0) {
 661                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 662                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 663                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 664                         break;
 665                 }
 666
 667                 /* The dummy BO will be busy until the CS including the fence has completed, or
 668                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 669                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 670                         break;
 671
 672                 if (++spins % 256)
 673                         continue;
 674 #ifdef PIPE_OS_UNIX
 675                 sched_yield();
 676 #else
 677                 os_time_sleep(10);
 678 #endif
 679                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 680                     os_time_get() - start_time >= timeout) {
 681                         break;
 682                 }
 683         }
 684
 685         return rscreen->fences.data[rfence->index] != 0;
 686 }
 687
 688 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 689 {
 690         switch (tiling_config & 0xf) {
 691         case 0:
 692                 rscreen->tiling_info.num_channels = 1;
 693                 break;
 694         case 1:
 695                 rscreen->tiling_info.num_channels = 2;
 696                 break;
 697         case 2:
 698                 rscreen->tiling_info.num_channels = 4;
 699                 break;
 700         case 3:
 701                 rscreen->tiling_info.num_channels = 8;
 702                 break;
 703         default:
 704                 return -EINVAL;
 705         }
 706
 707         switch ((tiling_config & 0xf0) >> 4) {
 708         case 0:
 709                 rscreen->tiling_info.num_banks = 4;
 710                 break;
 711         case 1:
 712                 rscreen->tiling_info.num_banks = 8;
 713                 break;
 714         case 2:
 715                 rscreen->tiling_info.num_banks = 16;
 716                 break;
 717         default:
 718                 return -EINVAL;
 719         }
 720
 721         switch ((tiling_config & 0xf00) >> 8) {
 722         case 0:
 723                 rscreen->tiling_info.group_bytes = 256;
 724                 break;
 725         case 1:
 726                 rscreen->tiling_info.group_bytes = 512;
 727                 break;
 728         default:
 729                 return -EINVAL;
 730         }
 731         return 0;
 732 }
 733
 734 static int r600_init_tiling(struct r600_screen *rscreen)
 735 {
 736         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 737
 738         /* set default group bytes, overridden by tiling info ioctl */
 739         rscreen->tiling_info.group_bytes = 512;
 740
 741         if (!tiling_config)
 742                 return 0;
 743
 744         return evergreen_interpret_tiling(rscreen, tiling_config);
 745 }
 746
 747 static unsigned radeon_family_from_device(unsigned device)
 748 {
 749         switch (device) {
 750 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 751 #include "pci_ids/radeonsi_pci_ids.h"
 752 #undef CHIPSET
 753         default:
 754                 return CHIP_UNKNOWN;
 755         }
 756 }
 757
 758 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 759 {
 760         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 761         if (rscreen == NULL) {
 762                 return NULL;
 763         }
 764
 765         rscreen->ws = ws;
 766         ws->query_info(ws, &rscreen->info);
 767
 768         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 769         if (rscreen->family == CHIP_UNKNOWN) {
 770                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 771                 FREE(rscreen);
 772                 return NULL;
 773         }
 774
 775         /* setup class */
 776         if (rscreen->family >= CHIP_TAHITI) {
 777                 rscreen->chip_class = TAHITI;
 778         } else {
 779                 fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family);
 780                 FREE(rscreen);
 781                 return NULL;
 782         }
 783
 784         if (r600_init_tiling(rscreen)) {
 785                 FREE(rscreen);
 786                 return NULL;
 787         }
 788
 789         rscreen->screen.destroy = r600_destroy_screen;
 790         rscreen->screen.get_name = r600_get_name;
 791         rscreen->screen.get_vendor = r600_get_vendor;
 792         rscreen->screen.get_param = r600_get_param;
 793         rscreen->screen.get_shader_param = r600_get_shader_param;
 794         rscreen->screen.get_paramf = r600_get_paramf;
 795         rscreen->screen.get_compute_param = r600_get_compute_param;
 796         rscreen->screen.is_format_supported = si_is_format_supported;
 797         rscreen->screen.context_create = r600_create_context;
 798         rscreen->screen.fence_reference = r600_fence_reference;
 799         rscreen->screen.fence_signalled = r600_fence_signalled;
 800         rscreen->screen.fence_finish = r600_fence_finish;
 801         r600_init_screen_resource_functions(&rscreen->screen);
 802
 803         if (rscreen->info.has_uvd) {
 804                 rscreen->screen.get_video_param = ruvd_get_video_param;
 805                 rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
 806         } else {
 807                 rscreen->screen.get_video_param = r600_get_video_param;
 808                 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 809         }
 810
 811         util_format_s3tc_init();
 812
 813         rscreen->fences.bo = NULL;
 814         rscreen->fences.data = NULL;
 815         rscreen->fences.next_index = 0;
 816         LIST_INITHEAD(&rscreen->fences.pool);
 817         LIST_INITHEAD(&rscreen->fences.blocks);
 818         pipe_mutex_init(rscreen->fences.mutex);
 819
 820 #if R600_TRACE_CS
 821         rscreen->cs_count = 0;
 822         if (rscreen->info.drm_minor >= 28) {
 823                 rscreen->trace_bo = (struct si_resource*)pipe_buffer_create(&rscreen->screen,
 824                                                                                 PIPE_BIND_CUSTOM,
 825                                                                                 PIPE_USAGE_STAGING,
 826                                                                                 4096);
 827                 if (rscreen->trace_bo) {
 828                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 829                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 830                 }
 831         }
 832 #endif
 833
 834         return &rscreen->screen;
 835 }