src/gallium/drivers/radeonsi/radeonsi_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_transfer.h"
  35 #include "util/u_surface.h"
  36 #include "util/u_pack_color.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_inlines.h"
  39 #include "util/u_simple_shaders.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "radeonsi_pipe.h"
  46 #include "radeon/radeon_uvd.h"
  47 #include "r600.h"
  48 #include "sid.h"
  49 #include "r600_resource.h"
  50 #include "radeonsi_pipe.h"
  51 #include "si_state.h"
  52 #include "../radeon/r600_cs.h"
  53
  54 /*
  55  * pipe_context
  56  */
  57 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
  58                     unsigned flags)
  59 {
  60         struct r600_context *rctx = (struct r600_context *)ctx;
  61         struct pipe_query *render_cond = NULL;
  62         boolean render_cond_cond = FALSE;
  63         unsigned render_cond_mode = 0;
  64
  65         if (fence) {
  66                 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
  67         }
  68
  69         /* Disable render condition. */
  70         if (rctx->current_render_cond) {
  71                 render_cond = rctx->current_render_cond;
  72                 render_cond_cond = rctx->current_render_cond_cond;
  73                 render_cond_mode = rctx->current_render_cond_mode;
  74                 ctx->render_condition(ctx, NULL, FALSE, 0);
  75         }
  76
  77         si_context_flush(rctx, flags);
  78
  79         /* Re-enable render condition. */
  80         if (render_cond) {
  81                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  82         }
  83 }
  84
  85 static void r600_flush_from_st(struct pipe_context *ctx,
  86                                struct pipe_fence_handle **fence,
  87                                unsigned flags)
  88 {
  89         radeonsi_flush(ctx, fence,
  90                        flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
  91 }
  92
  93 static void r600_flush_from_winsys(void *ctx, unsigned flags)
  94 {
  95         radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
  96 }
  97
  98 static void r600_destroy_context(struct pipe_context *context)
  99 {
 100         struct r600_context *rctx = (struct r600_context *)context;
 101
 102         si_release_all_descriptors(rctx);
 103
 104         pipe_resource_reference(&rctx->null_const_buf.buffer, NULL);
 105         r600_resource_reference(&rctx->border_color_table, NULL);
 106
 107         if (rctx->dummy_pixel_shader) {
 108                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 109         }
 110         for (int i = 0; i < 8; i++) {
 111                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_depth_stencil[i]);
 112                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_depth[i]);
 113                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_stencil[i]);
 114         }
 115         rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush_inplace);
 116         rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
 117         rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 118         util_unreference_framebuffer_state(&rctx->framebuffer);
 119
 120         util_blitter_destroy(rctx->blitter);
 121
 122         if (rctx->uploader) {
 123                 u_upload_destroy(rctx->uploader);
 124         }
 125         util_slab_destroy(&rctx->pool_transfers);
 126
 127         r600_common_context_cleanup(&rctx->b);
 128         FREE(rctx);
 129 }
 130
 131 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 132 {
 133         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 134         struct r600_screen* rscreen = (struct r600_screen *)screen;
 135         int shader, i;
 136
 137         if (rctx == NULL)
 138                 return NULL;
 139
 140         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 141                 goto fail;
 142
 143         rctx->b.b.screen = screen;
 144         rctx->b.b.priv = priv;
 145         rctx->b.b.destroy = r600_destroy_context;
 146         rctx->b.b.flush = r600_flush_from_st;
 147
 148         /* Easy accessing of screen/winsys. */
 149         rctx->screen = rscreen;
 150
 151         si_init_blit_functions(rctx);
 152         r600_init_query_functions(rctx);
 153         r600_init_context_resource_functions(rctx);
 154         si_init_compute_functions(rctx);
 155
 156         if (rscreen->b.info.has_uvd) {
 157                 rctx->b.b.create_video_codec = radeonsi_uvd_create_decoder;
 158                 rctx->b.b.create_video_buffer = radeonsi_video_buffer_create;
 159         } else {
 160                 rctx->b.b.create_video_codec = vl_create_decoder;
 161                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 162         }
 163
 164         rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
 165         rctx->b.rings.gfx.flush = r600_flush_from_winsys;
 166
 167         si_init_all_descriptors(rctx);
 168
 169         /* Initialize cache_flush. */
 170         rctx->cache_flush = si_atom_cache_flush;
 171         rctx->atoms.cache_flush = &rctx->cache_flush;
 172
 173         rctx->atoms.streamout_begin = &rctx->b.streamout.begin_atom;
 174
 175         switch (rctx->b.chip_class) {
 176         case SI:
 177         case CIK:
 178                 si_init_state_functions(rctx);
 179                 LIST_INITHEAD(&rctx->active_nontimer_query_list);
 180                 rctx->max_db = 8;
 181                 si_init_config(rctx);
 182                 break;
 183         default:
 184                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 185                 goto fail;
 186         }
 187
 188         rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
 189
 190         util_slab_create(&rctx->pool_transfers,
 191                          sizeof(struct pipe_transfer), 64,
 192                          UTIL_SLAB_SINGLETHREADED);
 193
 194         rctx->uploader = u_upload_create(&rctx->b.b, 1024 * 1024, 256,
 195                                          PIPE_BIND_INDEX_BUFFER |
 196                                          PIPE_BIND_CONSTANT_BUFFER);
 197         if (!rctx->uploader)
 198                 goto fail;
 199
 200         rctx->blitter = util_blitter_create(&rctx->b.b);
 201         if (rctx->blitter == NULL)
 202                 goto fail;
 203
 204         rctx->dummy_pixel_shader =
 205                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 206                                                      TGSI_SEMANTIC_GENERIC,
 207                                                      TGSI_INTERPOLATE_CONSTANT);
 208         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 209
 210         /* these must be last */
 211         si_begin_new_cs(rctx);
 212         si_get_backend_mask(rctx);
 213
 214         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 215          * with a NULL buffer). We need to use a dummy buffer instead. */
 216         if (rctx->b.chip_class == CIK) {
 217                 rctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 218                                                                  PIPE_USAGE_STATIC, 16);
 219                 rctx->null_const_buf.buffer_size = rctx->null_const_buf.buffer->width0;
 220
 221                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 222                         for (i = 0; i < NUM_CONST_BUFFERS; i++) {
 223                                 rctx->b.b.set_constant_buffer(&rctx->b.b, shader, i,
 224                                                               &rctx->null_const_buf);
 225                         }
 226                 }
 227
 228                 /* Clear the NULL constant buffer, because loads should return zeros. */
 229                 rctx->b.clear_buffer(&rctx->b.b, rctx->null_const_buf.buffer, 0,
 230                                      rctx->null_const_buf.buffer->width0, 0);
 231         }
 232
 233         return &rctx->b.b;
 234 fail:
 235         r600_destroy_context(&rctx->b.b);
 236         return NULL;
 237 }
 238
 239 /*
 240  * pipe_screen
 241  */
 242 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 243 {
 244         return "X.Org";
 245 }
 246
 247 const char *r600_get_llvm_processor_name(enum radeon_family family)
 248 {
 249         switch (family) {
 250                 case CHIP_TAHITI: return "tahiti";
 251                 case CHIP_PITCAIRN: return "pitcairn";
 252                 case CHIP_VERDE: return "verde";
 253                 case CHIP_OLAND: return "oland";
 254 #if HAVE_LLVM <= 0x0303
 255                 default: return "SI";
 256 #else
 257                 case CHIP_HAINAN: return "hainan";
 258                 case CHIP_BONAIRE: return "bonaire";
 259                 case CHIP_KABINI: return "kabini";
 260                 case CHIP_KAVERI: return "kaveri";
 261                 default: return "";
 262 #endif
 263         }
 264 }
 265
 266 static const char *r600_get_family_name(enum radeon_family family)
 267 {
 268         switch(family) {
 269         case CHIP_TAHITI: return "AMD TAHITI";
 270         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 271         case CHIP_VERDE: return "AMD CAPE VERDE";
 272         case CHIP_OLAND: return "AMD OLAND";
 273         case CHIP_HAINAN: return "AMD HAINAN";
 274         case CHIP_BONAIRE: return "AMD BONAIRE";
 275         case CHIP_KAVERI: return "AMD KAVERI";
 276         case CHIP_KABINI: return "AMD KABINI";
 277         default: return "AMD unknown";
 278         }
 279 }
 280
 281 static const char* r600_get_name(struct pipe_screen* pscreen)
 282 {
 283         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 284
 285         return r600_get_family_name(rscreen->b.family);
 286 }
 287
 288 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 289 {
 290         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 291         bool has_streamout = HAVE_LLVM >= 0x0304;
 292
 293         switch (param) {
 294         /* Supported features (boolean caps). */
 295         case PIPE_CAP_TWO_SIDED_STENCIL:
 296         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 297         case PIPE_CAP_ANISOTROPIC_FILTER:
 298         case PIPE_CAP_POINT_SPRITE:
 299         case PIPE_CAP_OCCLUSION_QUERY:
 300         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 301         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 302         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 303         case PIPE_CAP_TEXTURE_SWIZZLE:
 304         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 305         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 306         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 307         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 308         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 309         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 310         case PIPE_CAP_SM3:
 311         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 312         case PIPE_CAP_PRIMITIVE_RESTART:
 313         case PIPE_CAP_CONDITIONAL_RENDER:
 314         case PIPE_CAP_TEXTURE_BARRIER:
 315         case PIPE_CAP_INDEP_BLEND_ENABLE:
 316         case PIPE_CAP_INDEP_BLEND_FUNC:
 317         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 318         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 319         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 320         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 321         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 322         case PIPE_CAP_USER_INDEX_BUFFERS:
 323         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 324         case PIPE_CAP_START_INSTANCE:
 325         case PIPE_CAP_NPOT_TEXTURES:
 326         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 327         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 328         case PIPE_CAP_TGSI_INSTANCEID:
 329         case PIPE_CAP_COMPUTE:
 330                 return 1;
 331
 332         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 333                 return HAVE_LLVM >= 0x0304 && rscreen->b.chip_class == SI;
 334
 335         case PIPE_CAP_TGSI_TEXCOORD:
 336                 return 0;
 337
 338         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 339                 return 64;
 340
 341         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 342                 return 256;
 343
 344         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 345                 return 130;
 346
 347         /* Unsupported features. */
 348         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 349         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 350         case PIPE_CAP_SCALED_RESOLVE:
 351         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 352         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 353         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 354         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 355         case PIPE_CAP_USER_VERTEX_BUFFERS:
 356         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 357         case PIPE_CAP_CUBE_MAP_ARRAY:
 358         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 359         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 360         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 361                 return 0;
 362
 363         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 364                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 365
 366         /* Stream output. */
 367         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 368                 return has_streamout ? 4 : 0;
 369         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 370                 return has_streamout ? 1 : 0;
 371         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 372         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 373                 return has_streamout ? 32*4 : 0;
 374
 375         /* Texturing. */
 376         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 377         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 378         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 379                         return 15;
 380         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 381                 return 16384;
 382         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 383                 return 32;
 384
 385         /* Render targets. */
 386         case PIPE_CAP_MAX_RENDER_TARGETS:
 387                 /* FIXME some r6xx are buggy and can only do 4 */
 388                 return 8;
 389
 390         case PIPE_CAP_MAX_VIEWPORTS:
 391                 return 1;
 392
 393         /* Timer queries, present when the clock frequency is non zero. */
 394         case PIPE_CAP_QUERY_TIMESTAMP:
 395         case PIPE_CAP_QUERY_TIME_ELAPSED:
 396                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 397
 398         case PIPE_CAP_MIN_TEXEL_OFFSET:
 399                 return -8;
 400
 401         case PIPE_CAP_MAX_TEXEL_OFFSET:
 402                 return 7;
 403         case PIPE_CAP_ENDIANNESS:
 404                 return PIPE_ENDIAN_LITTLE;
 405         }
 406         return 0;
 407 }
 408
 409 static float r600_get_paramf(struct pipe_screen* pscreen,
 410                              enum pipe_capf param)
 411 {
 412         switch (param) {
 413         case PIPE_CAPF_MAX_LINE_WIDTH:
 414         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 415         case PIPE_CAPF_MAX_POINT_WIDTH:
 416         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 417                 return 16384.0f;
 418         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 419                 return 16.0f;
 420         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 421                 return 16.0f;
 422         case PIPE_CAPF_GUARD_BAND_LEFT:
 423         case PIPE_CAPF_GUARD_BAND_TOP:
 424         case PIPE_CAPF_GUARD_BAND_RIGHT:
 425         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 426                 return 0.0f;
 427         }
 428         return 0.0f;
 429 }
 430
 431 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 432 {
 433         switch(shader)
 434         {
 435         case PIPE_SHADER_FRAGMENT:
 436         case PIPE_SHADER_VERTEX:
 437                 break;
 438         case PIPE_SHADER_GEOMETRY:
 439                 /* TODO: support and enable geometry programs */
 440                 return 0;
 441         case PIPE_SHADER_COMPUTE:
 442                 switch (param) {
 443                 case PIPE_SHADER_CAP_PREFERRED_IR:
 444                         return PIPE_SHADER_IR_LLVM;
 445                 default:
 446                         return 0;
 447                 }
 448         default:
 449                 /* TODO: support tessellation */
 450                 return 0;
 451         }
 452
 453         switch (param) {
 454         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 455         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 456         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 457         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 458                 return 16384;
 459         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 460                 return 32;
 461         case PIPE_SHADER_CAP_MAX_INPUTS:
 462                 return 32;
 463         case PIPE_SHADER_CAP_MAX_TEMPS:
 464                 return 256; /* Max native temporaries. */
 465         case PIPE_SHADER_CAP_MAX_ADDRS:
 466                 /* FIXME Isn't this equal to TEMPS? */
 467                 return 1; /* Max native address registers */
 468         case PIPE_SHADER_CAP_MAX_CONSTS:
 469                 return 4096; /* actually only memory limits this */
 470         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 471                 return NUM_PIPE_CONST_BUFFERS;
 472         case PIPE_SHADER_CAP_MAX_PREDS:
 473                 return 0; /* FIXME */
 474         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 475                 return 1;
 476         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 477                 return 0;
 478         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 479         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 480         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 481         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 482                 return 1;
 483         case PIPE_SHADER_CAP_INTEGERS:
 484                 return 1;
 485         case PIPE_SHADER_CAP_SUBROUTINES:
 486                 return 0;
 487         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 488                 return 16;
 489         case PIPE_SHADER_CAP_PREFERRED_IR:
 490                 return PIPE_SHADER_IR_TGSI;
 491         }
 492         return 0;
 493 }
 494
 495 static int r600_get_video_param(struct pipe_screen *screen,
 496                                 enum pipe_video_profile profile,
 497                                 enum pipe_video_entrypoint entrypoint,
 498                                 enum pipe_video_cap param)
 499 {
 500         switch (param) {
 501         case PIPE_VIDEO_CAP_SUPPORTED:
 502                 return vl_profile_supported(screen, profile, entrypoint);
 503         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 504                 return 1;
 505         case PIPE_VIDEO_CAP_MAX_WIDTH:
 506         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 507                 return vl_video_buffer_max_size(screen);
 508         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 509                 return PIPE_FORMAT_NV12;
 510         case PIPE_VIDEO_CAP_MAX_LEVEL:
 511                 return vl_level_supported(screen, profile);
 512         default:
 513                 return 0;
 514         }
 515 }
 516
 517 static int r600_get_compute_param(struct pipe_screen *screen,
 518         enum pipe_compute_cap param,
 519         void *ret)
 520 {
 521         struct r600_screen *rscreen = (struct r600_screen *)screen;
 522         //TODO: select these params by asic
 523         switch (param) {
 524         case PIPE_COMPUTE_CAP_IR_TARGET: {
 525                 const char *gpu = r600_get_llvm_processor_name(rscreen->b.family);
 526                 if (ret) {
 527                         sprintf(ret, "%s-r600--", gpu);
 528                 }
 529                 return (8 + strlen(gpu)) * sizeof(char);
 530         }
 531         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 532                 if (ret) {
 533                         uint64_t * grid_dimension = ret;
 534                         grid_dimension[0] = 3;
 535                 }
 536                 return 1 * sizeof(uint64_t);
 537         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 538                 if (ret) {
 539                         uint64_t * grid_size = ret;
 540                         grid_size[0] = 65535;
 541                         grid_size[1] = 65535;
 542                         grid_size[2] = 1;
 543                 }
 544                 return 3 * sizeof(uint64_t) ;
 545
 546         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 547                 if (ret) {
 548                         uint64_t * block_size = ret;
 549                         block_size[0] = 256;
 550                         block_size[1] = 256;
 551                         block_size[2] = 256;
 552                 }
 553                 return 3 * sizeof(uint64_t);
 554         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 555                 if (ret) {
 556                         uint64_t * max_threads_per_block = ret;
 557                         *max_threads_per_block = 256;
 558                 }
 559                 return sizeof(uint64_t);
 560
 561         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 562                 if (ret) {
 563                         uint64_t *max_global_size = ret;
 564                         /* XXX: Not sure what to put here. */
 565                         *max_global_size = 2000000000;
 566                 }
 567                 return sizeof(uint64_t);
 568         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 569                 if (ret) {
 570                         uint64_t *max_local_size = ret;
 571                         /* Value reported by the closed source driver. */
 572                         *max_local_size = 32768;
 573                 }
 574                 return sizeof(uint64_t);
 575         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 576                 if (ret) {
 577                         uint64_t *max_input_size = ret;
 578                         /* Value reported by the closed source driver. */
 579                         *max_input_size = 1024;
 580                 }
 581                 return sizeof(uint64_t);
 582         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 583                 if (ret) {
 584                         uint64_t max_global_size;
 585                         uint64_t *max_mem_alloc_size = ret;
 586                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 587                         *max_mem_alloc_size = max_global_size / 4;
 588                 }
 589                 return sizeof(uint64_t);
 590         default:
 591                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 592                 return 0;
 593         }
 594 }
 595
 596 static void r600_destroy_screen(struct pipe_screen* pscreen)
 597 {
 598         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 599
 600         if (rscreen == NULL)
 601                 return;
 602
 603         if (!radeon_winsys_unref(rscreen->b.ws))
 604                 return;
 605
 606         r600_common_screen_cleanup(&rscreen->b);
 607
 608 #if R600_TRACE_CS
 609         if (rscreen->trace_bo) {
 610                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 611                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 612         }
 613 #endif
 614
 615         rscreen->b.ws->destroy(rscreen->b.ws);
 616         FREE(rscreen);
 617 }
 618
 619 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 620 {
 621         struct r600_screen *rscreen = (struct r600_screen*)screen;
 622
 623         return 1000000 * rscreen->b.ws->query_value(rscreen->b.ws, RADEON_TIMESTAMP) /
 624                 rscreen->b.info.r600_clock_crystal_freq;
 625 }
 626
 627 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 628 {
 629         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 630         if (rscreen == NULL) {
 631                 return NULL;
 632         }
 633
 634         ws->query_info(ws, &rscreen->b.info);
 635
 636         /* Set functions first. */
 637         rscreen->b.b.context_create = r600_create_context;
 638         rscreen->b.b.destroy = r600_destroy_screen;
 639         rscreen->b.b.get_name = r600_get_name;
 640         rscreen->b.b.get_vendor = r600_get_vendor;
 641         rscreen->b.b.get_param = r600_get_param;
 642         rscreen->b.b.get_shader_param = r600_get_shader_param;
 643         rscreen->b.b.get_paramf = r600_get_paramf;
 644         rscreen->b.b.get_compute_param = r600_get_compute_param;
 645         rscreen->b.b.get_timestamp = r600_get_timestamp;
 646         rscreen->b.b.is_format_supported = si_is_format_supported;
 647         if (rscreen->b.info.has_uvd) {
 648                 rscreen->b.b.get_video_param = ruvd_get_video_param;
 649                 rscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
 650         } else {
 651                 rscreen->b.b.get_video_param = r600_get_video_param;
 652                 rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
 653         }
 654         r600_init_screen_resource_functions(&rscreen->b.b);
 655
 656         if (!r600_common_screen_init(&rscreen->b, ws)) {
 657                 FREE(rscreen);
 658                 return NULL;
 659         }
 660
 661         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 662                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 663
 664 #if R600_TRACE_CS
 665         rscreen->cs_count = 0;
 666         if (rscreen->info.drm_minor >= 28) {
 667                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
 668                                                                                 PIPE_BIND_CUSTOM,
 669                                                                                 PIPE_USAGE_STAGING,
 670                                                                                 4096);
 671                 if (rscreen->trace_bo) {
 672                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 673                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 674                 }
 675         }
 676 #endif
 677
 678         /* Create the auxiliary context. This must be done last. */
 679         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 680
 681         return &rscreen->b.b;
 682 }