2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31 #include "util/u_blitter.h"
32 #include "util/u_double_list.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_transfer.h"
36 #include "util/u_surface.h"
37 #include "util/u_pack_color.h"
38 #include "util/u_memory.h"
39 #include "util/u_inlines.h"
40 #include "util/u_simple_shaders.h"
41 #include "util/u_upload_mgr.h"
42 #include "vl/vl_decoder.h"
43 #include "vl/vl_video_buffer.h"
44 #include "os/os_time.h"
45 #include "pipebuffer/pb_buffer.h"
46 #include "radeonsi_pipe.h"
47 #include "radeon/radeon_uvd.h"
50 #include "r600_resource.h"
51 #include "radeonsi_pipe.h"
52 #include "r600_hw_context_priv.h"
58 static struct r600_fence
*r600_create_fence(struct r600_context
*rctx
)
60 struct r600_screen
*rscreen
= rctx
->screen
;
61 struct r600_fence
*fence
= NULL
;
63 pipe_mutex_lock(rscreen
->fences
.mutex
);
65 if (!rscreen
->fences
.bo
) {
66 /* Create the shared buffer object */
67 rscreen
->fences
.bo
= si_resource_create_custom(&rscreen
->screen
,
70 if (!rscreen
->fences
.bo
) {
71 R600_ERR("r600: failed to create bo for fence objects\n");
74 rscreen
->fences
.data
= rctx
->ws
->buffer_map(rscreen
->fences
.bo
->cs_buf
,
76 PIPE_TRANSFER_READ_WRITE
);
79 if (!LIST_IS_EMPTY(&rscreen
->fences
.pool
)) {
80 struct r600_fence
*entry
;
82 /* Try to find a freed fence that has been signalled */
83 LIST_FOR_EACH_ENTRY(entry
, &rscreen
->fences
.pool
, head
) {
84 if (rscreen
->fences
.data
[entry
->index
] != 0) {
85 LIST_DELINIT(&entry
->head
);
93 /* Allocate a new fence */
94 struct r600_fence_block
*block
;
97 if ((rscreen
->fences
.next_index
+ 1) >= 1024) {
98 R600_ERR("r600: too many concurrent fences\n");
102 index
= rscreen
->fences
.next_index
++;
104 if (!(index
% FENCE_BLOCK_SIZE
)) {
105 /* Allocate a new block */
106 block
= CALLOC_STRUCT(r600_fence_block
);
110 LIST_ADD(&block
->head
, &rscreen
->fences
.blocks
);
112 block
= LIST_ENTRY(struct r600_fence_block
, rscreen
->fences
.blocks
.next
, head
);
115 fence
= &block
->fences
[index
% FENCE_BLOCK_SIZE
];
116 fence
->index
= index
;
119 pipe_reference_init(&fence
->reference
, 1);
121 rscreen
->fences
.data
[fence
->index
] = 0;
122 si_context_emit_fence(rctx
, rscreen
->fences
.bo
, fence
->index
, 1);
124 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
125 fence
->sleep_bo
= si_resource_create_custom(&rctx
->screen
->screen
, PIPE_USAGE_STAGING
, 1);
127 /* Add the fence as a dummy relocation. */
128 r600_context_bo_reloc(rctx
, fence
->sleep_bo
, RADEON_USAGE_READWRITE
);
131 pipe_mutex_unlock(rscreen
->fences
.mutex
);
136 void radeonsi_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
139 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
140 struct r600_fence
**rfence
= (struct r600_fence
**)fence
;
141 struct pipe_query
*render_cond
= NULL
;
142 boolean render_cond_cond
= FALSE
;
143 unsigned render_cond_mode
= 0;
146 *rfence
= r600_create_fence(rctx
);
148 /* Disable render condition. */
149 if (rctx
->current_render_cond
) {
150 render_cond
= rctx
->current_render_cond
;
151 render_cond_cond
= rctx
->current_render_cond_cond
;
152 render_cond_mode
= rctx
->current_render_cond_mode
;
153 ctx
->render_condition(ctx
, NULL
, FALSE
, 0);
156 si_context_flush(rctx
, flags
);
158 /* Re-enable render condition. */
160 ctx
->render_condition(ctx
, render_cond
, render_cond_cond
, render_cond_mode
);
164 static void r600_flush_from_st(struct pipe_context
*ctx
,
165 struct pipe_fence_handle
**fence
,
168 radeonsi_flush(ctx
, fence
,
169 flags
& PIPE_FLUSH_END_OF_FRAME
? RADEON_FLUSH_END_OF_FRAME
: 0);
172 static void r600_flush_from_winsys(void *ctx
, unsigned flags
)
174 radeonsi_flush((struct pipe_context
*)ctx
, NULL
, flags
);
177 static void r600_destroy_context(struct pipe_context
*context
)
179 struct r600_context
*rctx
= (struct r600_context
*)context
;
181 si_resource_reference(&rctx
->border_color_table
, NULL
);
183 if (rctx
->dummy_pixel_shader
) {
184 rctx
->context
.delete_fs_state(&rctx
->context
, rctx
->dummy_pixel_shader
);
186 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush_depth_stencil
);
187 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush_depth
);
188 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush_stencil
);
189 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush_inplace
);
190 util_unreference_framebuffer_state(&rctx
->framebuffer
);
192 util_blitter_destroy(rctx
->blitter
);
194 if (rctx
->uploader
) {
195 u_upload_destroy(rctx
->uploader
);
197 util_slab_destroy(&rctx
->pool_transfers
);
201 static struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
203 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
204 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
209 rctx
->context
.screen
= screen
;
210 rctx
->context
.priv
= priv
;
211 rctx
->context
.destroy
= r600_destroy_context
;
212 rctx
->context
.flush
= r600_flush_from_st
;
214 /* Easy accessing of screen/winsys. */
215 rctx
->screen
= rscreen
;
216 rctx
->ws
= rscreen
->ws
;
217 rctx
->family
= rscreen
->family
;
218 rctx
->chip_class
= rscreen
->chip_class
;
220 si_init_blit_functions(rctx
);
221 r600_init_query_functions(rctx
);
222 r600_init_context_resource_functions(rctx
);
223 si_init_surface_functions(rctx
);
224 si_init_compute_functions(rctx
);
226 if (rscreen
->info
.has_uvd
) {
227 rctx
->context
.create_video_decoder
= radeonsi_uvd_create_decoder
;
228 rctx
->context
.create_video_buffer
= radeonsi_video_buffer_create
;
230 rctx
->context
.create_video_decoder
= vl_create_decoder
;
231 rctx
->context
.create_video_buffer
= vl_video_buffer_create
;
234 switch (rctx
->chip_class
) {
236 si_init_state_functions(rctx
);
237 LIST_INITHEAD(&rctx
->active_query_list
);
238 rctx
->cs
= rctx
->ws
->cs_create(rctx
->ws
, RING_GFX
, NULL
);
240 si_init_config(rctx
);
243 si_init_state_functions(rctx
);
244 LIST_INITHEAD(&rctx
->active_query_list
);
245 rctx
->cs
= rctx
->ws
->cs_create(rctx
->ws
, RING_GFX
, NULL
);
247 si_init_config(rctx
);
250 R600_ERR("Unsupported chip class %d.\n", rctx
->chip_class
);
251 r600_destroy_context(&rctx
->context
);
255 rctx
->ws
->cs_set_flush_callback(rctx
->cs
, r600_flush_from_winsys
, rctx
);
257 util_slab_create(&rctx
->pool_transfers
,
258 sizeof(struct pipe_transfer
), 64,
259 UTIL_SLAB_SINGLETHREADED
);
261 rctx
->uploader
= u_upload_create(&rctx
->context
, 1024 * 1024, 256,
262 PIPE_BIND_INDEX_BUFFER
|
263 PIPE_BIND_CONSTANT_BUFFER
);
264 if (!rctx
->uploader
) {
265 r600_destroy_context(&rctx
->context
);
269 rctx
->blitter
= util_blitter_create(&rctx
->context
);
270 if (rctx
->blitter
== NULL
) {
271 r600_destroy_context(&rctx
->context
);
275 si_get_backend_mask(rctx
); /* this emits commands and must be last */
277 rctx
->dummy_pixel_shader
=
278 util_make_fragment_cloneinput_shader(&rctx
->context
, 0,
279 TGSI_SEMANTIC_GENERIC
,
280 TGSI_INTERPOLATE_CONSTANT
);
281 rctx
->context
.bind_fs_state(&rctx
->context
, rctx
->dummy_pixel_shader
);
283 return &rctx
->context
;
289 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
294 const char *r600_get_llvm_processor_name(enum radeon_family family
)
297 case CHIP_TAHITI
: return "tahiti";
298 case CHIP_PITCAIRN
: return "pitcairn";
299 case CHIP_VERDE
: return "verde";
300 case CHIP_OLAND
: return "oland";
301 case CHIP_HAINAN
: return "hainan";
302 case CHIP_BONAIRE
: return "bonaire";
303 case CHIP_KABINI
: return "kabini";
304 case CHIP_KAVERI
: return "kaveri";
309 static const char *r600_get_family_name(enum radeon_family family
)
312 case CHIP_TAHITI
: return "AMD TAHITI";
313 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
314 case CHIP_VERDE
: return "AMD CAPE VERDE";
315 case CHIP_OLAND
: return "AMD OLAND";
316 case CHIP_HAINAN
: return "AMD HAINAN";
317 case CHIP_BONAIRE
: return "AMD BONAIRE";
318 case CHIP_KAVERI
: return "AMD KAVERI";
319 case CHIP_KABINI
: return "AMD KABINI";
320 default: return "AMD unknown";
324 static const char* r600_get_name(struct pipe_screen
* pscreen
)
326 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
328 return r600_get_family_name(rscreen
->family
);
331 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
333 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
336 /* Supported features (boolean caps). */
337 case PIPE_CAP_TWO_SIDED_STENCIL
:
338 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
339 case PIPE_CAP_ANISOTROPIC_FILTER
:
340 case PIPE_CAP_POINT_SPRITE
:
341 case PIPE_CAP_OCCLUSION_QUERY
:
342 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
343 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
344 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
345 case PIPE_CAP_TEXTURE_SWIZZLE
:
346 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
347 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
348 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
349 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
350 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
351 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
353 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
354 case PIPE_CAP_PRIMITIVE_RESTART
:
355 case PIPE_CAP_CONDITIONAL_RENDER
:
356 case PIPE_CAP_TEXTURE_BARRIER
:
357 case PIPE_CAP_INDEP_BLEND_ENABLE
:
358 case PIPE_CAP_INDEP_BLEND_FUNC
:
359 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
360 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
361 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
362 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
363 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
364 case PIPE_CAP_USER_INDEX_BUFFERS
:
365 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
366 case PIPE_CAP_START_INSTANCE
:
367 case PIPE_CAP_NPOT_TEXTURES
:
368 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
369 case PIPE_CAP_TGSI_INSTANCEID
:
370 case PIPE_CAP_COMPUTE
:
372 case PIPE_CAP_TGSI_TEXCOORD
:
375 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
378 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
381 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
384 /* Unsupported features. */
385 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
386 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
387 case PIPE_CAP_SCALED_RESOLVE
:
388 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS
:
389 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
390 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
391 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
392 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
393 case PIPE_CAP_USER_VERTEX_BUFFERS
:
394 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
395 case PIPE_CAP_QUERY_TIMESTAMP
:
396 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
397 case PIPE_CAP_CUBE_MAP_ARRAY
:
398 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
399 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
400 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
401 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
406 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
407 return debug_get_bool_option("R600_STREAMOUT", FALSE
) ? 4 : 0;
408 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
409 return debug_get_bool_option("R600_STREAMOUT", FALSE
) ? 1 : 0;
410 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
411 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
414 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
415 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
416 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
417 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
421 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
422 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
423 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
425 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
427 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
430 /* Render targets. */
431 case PIPE_CAP_MAX_RENDER_TARGETS
:
432 /* FIXME some r6xx are buggy and can only do 4 */
435 /* Timer queries, present when the clock frequency is non zero. */
436 case PIPE_CAP_QUERY_TIME_ELAPSED
:
437 return rscreen
->info
.r600_clock_crystal_freq
!= 0;
439 case PIPE_CAP_MIN_TEXEL_OFFSET
:
442 case PIPE_CAP_MAX_TEXEL_OFFSET
:
448 static float r600_get_paramf(struct pipe_screen
* pscreen
,
449 enum pipe_capf param
)
452 case PIPE_CAPF_MAX_LINE_WIDTH
:
453 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
454 case PIPE_CAPF_MAX_POINT_WIDTH
:
455 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
457 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
459 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
461 case PIPE_CAPF_GUARD_BAND_LEFT
:
462 case PIPE_CAPF_GUARD_BAND_TOP
:
463 case PIPE_CAPF_GUARD_BAND_RIGHT
:
464 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
470 static int r600_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
474 case PIPE_SHADER_FRAGMENT
:
475 case PIPE_SHADER_VERTEX
:
477 case PIPE_SHADER_GEOMETRY
:
478 /* TODO: support and enable geometry programs */
480 case PIPE_SHADER_COMPUTE
:
482 case PIPE_SHADER_CAP_PREFERRED_IR
:
483 return PIPE_SHADER_IR_LLVM
;
488 /* TODO: support tessellation */
493 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
494 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
495 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
496 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
498 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
500 case PIPE_SHADER_CAP_MAX_INPUTS
:
502 case PIPE_SHADER_CAP_MAX_TEMPS
:
503 return 256; /* Max native temporaries. */
504 case PIPE_SHADER_CAP_MAX_ADDRS
:
505 /* FIXME Isn't this equal to TEMPS? */
506 return 1; /* Max native address registers */
507 case PIPE_SHADER_CAP_MAX_CONSTS
:
508 return 4096; /* actually only memory limits this */
509 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
511 case PIPE_SHADER_CAP_MAX_PREDS
:
512 return 0; /* FIXME */
513 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
515 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
517 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
518 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
519 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
520 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
522 case PIPE_SHADER_CAP_INTEGERS
:
524 case PIPE_SHADER_CAP_SUBROUTINES
:
526 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
528 case PIPE_SHADER_CAP_PREFERRED_IR
:
529 return PIPE_SHADER_IR_TGSI
;
534 static int r600_get_video_param(struct pipe_screen
*screen
,
535 enum pipe_video_profile profile
,
536 enum pipe_video_cap param
)
539 case PIPE_VIDEO_CAP_SUPPORTED
:
540 return vl_profile_supported(screen
, profile
);
541 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
543 case PIPE_VIDEO_CAP_MAX_WIDTH
:
544 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
545 return vl_video_buffer_max_size(screen
);
546 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
547 return PIPE_FORMAT_NV12
;
553 static int r600_get_compute_param(struct pipe_screen
*screen
,
554 enum pipe_compute_cap param
,
557 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
558 //TODO: select these params by asic
560 case PIPE_COMPUTE_CAP_IR_TARGET
: {
561 const char *gpu
= r600_get_llvm_processor_name(rscreen
->family
);
563 sprintf(ret
, "%s-r600--", gpu
);
565 return (8 + strlen(gpu
)) * sizeof(char);
567 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
569 uint64_t * grid_dimension
= ret
;
570 grid_dimension
[0] = 3;
572 return 1 * sizeof(uint64_t);
573 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
575 uint64_t * grid_size
= ret
;
576 grid_size
[0] = 65535;
577 grid_size
[1] = 65535;
580 return 3 * sizeof(uint64_t) ;
582 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
584 uint64_t * block_size
= ret
;
589 return 3 * sizeof(uint64_t);
590 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
592 uint64_t * max_threads_per_block
= ret
;
593 *max_threads_per_block
= 256;
595 return sizeof(uint64_t);
597 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
599 uint64_t *max_global_size
= ret
;
600 /* XXX: Not sure what to put here. */
601 *max_global_size
= 2000000000;
603 return sizeof(uint64_t);
605 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
607 uint64_t max_global_size
;
608 uint64_t *max_mem_alloc_size
= ret
;
609 r600_get_compute_param(screen
, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
, &max_global_size
);
610 *max_mem_alloc_size
= max_global_size
/ 4;
612 return sizeof(uint64_t);
614 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
619 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
621 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
626 if (rscreen
->fences
.bo
) {
627 struct r600_fence_block
*entry
, *tmp
;
629 LIST_FOR_EACH_ENTRY_SAFE(entry
, tmp
, &rscreen
->fences
.blocks
, head
) {
630 LIST_DEL(&entry
->head
);
634 rscreen
->ws
->buffer_unmap(rscreen
->fences
.bo
->cs_buf
);
635 si_resource_reference(&rscreen
->fences
.bo
, NULL
);
639 if (rscreen
->trace_bo
) {
640 rscreen
->ws
->buffer_unmap(rscreen
->trace_bo
->cs_buf
);
641 pipe_resource_reference((struct pipe_resource
**)&rscreen
->trace_bo
, NULL
);
645 pipe_mutex_destroy(rscreen
->fences
.mutex
);
647 rscreen
->ws
->destroy(rscreen
->ws
);
651 static void r600_fence_reference(struct pipe_screen
*pscreen
,
652 struct pipe_fence_handle
**ptr
,
653 struct pipe_fence_handle
*fence
)
655 struct r600_fence
**oldf
= (struct r600_fence
**)ptr
;
656 struct r600_fence
*newf
= (struct r600_fence
*)fence
;
658 if (pipe_reference(&(*oldf
)->reference
, &newf
->reference
)) {
659 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
660 pipe_mutex_lock(rscreen
->fences
.mutex
);
661 si_resource_reference(&(*oldf
)->sleep_bo
, NULL
);
662 LIST_ADDTAIL(&(*oldf
)->head
, &rscreen
->fences
.pool
);
663 pipe_mutex_unlock(rscreen
->fences
.mutex
);
669 static boolean
r600_fence_signalled(struct pipe_screen
*pscreen
,
670 struct pipe_fence_handle
*fence
)
672 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
673 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
675 return rscreen
->fences
.data
[rfence
->index
] != 0;
678 static boolean
r600_fence_finish(struct pipe_screen
*pscreen
,
679 struct pipe_fence_handle
*fence
,
682 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
683 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
684 int64_t start_time
= 0;
687 if (timeout
!= PIPE_TIMEOUT_INFINITE
) {
688 start_time
= os_time_get();
690 /* Convert to microseconds. */
694 while (rscreen
->fences
.data
[rfence
->index
] == 0) {
695 /* Special-case infinite timeout - wait for the dummy BO to become idle */
696 if (timeout
== PIPE_TIMEOUT_INFINITE
) {
697 rscreen
->ws
->buffer_wait(rfence
->sleep_bo
->buf
, RADEON_USAGE_READWRITE
);
701 /* The dummy BO will be busy until the CS including the fence has completed, or
702 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
703 if (!rscreen
->ws
->buffer_is_busy(rfence
->sleep_bo
->buf
, RADEON_USAGE_READWRITE
))
713 if (timeout
!= PIPE_TIMEOUT_INFINITE
&&
714 os_time_get() - start_time
>= timeout
) {
719 return rscreen
->fences
.data
[rfence
->index
] != 0;
722 static int evergreen_interpret_tiling(struct r600_screen
*rscreen
, uint32_t tiling_config
)
724 switch (tiling_config
& 0xf) {
726 rscreen
->tiling_info
.num_channels
= 1;
729 rscreen
->tiling_info
.num_channels
= 2;
732 rscreen
->tiling_info
.num_channels
= 4;
735 rscreen
->tiling_info
.num_channels
= 8;
741 switch ((tiling_config
& 0xf0) >> 4) {
743 rscreen
->tiling_info
.num_banks
= 4;
746 rscreen
->tiling_info
.num_banks
= 8;
749 rscreen
->tiling_info
.num_banks
= 16;
755 switch ((tiling_config
& 0xf00) >> 8) {
757 rscreen
->tiling_info
.group_bytes
= 256;
760 rscreen
->tiling_info
.group_bytes
= 512;
768 static int r600_init_tiling(struct r600_screen
*rscreen
)
770 uint32_t tiling_config
= rscreen
->info
.r600_tiling_config
;
772 /* set default group bytes, overridden by tiling info ioctl */
773 rscreen
->tiling_info
.group_bytes
= 512;
778 return evergreen_interpret_tiling(rscreen
, tiling_config
);
781 static unsigned radeon_family_from_device(unsigned device
)
784 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
785 #include "pci_ids/radeonsi_pci_ids.h"
792 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
794 struct r600_screen
*rscreen
= CALLOC_STRUCT(r600_screen
);
795 if (rscreen
== NULL
) {
800 ws
->query_info(ws
, &rscreen
->info
);
802 rscreen
->family
= radeon_family_from_device(rscreen
->info
.pci_id
);
803 if (rscreen
->family
== CHIP_UNKNOWN
) {
804 fprintf(stderr
, "r600: Unknown chipset 0x%04X\n", rscreen
->info
.pci_id
);
810 if (rscreen
->family
>= CHIP_BONAIRE
) {
811 rscreen
->chip_class
= CIK
;
812 } else if (rscreen
->family
>= CHIP_TAHITI
) {
813 rscreen
->chip_class
= SI
;
815 fprintf(stderr
, "r600: Unsupported family %d\n", rscreen
->family
);
820 if (r600_init_tiling(rscreen
)) {
825 rscreen
->screen
.destroy
= r600_destroy_screen
;
826 rscreen
->screen
.get_name
= r600_get_name
;
827 rscreen
->screen
.get_vendor
= r600_get_vendor
;
828 rscreen
->screen
.get_param
= r600_get_param
;
829 rscreen
->screen
.get_shader_param
= r600_get_shader_param
;
830 rscreen
->screen
.get_paramf
= r600_get_paramf
;
831 rscreen
->screen
.get_compute_param
= r600_get_compute_param
;
832 rscreen
->screen
.is_format_supported
= si_is_format_supported
;
833 rscreen
->screen
.context_create
= r600_create_context
;
834 rscreen
->screen
.fence_reference
= r600_fence_reference
;
835 rscreen
->screen
.fence_signalled
= r600_fence_signalled
;
836 rscreen
->screen
.fence_finish
= r600_fence_finish
;
837 r600_init_screen_resource_functions(&rscreen
->screen
);
839 if (rscreen
->info
.has_uvd
) {
840 rscreen
->screen
.get_video_param
= ruvd_get_video_param
;
841 rscreen
->screen
.is_video_format_supported
= ruvd_is_format_supported
;
843 rscreen
->screen
.get_video_param
= r600_get_video_param
;
844 rscreen
->screen
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
847 util_format_s3tc_init();
849 rscreen
->fences
.bo
= NULL
;
850 rscreen
->fences
.data
= NULL
;
851 rscreen
->fences
.next_index
= 0;
852 LIST_INITHEAD(&rscreen
->fences
.pool
);
853 LIST_INITHEAD(&rscreen
->fences
.blocks
);
854 pipe_mutex_init(rscreen
->fences
.mutex
);
857 rscreen
->cs_count
= 0;
858 if (rscreen
->info
.drm_minor
>= 28) {
859 rscreen
->trace_bo
= (struct si_resource
*)pipe_buffer_create(&rscreen
->screen
,
863 if (rscreen
->trace_bo
) {
864 rscreen
->trace_ptr
= rscreen
->ws
->buffer_map(rscreen
->trace_bo
->cs_buf
, NULL
,
865 PIPE_TRANSFER_UNSYNCHRONIZED
);
870 return &rscreen
->screen
;