src/gallium/drivers/radeonsi/radeonsi_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "r600.h"
  46 #include "sid.h"
  47 #include "r600_resource.h"
  48 #include "radeonsi_pipe.h"
  49 #include "r600_hw_context_priv.h"
  50
  51 /*
  52  * pipe_context
  53  */
  54 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  55 {
  56         struct r600_screen *rscreen = rctx->screen;
  57         struct r600_fence *fence = NULL;
  58
  59         pipe_mutex_lock(rscreen->fences.mutex);
  60
  61         if (!rscreen->fences.bo) {
  62                 /* Create the shared buffer object */
  63                 rscreen->fences.bo = (struct r600_resource*)
  64                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  65                                            PIPE_USAGE_STAGING, 4096);
  66                 if (!rscreen->fences.bo) {
  67                         R600_ERR("r600: failed to create bo for fence objects\n");
  68                         goto out;
  69                 }
  70                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  71                                                            rctx->cs,
  72                                                            PIPE_TRANSFER_READ_WRITE);
  73         }
  74
  75         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  76                 struct r600_fence *entry;
  77
  78                 /* Try to find a freed fence that has been signalled */
  79                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  80                         if (rscreen->fences.data[entry->index] != 0) {
  81                                 LIST_DELINIT(&entry->head);
  82                                 fence = entry;
  83                                 break;
  84                         }
  85                 }
  86         }
  87
  88         if (!fence) {
  89                 /* Allocate a new fence */
  90                 struct r600_fence_block *block;
  91                 unsigned index;
  92
  93                 if ((rscreen->fences.next_index + 1) >= 1024) {
  94                         R600_ERR("r600: too many concurrent fences\n");
  95                         goto out;
  96                 }
  97
  98                 index = rscreen->fences.next_index++;
  99
 100                 if (!(index % FENCE_BLOCK_SIZE)) {
 101                         /* Allocate a new block */
 102                         block = CALLOC_STRUCT(r600_fence_block);
 103                         if (block == NULL)
 104                                 goto out;
 105
 106                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 107                 } else {
 108                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 109                 }
 110
 111                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 112                 fence->index = index;
 113         }
 114
 115         pipe_reference_init(&fence->reference, 1);
 116
 117         rscreen->fences.data[fence->index] = 0;
 118         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 119
 120         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 121         fence->sleep_bo = (struct r600_resource*)
 122                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 123                                            PIPE_USAGE_STAGING, 1);
 124         /* Add the fence as a dummy relocation. */
 125         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 126
 127 out:
 128         pipe_mutex_unlock(rscreen->fences.mutex);
 129         return fence;
 130 }
 131
 132
 133 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 134                     unsigned flags)
 135 {
 136         struct r600_context *rctx = (struct r600_context *)ctx;
 137         struct r600_fence **rfence = (struct r600_fence**)fence;
 138         struct pipe_query *render_cond = NULL;
 139         unsigned render_cond_mode = 0;
 140
 141         if (rfence)
 142                 *rfence = r600_create_fence(rctx);
 143
 144         /* Disable render condition. */
 145         if (rctx->current_render_cond) {
 146                 render_cond = rctx->current_render_cond;
 147                 render_cond_mode = rctx->current_render_cond_mode;
 148                 ctx->render_condition(ctx, NULL, 0);
 149         }
 150
 151         r600_context_flush(rctx, flags);
 152
 153         /* Re-enable render condition. */
 154         if (render_cond) {
 155                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 156         }
 157 }
 158
 159 static void r600_flush_from_st(struct pipe_context *ctx,
 160                                struct pipe_fence_handle **fence)
 161 {
 162         radeonsi_flush(ctx, fence, 0);
 163 }
 164
 165 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 166 {
 167         radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
 168 }
 169
 170 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 171 {
 172         pipe_mutex_lock(rscreen->mutex_num_contexts);
 173         if (diff > 0) {
 174                 rscreen->num_contexts++;
 175
 176                 if (rscreen->num_contexts > 1)
 177                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 178                                                     UTIL_SLAB_MULTITHREADED);
 179         } else {
 180                 rscreen->num_contexts--;
 181
 182                 if (rscreen->num_contexts <= 1)
 183                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 184                                                     UTIL_SLAB_SINGLETHREADED);
 185         }
 186         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 187 }
 188
 189 static void r600_destroy_context(struct pipe_context *context)
 190 {
 191         struct r600_context *rctx = (struct r600_context *)context;
 192
 193         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 194         util_unreference_framebuffer_state(&rctx->framebuffer);
 195
 196         r600_context_fini(rctx);
 197
 198         util_blitter_destroy(rctx->blitter);
 199
 200         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 201                 free(rctx->states[i]);
 202         }
 203
 204         if (rctx->uploader) {
 205                 u_upload_destroy(rctx->uploader);
 206         }
 207         util_slab_destroy(&rctx->pool_transfers);
 208
 209         r600_update_num_contexts(rctx->screen, -1);
 210
 211         FREE(rctx);
 212 }
 213
 214 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 215 {
 216         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 217         struct r600_screen* rscreen = (struct r600_screen *)screen;
 218
 219         if (rctx == NULL)
 220                 return NULL;
 221
 222         r600_update_num_contexts(rscreen, 1);
 223
 224         rctx->context.screen = screen;
 225         rctx->context.priv = priv;
 226         rctx->context.destroy = r600_destroy_context;
 227         rctx->context.flush = r600_flush_from_st;
 228
 229         /* Easy accessing of screen/winsys. */
 230         rctx->screen = rscreen;
 231         rctx->ws = rscreen->ws;
 232         rctx->family = rscreen->family;
 233         rctx->chip_class = rscreen->chip_class;
 234
 235         r600_init_blit_functions(rctx);
 236         r600_init_query_functions(rctx);
 237         r600_init_context_resource_functions(rctx);
 238         r600_init_surface_functions(rctx);
 239         rctx->context.draw_vbo = r600_draw_vbo;
 240
 241         rctx->context.create_video_decoder = vl_create_decoder;
 242         rctx->context.create_video_buffer = vl_video_buffer_create;
 243
 244         r600_init_common_atoms(rctx);
 245
 246         switch (rctx->chip_class) {
 247         case TAHITI:
 248                 cayman_init_state_functions(rctx);
 249                 if (si_context_init(rctx)) {
 250                         r600_destroy_context(&rctx->context);
 251                         return NULL;
 252                 }
 253                 si_init_config(rctx);
 254                 rctx->custom_dsa_flush = cayman_create_db_flush_dsa(rctx);
 255                 break;
 256         default:
 257                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 258                 r600_destroy_context(&rctx->context);
 259                 return NULL;
 260         }
 261
 262         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 263
 264         util_slab_create(&rctx->pool_transfers,
 265                          sizeof(struct pipe_transfer), 64,
 266                          UTIL_SLAB_SINGLETHREADED);
 267
 268         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 269                                          PIPE_BIND_INDEX_BUFFER |
 270                                          PIPE_BIND_CONSTANT_BUFFER);
 271         if (!rctx->uploader) {
 272                 r600_destroy_context(&rctx->context);
 273                 return NULL;
 274         }
 275
 276         rctx->blitter = util_blitter_create(&rctx->context);
 277         if (rctx->blitter == NULL) {
 278                 r600_destroy_context(&rctx->context);
 279                 return NULL;
 280         }
 281
 282         LIST_INITHEAD(&rctx->dirty_states);
 283
 284         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 285
 286         return &rctx->context;
 287 }
 288
 289 /*
 290  * pipe_screen
 291  */
 292 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 293 {
 294         return "X.Org";
 295 }
 296
 297 static const char *r600_get_family_name(enum radeon_family family)
 298 {
 299         switch(family) {
 300         case CHIP_CAYMAN: return "AMD CAYMAN";
 301         default: return "AMD unknown";
 302         }
 303 }
 304
 305 static const char* r600_get_name(struct pipe_screen* pscreen)
 306 {
 307         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 308
 309         return r600_get_family_name(rscreen->family);
 310 }
 311
 312 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 313 {
 314         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 315         enum radeon_family family = rscreen->family;
 316
 317         switch (param) {
 318         /* Supported features (boolean caps). */
 319         case PIPE_CAP_NPOT_TEXTURES:
 320         case PIPE_CAP_TWO_SIDED_STENCIL:
 321         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 322         case PIPE_CAP_ANISOTROPIC_FILTER:
 323         case PIPE_CAP_POINT_SPRITE:
 324         case PIPE_CAP_OCCLUSION_QUERY:
 325         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 326         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 327         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 328         case PIPE_CAP_TEXTURE_SWIZZLE:
 329         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 330         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 331         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 332         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 333         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 334         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 335         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 336         case PIPE_CAP_SM3:
 337         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 338         case PIPE_CAP_PRIMITIVE_RESTART:
 339         case PIPE_CAP_CONDITIONAL_RENDER:
 340         case PIPE_CAP_TEXTURE_BARRIER:
 341         case PIPE_CAP_INDEP_BLEND_ENABLE:
 342         case PIPE_CAP_INDEP_BLEND_FUNC:
 343         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 344         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 345         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 346         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 347         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 348                 return 1;
 349
 350         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 351                 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
 352
 353         /* Unsupported features. */
 354         case PIPE_CAP_TGSI_INSTANCEID:
 355         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 356         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 357         case PIPE_CAP_SCALED_RESOLVE:
 358         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 359         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 360         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 361         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 362         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 363         case PIPE_CAP_USER_VERTEX_BUFFERS:
 364                 return 0;
 365
 366         /* Stream output. */
 367         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 368                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 369         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 370                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
 371         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 372         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 373                 return 16*4;
 374
 375         /* Texturing. */
 376         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 377         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 378         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 379                         return 15;
 380         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 381                 return rscreen->info.drm_minor >= 9 ? 16384 : 0;
 382         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 383                 return 32;
 384
 385         /* Render targets. */
 386         case PIPE_CAP_MAX_RENDER_TARGETS:
 387                 /* FIXME some r6xx are buggy and can only do 4 */
 388                 return 8;
 389
 390         /* Timer queries, present when the clock frequency is non zero. */
 391         case PIPE_CAP_TIMER_QUERY:
 392                 return rscreen->info.r600_clock_crystal_freq != 0;
 393
 394         case PIPE_CAP_MIN_TEXEL_OFFSET:
 395                 return -8;
 396
 397         case PIPE_CAP_MAX_TEXEL_OFFSET:
 398                 return 7;
 399         }
 400         return 0;
 401 }
 402
 403 static float r600_get_paramf(struct pipe_screen* pscreen,
 404                              enum pipe_capf param)
 405 {
 406         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 407         enum radeon_family family = rscreen->family;
 408
 409         switch (param) {
 410         case PIPE_CAPF_MAX_LINE_WIDTH:
 411         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 412         case PIPE_CAPF_MAX_POINT_WIDTH:
 413         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 414                 return 16384.0f;
 415         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 416                 return 16.0f;
 417         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 418                 return 16.0f;
 419         case PIPE_CAPF_GUARD_BAND_LEFT:
 420         case PIPE_CAPF_GUARD_BAND_TOP:
 421         case PIPE_CAPF_GUARD_BAND_RIGHT:
 422         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 423                 return 0.0f;
 424         }
 425         return 0.0f;
 426 }
 427
 428 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 429 {
 430         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 431         switch(shader)
 432         {
 433         case PIPE_SHADER_FRAGMENT:
 434         case PIPE_SHADER_VERTEX:
 435                 break;
 436         case PIPE_SHADER_GEOMETRY:
 437                 /* TODO: support and enable geometry programs */
 438                 return 0;
 439         default:
 440                 /* TODO: support tessellation */
 441                 return 0;
 442         }
 443
 444         /* TODO: all these should be fixed, since r600 surely supports much more! */
 445         switch (param) {
 446         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 447         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 448         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 449         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 450                 return 16384;
 451         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 452                 return 8; /* FIXME */
 453         case PIPE_SHADER_CAP_MAX_INPUTS:
 454                 if(shader == PIPE_SHADER_FRAGMENT)
 455                         return 34;
 456                 else
 457                         return 32;
 458         case PIPE_SHADER_CAP_MAX_TEMPS:
 459                 return 256; /* Max native temporaries. */
 460         case PIPE_SHADER_CAP_MAX_ADDRS:
 461                 /* FIXME Isn't this equal to TEMPS? */
 462                 return 1; /* Max native address registers */
 463         case PIPE_SHADER_CAP_MAX_CONSTS:
 464                 return R600_MAX_CONST_BUFFER_SIZE;
 465         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 466                 return R600_MAX_CONST_BUFFERS;
 467         case PIPE_SHADER_CAP_MAX_PREDS:
 468                 return 0; /* FIXME */
 469         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 470                 return 1;
 471         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 472         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 473         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 474         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 475         case PIPE_SHADER_CAP_INTEGERS:
 476                 return 0;
 477         case PIPE_SHADER_CAP_SUBROUTINES:
 478                 return 0;
 479         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 480                 return 16;
 481         }
 482         return 0;
 483 }
 484
 485 static int r600_get_video_param(struct pipe_screen *screen,
 486                                 enum pipe_video_profile profile,
 487                                 enum pipe_video_cap param)
 488 {
 489         switch (param) {
 490         case PIPE_VIDEO_CAP_SUPPORTED:
 491                 return vl_profile_supported(screen, profile);
 492         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 493                 return 1;
 494         case PIPE_VIDEO_CAP_MAX_WIDTH:
 495         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 496                 return vl_video_buffer_max_size(screen);
 497         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 498                 return PIPE_FORMAT_NV12;
 499         default:
 500                 return 0;
 501         }
 502 }
 503
 504 static void r600_destroy_screen(struct pipe_screen* pscreen)
 505 {
 506         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 507
 508         if (rscreen == NULL)
 509                 return;
 510
 511         if (rscreen->fences.bo) {
 512                 struct r600_fence_block *entry, *tmp;
 513
 514                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 515                         LIST_DEL(&entry->head);
 516                         FREE(entry);
 517                 }
 518
 519                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 520                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 521         }
 522         pipe_mutex_destroy(rscreen->fences.mutex);
 523
 524         rscreen->ws->destroy(rscreen->ws);
 525
 526         util_slab_destroy(&rscreen->pool_buffers);
 527         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 528         FREE(rscreen);
 529 }
 530
 531 static void r600_fence_reference(struct pipe_screen *pscreen,
 532                                  struct pipe_fence_handle **ptr,
 533                                  struct pipe_fence_handle *fence)
 534 {
 535         struct r600_fence **oldf = (struct r600_fence**)ptr;
 536         struct r600_fence *newf = (struct r600_fence*)fence;
 537
 538         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 539                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 540                 pipe_mutex_lock(rscreen->fences.mutex);
 541                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 542                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 543                 pipe_mutex_unlock(rscreen->fences.mutex);
 544         }
 545
 546         *ptr = fence;
 547 }
 548
 549 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 550                                     struct pipe_fence_handle *fence)
 551 {
 552         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 553         struct r600_fence *rfence = (struct r600_fence*)fence;
 554
 555         return rscreen->fences.data[rfence->index];
 556 }
 557
 558 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 559                                  struct pipe_fence_handle *fence,
 560                                  uint64_t timeout)
 561 {
 562         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 563         struct r600_fence *rfence = (struct r600_fence*)fence;
 564         int64_t start_time = 0;
 565         unsigned spins = 0;
 566
 567         if (timeout != PIPE_TIMEOUT_INFINITE) {
 568                 start_time = os_time_get();
 569
 570                 /* Convert to microseconds. */
 571                 timeout /= 1000;
 572         }
 573
 574         while (rscreen->fences.data[rfence->index] == 0) {
 575                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 576                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 577                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 578                         break;
 579                 }
 580
 581                 /* The dummy BO will be busy until the CS including the fence has completed, or
 582                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 583                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 584                         break;
 585
 586                 if (++spins % 256)
 587                         continue;
 588 #ifdef PIPE_OS_UNIX
 589                 sched_yield();
 590 #else
 591                 os_time_sleep(10);
 592 #endif
 593                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 594                     os_time_get() - start_time >= timeout) {
 595                         break;
 596                 }
 597         }
 598
 599         return rscreen->fences.data[rfence->index] != 0;
 600 }
 601
 602 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 603 {
 604         switch (tiling_config & 0xf) {
 605         case 0:
 606                 rscreen->tiling_info.num_channels = 1;
 607                 break;
 608         case 1:
 609                 rscreen->tiling_info.num_channels = 2;
 610                 break;
 611         case 2:
 612                 rscreen->tiling_info.num_channels = 4;
 613                 break;
 614         case 3:
 615                 rscreen->tiling_info.num_channels = 8;
 616                 break;
 617         default:
 618                 return -EINVAL;
 619         }
 620
 621         switch ((tiling_config & 0xf0) >> 4) {
 622         case 0:
 623                 rscreen->tiling_info.num_banks = 4;
 624                 break;
 625         case 1:
 626                 rscreen->tiling_info.num_banks = 8;
 627                 break;
 628         case 2:
 629                 rscreen->tiling_info.num_banks = 16;
 630                 break;
 631         default:
 632                 return -EINVAL;
 633         }
 634
 635         switch ((tiling_config & 0xf00) >> 8) {
 636         case 0:
 637                 rscreen->tiling_info.group_bytes = 256;
 638                 break;
 639         case 1:
 640                 rscreen->tiling_info.group_bytes = 512;
 641                 break;
 642         default:
 643                 return -EINVAL;
 644         }
 645         return 0;
 646 }
 647
 648 static int r600_init_tiling(struct r600_screen *rscreen)
 649 {
 650         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 651
 652         /* set default group bytes, overridden by tiling info ioctl */
 653         rscreen->tiling_info.group_bytes = 512;
 654
 655         if (!tiling_config)
 656                 return 0;
 657
 658         return evergreen_interpret_tiling(rscreen, tiling_config);
 659 }
 660
 661 static unsigned radeon_family_from_device(unsigned device)
 662 {
 663         switch (device) {
 664 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 665 #include "pci_ids/radeonsi_pci_ids.h"
 666 #undef CHIPSET
 667         default:
 668                 return CHIP_UNKNOWN;
 669         }
 670 }
 671
 672 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 673 {
 674         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 675         if (rscreen == NULL) {
 676                 return NULL;
 677         }
 678
 679         rscreen->ws = ws;
 680         ws->query_info(ws, &rscreen->info);
 681
 682         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 683         if (rscreen->family == CHIP_UNKNOWN) {
 684                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 685                 FREE(rscreen);
 686                 return NULL;
 687         }
 688
 689         /* setup class */
 690         if (rscreen->family >= CHIP_TAHITI) {
 691                 rscreen->chip_class = TAHITI;
 692         } else {
 693                 fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family);
 694                 FREE(rscreen);
 695                 return NULL;
 696         }
 697
 698         if (r600_init_tiling(rscreen)) {
 699                 FREE(rscreen);
 700                 return NULL;
 701         }
 702
 703         rscreen->screen.destroy = r600_destroy_screen;
 704         rscreen->screen.get_name = r600_get_name;
 705         rscreen->screen.get_vendor = r600_get_vendor;
 706         rscreen->screen.get_param = r600_get_param;
 707         rscreen->screen.get_shader_param = r600_get_shader_param;
 708         rscreen->screen.get_paramf = r600_get_paramf;
 709         rscreen->screen.get_video_param = r600_get_video_param;
 710         rscreen->screen.is_format_supported = si_is_format_supported;
 711         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 712         rscreen->screen.context_create = r600_create_context;
 713         rscreen->screen.fence_reference = r600_fence_reference;
 714         rscreen->screen.fence_signalled = r600_fence_signalled;
 715         rscreen->screen.fence_finish = r600_fence_finish;
 716         r600_init_screen_resource_functions(&rscreen->screen);
 717
 718         util_format_s3tc_init();
 719
 720         util_slab_create(&rscreen->pool_buffers,
 721                          sizeof(struct r600_resource), 64,
 722                          UTIL_SLAB_SINGLETHREADED);
 723
 724         pipe_mutex_init(rscreen->mutex_num_contexts);
 725
 726         rscreen->fences.bo = NULL;
 727         rscreen->fences.data = NULL;
 728         rscreen->fences.next_index = 0;
 729         LIST_INITHEAD(&rscreen->fences.pool);
 730         LIST_INITHEAD(&rscreen->fences.blocks);
 731         pipe_mutex_init(rscreen->fences.mutex);
 732
 733         return &rscreen->screen;
 734 }