src/gallium/drivers/radeonsi/radeonsi_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_simple_shaders.h"
  41 #include "util/u_upload_mgr.h"
  42 #include "vl/vl_decoder.h"
  43 #include "vl/vl_video_buffer.h"
  44 #include "os/os_time.h"
  45 #include "pipebuffer/pb_buffer.h"
  46 #include "r600.h"
  47 #include "sid.h"
  48 #include "r600_resource.h"
  49 #include "radeonsi_pipe.h"
  50 #include "r600_hw_context_priv.h"
  51 #include "si_state.h"
  52
  53 /*
  54  * pipe_context
  55  */
  56 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  57 {
  58         struct r600_screen *rscreen = rctx->screen;
  59         struct r600_fence *fence = NULL;
  60
  61         pipe_mutex_lock(rscreen->fences.mutex);
  62
  63         if (!rscreen->fences.bo) {
  64                 /* Create the shared buffer object */
  65                 rscreen->fences.bo = si_resource_create_custom(&rscreen->screen,
  66                                                                PIPE_USAGE_STAGING,
  67                                                                4096);
  68                 if (!rscreen->fences.bo) {
  69                         R600_ERR("r600: failed to create bo for fence objects\n");
  70                         goto out;
  71                 }
  72                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  73                                                            rctx->cs,
  74                                                            PIPE_TRANSFER_READ_WRITE);
  75         }
  76
  77         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  78                 struct r600_fence *entry;
  79
  80                 /* Try to find a freed fence that has been signalled */
  81                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  82                         if (rscreen->fences.data[entry->index] != 0) {
  83                                 LIST_DELINIT(&entry->head);
  84                                 fence = entry;
  85                                 break;
  86                         }
  87                 }
  88         }
  89
  90         if (!fence) {
  91                 /* Allocate a new fence */
  92                 struct r600_fence_block *block;
  93                 unsigned index;
  94
  95                 if ((rscreen->fences.next_index + 1) >= 1024) {
  96                         R600_ERR("r600: too many concurrent fences\n");
  97                         goto out;
  98                 }
  99
 100                 index = rscreen->fences.next_index++;
 101
 102                 if (!(index % FENCE_BLOCK_SIZE)) {
 103                         /* Allocate a new block */
 104                         block = CALLOC_STRUCT(r600_fence_block);
 105                         if (block == NULL)
 106                                 goto out;
 107
 108                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 109                 } else {
 110                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 111                 }
 112
 113                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 114                 fence->index = index;
 115         }
 116
 117         pipe_reference_init(&fence->reference, 1);
 118
 119         rscreen->fences.data[fence->index] = 0;
 120         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 121
 122         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 123         fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
 124
 125         /* Add the fence as a dummy relocation. */
 126         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 127
 128 out:
 129         pipe_mutex_unlock(rscreen->fences.mutex);
 130         return fence;
 131 }
 132
 133
 134 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 135                     unsigned flags)
 136 {
 137         struct r600_context *rctx = (struct r600_context *)ctx;
 138         struct r600_fence **rfence = (struct r600_fence**)fence;
 139         struct pipe_query *render_cond = NULL;
 140         unsigned render_cond_mode = 0;
 141
 142         if (rfence)
 143                 *rfence = r600_create_fence(rctx);
 144
 145         /* Disable render condition. */
 146         if (rctx->current_render_cond) {
 147                 render_cond = rctx->current_render_cond;
 148                 render_cond_mode = rctx->current_render_cond_mode;
 149                 ctx->render_condition(ctx, NULL, 0);
 150         }
 151
 152         r600_context_flush(rctx, flags);
 153
 154         /* Re-enable render condition. */
 155         if (render_cond) {
 156                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 157         }
 158 }
 159
 160 static void r600_flush_from_st(struct pipe_context *ctx,
 161                                struct pipe_fence_handle **fence)
 162 {
 163         radeonsi_flush(ctx, fence, 0);
 164 }
 165
 166 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 167 {
 168         radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
 169 }
 170
 171 static void r600_destroy_context(struct pipe_context *context)
 172 {
 173         struct r600_context *rctx = (struct r600_context *)context;
 174
 175         if (rctx->dummy_pixel_shader) {
 176                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 177         }
 178         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 179         util_unreference_framebuffer_state(&rctx->framebuffer);
 180
 181         util_blitter_destroy(rctx->blitter);
 182
 183         if (rctx->uploader) {
 184                 u_upload_destroy(rctx->uploader);
 185         }
 186         util_slab_destroy(&rctx->pool_transfers);
 187         FREE(rctx);
 188 }
 189
 190 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 191 {
 192         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 193         struct r600_screen* rscreen = (struct r600_screen *)screen;
 194
 195         if (rctx == NULL)
 196                 return NULL;
 197
 198         rctx->context.screen = screen;
 199         rctx->context.priv = priv;
 200         rctx->context.destroy = r600_destroy_context;
 201         rctx->context.flush = r600_flush_from_st;
 202
 203         /* Easy accessing of screen/winsys. */
 204         rctx->screen = rscreen;
 205         rctx->ws = rscreen->ws;
 206         rctx->family = rscreen->family;
 207         rctx->chip_class = rscreen->chip_class;
 208
 209         r600_init_blit_functions(rctx);
 210         r600_init_query_functions(rctx);
 211         r600_init_context_resource_functions(rctx);
 212         r600_init_surface_functions(rctx);
 213
 214         rctx->context.create_video_decoder = vl_create_decoder;
 215         rctx->context.create_video_buffer = vl_video_buffer_create;
 216
 217         r600_init_common_atoms(rctx);
 218
 219         switch (rctx->chip_class) {
 220         case TAHITI:
 221                 si_init_state_functions(rctx);
 222                 if (si_context_init(rctx)) {
 223                         r600_destroy_context(&rctx->context);
 224                         return NULL;
 225                 }
 226                 si_init_config(rctx);
 227                 break;
 228         default:
 229                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 230                 r600_destroy_context(&rctx->context);
 231                 return NULL;
 232         }
 233
 234         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 235
 236         util_slab_create(&rctx->pool_transfers,
 237                          sizeof(struct pipe_transfer), 64,
 238                          UTIL_SLAB_SINGLETHREADED);
 239
 240         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 241                                          PIPE_BIND_INDEX_BUFFER |
 242                                          PIPE_BIND_CONSTANT_BUFFER);
 243         if (!rctx->uploader) {
 244                 r600_destroy_context(&rctx->context);
 245                 return NULL;
 246         }
 247
 248         rctx->blitter = util_blitter_create(&rctx->context);
 249         if (rctx->blitter == NULL) {
 250                 r600_destroy_context(&rctx->context);
 251                 return NULL;
 252         }
 253
 254         LIST_INITHEAD(&rctx->dirty_states);
 255
 256         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 257
 258         rctx->dummy_pixel_shader =
 259                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 260                                                      TGSI_SEMANTIC_GENERIC,
 261                                                      TGSI_INTERPOLATE_CONSTANT);
 262         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 263
 264         return &rctx->context;
 265 }
 266
 267 /*
 268  * pipe_screen
 269  */
 270 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 271 {
 272         return "X.Org";
 273 }
 274
 275 static const char *r600_get_family_name(enum radeon_family family)
 276 {
 277         switch(family) {
 278         case CHIP_TAHITI: return "AMD TAHITI";
 279         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 280         case CHIP_VERDE: return "AMD CAPE VERDE";
 281         default: return "AMD unknown";
 282         }
 283 }
 284
 285 static const char* r600_get_name(struct pipe_screen* pscreen)
 286 {
 287         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 288
 289         return r600_get_family_name(rscreen->family);
 290 }
 291
 292 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 293 {
 294         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 295         enum radeon_family family = rscreen->family;
 296
 297         switch (param) {
 298         /* Supported features (boolean caps). */
 299         case PIPE_CAP_NPOT_TEXTURES:
 300         case PIPE_CAP_TWO_SIDED_STENCIL:
 301         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 302         case PIPE_CAP_ANISOTROPIC_FILTER:
 303         case PIPE_CAP_POINT_SPRITE:
 304         case PIPE_CAP_OCCLUSION_QUERY:
 305         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 306         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 307         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 308         case PIPE_CAP_TEXTURE_SWIZZLE:
 309         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 310         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 311         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 312         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 313         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 314         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 315         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 316         case PIPE_CAP_SM3:
 317         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 318         case PIPE_CAP_PRIMITIVE_RESTART:
 319         case PIPE_CAP_CONDITIONAL_RENDER:
 320         case PIPE_CAP_TEXTURE_BARRIER:
 321         case PIPE_CAP_INDEP_BLEND_ENABLE:
 322         case PIPE_CAP_INDEP_BLEND_FUNC:
 323         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 324         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 325         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 326         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 327         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 328         case PIPE_CAP_USER_INDEX_BUFFERS:
 329         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 330         case PIPE_CAP_START_INSTANCE:
 331                 return 1;
 332
 333         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 334                 return 256;
 335
 336         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 337                 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
 338
 339         /* Unsupported features. */
 340         case PIPE_CAP_TGSI_INSTANCEID:
 341         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 342         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 343         case PIPE_CAP_SCALED_RESOLVE:
 344         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 345         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 346         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 347         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 348         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 349         case PIPE_CAP_USER_VERTEX_BUFFERS:
 350                 return 0;
 351
 352         /* Stream output. */
 353         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 354                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 355         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 356                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
 357         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 358         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 359                 return 16*4;
 360
 361         /* Texturing. */
 362         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 363         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 364         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 365                         return 15;
 366         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 367                 return rscreen->info.drm_minor >= 9 ? 16384 : 0;
 368         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 369                 return 32;
 370
 371         /* Render targets. */
 372         case PIPE_CAP_MAX_RENDER_TARGETS:
 373                 /* FIXME some r6xx are buggy and can only do 4 */
 374                 return 8;
 375
 376         /* Timer queries, present when the clock frequency is non zero. */
 377         case PIPE_CAP_TIMER_QUERY:
 378                 return rscreen->info.r600_clock_crystal_freq != 0;
 379
 380         case PIPE_CAP_MIN_TEXEL_OFFSET:
 381                 return -8;
 382
 383         case PIPE_CAP_MAX_TEXEL_OFFSET:
 384                 return 7;
 385         }
 386         return 0;
 387 }
 388
 389 static float r600_get_paramf(struct pipe_screen* pscreen,
 390                              enum pipe_capf param)
 391 {
 392         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 393         enum radeon_family family = rscreen->family;
 394
 395         switch (param) {
 396         case PIPE_CAPF_MAX_LINE_WIDTH:
 397         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 398         case PIPE_CAPF_MAX_POINT_WIDTH:
 399         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 400                 return 16384.0f;
 401         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 402                 return 16.0f;
 403         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 404                 return 16.0f;
 405         case PIPE_CAPF_GUARD_BAND_LEFT:
 406         case PIPE_CAPF_GUARD_BAND_TOP:
 407         case PIPE_CAPF_GUARD_BAND_RIGHT:
 408         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 409                 return 0.0f;
 410         }
 411         return 0.0f;
 412 }
 413
 414 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 415 {
 416         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 417         switch(shader)
 418         {
 419         case PIPE_SHADER_FRAGMENT:
 420         case PIPE_SHADER_VERTEX:
 421                 break;
 422         case PIPE_SHADER_GEOMETRY:
 423                 /* TODO: support and enable geometry programs */
 424                 return 0;
 425         default:
 426                 /* TODO: support tessellation */
 427                 return 0;
 428         }
 429
 430         /* TODO: all these should be fixed, since r600 surely supports much more! */
 431         switch (param) {
 432         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 433         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 434         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 435         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 436                 return 16384;
 437         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 438                 return 8; /* FIXME */
 439         case PIPE_SHADER_CAP_MAX_INPUTS:
 440                 if(shader == PIPE_SHADER_FRAGMENT)
 441                         return 34;
 442                 else
 443                         return 32;
 444         case PIPE_SHADER_CAP_MAX_TEMPS:
 445                 return 256; /* Max native temporaries. */
 446         case PIPE_SHADER_CAP_MAX_ADDRS:
 447                 /* FIXME Isn't this equal to TEMPS? */
 448                 return 1; /* Max native address registers */
 449         case PIPE_SHADER_CAP_MAX_CONSTS:
 450                 return R600_MAX_CONST_BUFFER_SIZE;
 451         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 452                 return R600_MAX_CONST_BUFFERS;
 453         case PIPE_SHADER_CAP_MAX_PREDS:
 454                 return 0; /* FIXME */
 455         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 456                 return 1;
 457         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 458         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 459         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 460         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 461                 return 0;
 462         case PIPE_SHADER_CAP_INTEGERS:
 463                 return 1;
 464         case PIPE_SHADER_CAP_SUBROUTINES:
 465                 return 0;
 466         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 467                 return 16;
 468         }
 469         return 0;
 470 }
 471
 472 static int r600_get_video_param(struct pipe_screen *screen,
 473                                 enum pipe_video_profile profile,
 474                                 enum pipe_video_cap param)
 475 {
 476         switch (param) {
 477         case PIPE_VIDEO_CAP_SUPPORTED:
 478                 return vl_profile_supported(screen, profile);
 479         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 480                 return 1;
 481         case PIPE_VIDEO_CAP_MAX_WIDTH:
 482         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 483                 return vl_video_buffer_max_size(screen);
 484         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 485                 return PIPE_FORMAT_NV12;
 486         default:
 487                 return 0;
 488         }
 489 }
 490
 491 static void r600_destroy_screen(struct pipe_screen* pscreen)
 492 {
 493         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 494
 495         if (rscreen == NULL)
 496                 return;
 497
 498         if (rscreen->fences.bo) {
 499                 struct r600_fence_block *entry, *tmp;
 500
 501                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 502                         LIST_DEL(&entry->head);
 503                         FREE(entry);
 504                 }
 505
 506                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 507                 si_resource_reference(&rscreen->fences.bo, NULL);
 508         }
 509         pipe_mutex_destroy(rscreen->fences.mutex);
 510
 511         rscreen->ws->destroy(rscreen->ws);
 512         FREE(rscreen);
 513 }
 514
 515 static void r600_fence_reference(struct pipe_screen *pscreen,
 516                                  struct pipe_fence_handle **ptr,
 517                                  struct pipe_fence_handle *fence)
 518 {
 519         struct r600_fence **oldf = (struct r600_fence**)ptr;
 520         struct r600_fence *newf = (struct r600_fence*)fence;
 521
 522         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 523                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 524                 pipe_mutex_lock(rscreen->fences.mutex);
 525                 si_resource_reference(&(*oldf)->sleep_bo, NULL);
 526                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 527                 pipe_mutex_unlock(rscreen->fences.mutex);
 528         }
 529
 530         *ptr = fence;
 531 }
 532
 533 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 534                                     struct pipe_fence_handle *fence)
 535 {
 536         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 537         struct r600_fence *rfence = (struct r600_fence*)fence;
 538
 539         return rscreen->fences.data[rfence->index];
 540 }
 541
 542 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 543                                  struct pipe_fence_handle *fence,
 544                                  uint64_t timeout)
 545 {
 546         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 547         struct r600_fence *rfence = (struct r600_fence*)fence;
 548         int64_t start_time = 0;
 549         unsigned spins = 0;
 550
 551         if (timeout != PIPE_TIMEOUT_INFINITE) {
 552                 start_time = os_time_get();
 553
 554                 /* Convert to microseconds. */
 555                 timeout /= 1000;
 556         }
 557
 558         while (rscreen->fences.data[rfence->index] == 0) {
 559                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 560                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 561                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 562                         break;
 563                 }
 564
 565                 /* The dummy BO will be busy until the CS including the fence has completed, or
 566                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 567                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 568                         break;
 569
 570                 if (++spins % 256)
 571                         continue;
 572 #ifdef PIPE_OS_UNIX
 573                 sched_yield();
 574 #else
 575                 os_time_sleep(10);
 576 #endif
 577                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 578                     os_time_get() - start_time >= timeout) {
 579                         break;
 580                 }
 581         }
 582
 583         return rscreen->fences.data[rfence->index] != 0;
 584 }
 585
 586 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 587 {
 588         switch (tiling_config & 0xf) {
 589         case 0:
 590                 rscreen->tiling_info.num_channels = 1;
 591                 break;
 592         case 1:
 593                 rscreen->tiling_info.num_channels = 2;
 594                 break;
 595         case 2:
 596                 rscreen->tiling_info.num_channels = 4;
 597                 break;
 598         case 3:
 599                 rscreen->tiling_info.num_channels = 8;
 600                 break;
 601         default:
 602                 return -EINVAL;
 603         }
 604
 605         switch ((tiling_config & 0xf0) >> 4) {
 606         case 0:
 607                 rscreen->tiling_info.num_banks = 4;
 608                 break;
 609         case 1:
 610                 rscreen->tiling_info.num_banks = 8;
 611                 break;
 612         case 2:
 613                 rscreen->tiling_info.num_banks = 16;
 614                 break;
 615         default:
 616                 return -EINVAL;
 617         }
 618
 619         switch ((tiling_config & 0xf00) >> 8) {
 620         case 0:
 621                 rscreen->tiling_info.group_bytes = 256;
 622                 break;
 623         case 1:
 624                 rscreen->tiling_info.group_bytes = 512;
 625                 break;
 626         default:
 627                 return -EINVAL;
 628         }
 629         return 0;
 630 }
 631
 632 static int r600_init_tiling(struct r600_screen *rscreen)
 633 {
 634         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 635
 636         /* set default group bytes, overridden by tiling info ioctl */
 637         rscreen->tiling_info.group_bytes = 512;
 638
 639         if (!tiling_config)
 640                 return 0;
 641
 642         return evergreen_interpret_tiling(rscreen, tiling_config);
 643 }
 644
 645 static unsigned radeon_family_from_device(unsigned device)
 646 {
 647         switch (device) {
 648 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 649 #include "pci_ids/radeonsi_pci_ids.h"
 650 #undef CHIPSET
 651         default:
 652                 return CHIP_UNKNOWN;
 653         }
 654 }
 655
 656 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 657 {
 658         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 659         if (rscreen == NULL) {
 660                 return NULL;
 661         }
 662
 663         rscreen->ws = ws;
 664         ws->query_info(ws, &rscreen->info);
 665
 666         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 667         if (rscreen->family == CHIP_UNKNOWN) {
 668                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 669                 FREE(rscreen);
 670                 return NULL;
 671         }
 672
 673         /* setup class */
 674         if (rscreen->family >= CHIP_TAHITI) {
 675                 rscreen->chip_class = TAHITI;
 676         } else {
 677                 fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family);
 678                 FREE(rscreen);
 679                 return NULL;
 680         }
 681
 682         if (r600_init_tiling(rscreen)) {
 683                 FREE(rscreen);
 684                 return NULL;
 685         }
 686
 687         rscreen->screen.destroy = r600_destroy_screen;
 688         rscreen->screen.get_name = r600_get_name;
 689         rscreen->screen.get_vendor = r600_get_vendor;
 690         rscreen->screen.get_param = r600_get_param;
 691         rscreen->screen.get_shader_param = r600_get_shader_param;
 692         rscreen->screen.get_paramf = r600_get_paramf;
 693         rscreen->screen.get_video_param = r600_get_video_param;
 694         rscreen->screen.is_format_supported = si_is_format_supported;
 695         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 696         rscreen->screen.context_create = r600_create_context;
 697         rscreen->screen.fence_reference = r600_fence_reference;
 698         rscreen->screen.fence_signalled = r600_fence_signalled;
 699         rscreen->screen.fence_finish = r600_fence_finish;
 700         r600_init_screen_resource_functions(&rscreen->screen);
 701
 702         util_format_s3tc_init();
 703
 704         rscreen->fences.bo = NULL;
 705         rscreen->fences.data = NULL;
 706         rscreen->fences.next_index = 0;
 707         LIST_INITHEAD(&rscreen->fences.pool);
 708         LIST_INITHEAD(&rscreen->fences.blocks);
 709         pipe_mutex_init(rscreen->fences.mutex);
 710
 711         return &rscreen->screen;
 712 }