2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31 #include "util/u_blitter.h"
32 #include "util/u_double_list.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_transfer.h"
36 #include "util/u_surface.h"
37 #include "util/u_pack_color.h"
38 #include "util/u_memory.h"
39 #include "util/u_inlines.h"
40 #include "util/u_simple_shaders.h"
41 #include "util/u_upload_mgr.h"
42 #include "vl/vl_decoder.h"
43 #include "vl/vl_video_buffer.h"
44 #include "os/os_time.h"
45 #include "pipebuffer/pb_buffer.h"
46 #include "radeonsi_pipe.h"
47 #include "radeon/radeon_uvd.h"
50 #include "r600_resource.h"
51 #include "radeonsi_pipe.h"
52 #include "r600_hw_context_priv.h"
58 static struct r600_fence
*r600_create_fence(struct r600_context
*rctx
)
60 struct r600_screen
*rscreen
= rctx
->screen
;
61 struct r600_fence
*fence
= NULL
;
63 pipe_mutex_lock(rscreen
->fences
.mutex
);
65 if (!rscreen
->fences
.bo
) {
66 /* Create the shared buffer object */
67 rscreen
->fences
.bo
= si_resource_create_custom(&rscreen
->screen
,
70 if (!rscreen
->fences
.bo
) {
71 R600_ERR("r600: failed to create bo for fence objects\n");
74 rscreen
->fences
.data
= rctx
->ws
->buffer_map(rscreen
->fences
.bo
->cs_buf
,
76 PIPE_TRANSFER_READ_WRITE
);
79 if (!LIST_IS_EMPTY(&rscreen
->fences
.pool
)) {
80 struct r600_fence
*entry
;
82 /* Try to find a freed fence that has been signalled */
83 LIST_FOR_EACH_ENTRY(entry
, &rscreen
->fences
.pool
, head
) {
84 if (rscreen
->fences
.data
[entry
->index
] != 0) {
85 LIST_DELINIT(&entry
->head
);
93 /* Allocate a new fence */
94 struct r600_fence_block
*block
;
97 if ((rscreen
->fences
.next_index
+ 1) >= 1024) {
98 R600_ERR("r600: too many concurrent fences\n");
102 index
= rscreen
->fences
.next_index
++;
104 if (!(index
% FENCE_BLOCK_SIZE
)) {
105 /* Allocate a new block */
106 block
= CALLOC_STRUCT(r600_fence_block
);
110 LIST_ADD(&block
->head
, &rscreen
->fences
.blocks
);
112 block
= LIST_ENTRY(struct r600_fence_block
, rscreen
->fences
.blocks
.next
, head
);
115 fence
= &block
->fences
[index
% FENCE_BLOCK_SIZE
];
116 fence
->index
= index
;
119 pipe_reference_init(&fence
->reference
, 1);
121 rscreen
->fences
.data
[fence
->index
] = 0;
122 si_context_emit_fence(rctx
, rscreen
->fences
.bo
, fence
->index
, 1);
124 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
125 fence
->sleep_bo
= si_resource_create_custom(&rctx
->screen
->screen
, PIPE_USAGE_STAGING
, 1);
127 /* Add the fence as a dummy relocation. */
128 r600_context_bo_reloc(rctx
, fence
->sleep_bo
, RADEON_USAGE_READWRITE
);
131 pipe_mutex_unlock(rscreen
->fences
.mutex
);
136 void radeonsi_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
139 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
140 struct r600_fence
**rfence
= (struct r600_fence
**)fence
;
141 struct pipe_query
*render_cond
= NULL
;
142 unsigned render_cond_mode
= 0;
145 *rfence
= r600_create_fence(rctx
);
147 /* Disable render condition. */
148 if (rctx
->current_render_cond
) {
149 render_cond
= rctx
->current_render_cond
;
150 render_cond_mode
= rctx
->current_render_cond_mode
;
151 ctx
->render_condition(ctx
, NULL
, 0);
154 si_context_flush(rctx
, flags
);
156 /* Re-enable render condition. */
158 ctx
->render_condition(ctx
, render_cond
, render_cond_mode
);
162 static void r600_flush_from_st(struct pipe_context
*ctx
,
163 struct pipe_fence_handle
**fence
,
166 radeonsi_flush(ctx
, fence
,
167 flags
& PIPE_FLUSH_END_OF_FRAME
? RADEON_FLUSH_END_OF_FRAME
: 0);
170 static void r600_flush_from_winsys(void *ctx
, unsigned flags
)
172 radeonsi_flush((struct pipe_context
*)ctx
, NULL
, flags
);
175 static void r600_destroy_context(struct pipe_context
*context
)
177 struct r600_context
*rctx
= (struct r600_context
*)context
;
179 si_resource_reference(&rctx
->border_color_table
, NULL
);
181 if (rctx
->dummy_pixel_shader
) {
182 rctx
->context
.delete_fs_state(&rctx
->context
, rctx
->dummy_pixel_shader
);
184 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush_depth_stencil
);
185 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush_depth
);
186 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush_stencil
);
187 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush_inplace
);
188 util_unreference_framebuffer_state(&rctx
->framebuffer
);
190 util_blitter_destroy(rctx
->blitter
);
192 if (rctx
->uploader
) {
193 u_upload_destroy(rctx
->uploader
);
195 util_slab_destroy(&rctx
->pool_transfers
);
199 static struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
201 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
202 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
207 rctx
->context
.screen
= screen
;
208 rctx
->context
.priv
= priv
;
209 rctx
->context
.destroy
= r600_destroy_context
;
210 rctx
->context
.flush
= r600_flush_from_st
;
212 /* Easy accessing of screen/winsys. */
213 rctx
->screen
= rscreen
;
214 rctx
->ws
= rscreen
->ws
;
215 rctx
->family
= rscreen
->family
;
216 rctx
->chip_class
= rscreen
->chip_class
;
218 si_init_blit_functions(rctx
);
219 r600_init_query_functions(rctx
);
220 r600_init_context_resource_functions(rctx
);
221 si_init_surface_functions(rctx
);
222 si_init_compute_functions(rctx
);
224 if (rscreen
->info
.has_uvd
) {
225 rctx
->context
.create_video_decoder
= radeonsi_uvd_create_decoder
;
226 rctx
->context
.create_video_buffer
= radeonsi_video_buffer_create
;
228 rctx
->context
.create_video_decoder
= vl_create_decoder
;
229 rctx
->context
.create_video_buffer
= vl_video_buffer_create
;
232 switch (rctx
->chip_class
) {
234 si_init_state_functions(rctx
);
235 LIST_INITHEAD(&rctx
->active_query_list
);
236 rctx
->cs
= rctx
->ws
->cs_create(rctx
->ws
, RING_GFX
, NULL
);
238 si_init_config(rctx
);
241 R600_ERR("Unsupported chip class %d.\n", rctx
->chip_class
);
242 r600_destroy_context(&rctx
->context
);
246 rctx
->ws
->cs_set_flush_callback(rctx
->cs
, r600_flush_from_winsys
, rctx
);
248 util_slab_create(&rctx
->pool_transfers
,
249 sizeof(struct pipe_transfer
), 64,
250 UTIL_SLAB_SINGLETHREADED
);
252 rctx
->uploader
= u_upload_create(&rctx
->context
, 1024 * 1024, 256,
253 PIPE_BIND_INDEX_BUFFER
|
254 PIPE_BIND_CONSTANT_BUFFER
);
255 if (!rctx
->uploader
) {
256 r600_destroy_context(&rctx
->context
);
260 rctx
->blitter
= util_blitter_create(&rctx
->context
);
261 if (rctx
->blitter
== NULL
) {
262 r600_destroy_context(&rctx
->context
);
266 si_get_backend_mask(rctx
); /* this emits commands and must be last */
268 rctx
->dummy_pixel_shader
=
269 util_make_fragment_cloneinput_shader(&rctx
->context
, 0,
270 TGSI_SEMANTIC_GENERIC
,
271 TGSI_INTERPOLATE_CONSTANT
);
272 rctx
->context
.bind_fs_state(&rctx
->context
, rctx
->dummy_pixel_shader
);
274 return &rctx
->context
;
280 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
285 const char *r600_get_llvm_processor_name(enum radeon_family family
)
288 case CHIP_TAHITI
: return "tahiti";
289 case CHIP_PITCAIRN
: return "pitcairn";
290 case CHIP_VERDE
: return "verde";
291 case CHIP_OLAND
: return "oland";
296 static const char *r600_get_family_name(enum radeon_family family
)
299 case CHIP_TAHITI
: return "AMD TAHITI";
300 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
301 case CHIP_VERDE
: return "AMD CAPE VERDE";
302 case CHIP_OLAND
: return "AMD OLAND";
303 default: return "AMD unknown";
307 static const char* r600_get_name(struct pipe_screen
* pscreen
)
309 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
311 return r600_get_family_name(rscreen
->family
);
314 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
316 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
319 /* Supported features (boolean caps). */
320 case PIPE_CAP_TWO_SIDED_STENCIL
:
321 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
322 case PIPE_CAP_ANISOTROPIC_FILTER
:
323 case PIPE_CAP_POINT_SPRITE
:
324 case PIPE_CAP_OCCLUSION_QUERY
:
325 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
326 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
327 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
328 case PIPE_CAP_TEXTURE_SWIZZLE
:
329 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
330 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
331 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
332 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
333 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
334 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
336 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
337 case PIPE_CAP_PRIMITIVE_RESTART
:
338 case PIPE_CAP_CONDITIONAL_RENDER
:
339 case PIPE_CAP_TEXTURE_BARRIER
:
340 case PIPE_CAP_INDEP_BLEND_ENABLE
:
341 case PIPE_CAP_INDEP_BLEND_FUNC
:
342 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
343 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
344 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
345 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
346 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
347 case PIPE_CAP_USER_INDEX_BUFFERS
:
348 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
349 case PIPE_CAP_START_INSTANCE
:
350 case PIPE_CAP_NPOT_TEXTURES
:
351 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
352 case PIPE_CAP_TGSI_INSTANCEID
:
353 case PIPE_CAP_COMPUTE
:
355 case PIPE_CAP_TGSI_TEXCOORD
:
358 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
361 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
364 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
365 return debug_get_bool_option("R600_GLSL130", FALSE
) ? 130 : 120;
367 /* Unsupported features. */
368 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
369 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
370 case PIPE_CAP_SCALED_RESOLVE
:
371 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS
:
372 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
373 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
374 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
375 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
376 case PIPE_CAP_USER_VERTEX_BUFFERS
:
377 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
378 case PIPE_CAP_QUERY_TIMESTAMP
:
379 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
380 case PIPE_CAP_CUBE_MAP_ARRAY
:
381 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
382 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
383 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
388 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
389 return debug_get_bool_option("R600_STREAMOUT", FALSE
) ? 4 : 0;
390 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
391 return debug_get_bool_option("R600_STREAMOUT", FALSE
) ? 1 : 0;
392 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
393 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
396 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
397 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
398 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
399 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
403 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
404 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
405 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
407 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
409 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
412 /* Render targets. */
413 case PIPE_CAP_MAX_RENDER_TARGETS
:
414 /* FIXME some r6xx are buggy and can only do 4 */
417 /* Timer queries, present when the clock frequency is non zero. */
418 case PIPE_CAP_QUERY_TIME_ELAPSED
:
419 return rscreen
->info
.r600_clock_crystal_freq
!= 0;
421 case PIPE_CAP_MIN_TEXEL_OFFSET
:
424 case PIPE_CAP_MAX_TEXEL_OFFSET
:
430 static float r600_get_paramf(struct pipe_screen
* pscreen
,
431 enum pipe_capf param
)
434 case PIPE_CAPF_MAX_LINE_WIDTH
:
435 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
436 case PIPE_CAPF_MAX_POINT_WIDTH
:
437 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
439 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
441 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
443 case PIPE_CAPF_GUARD_BAND_LEFT
:
444 case PIPE_CAPF_GUARD_BAND_TOP
:
445 case PIPE_CAPF_GUARD_BAND_RIGHT
:
446 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
452 static int r600_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
456 case PIPE_SHADER_FRAGMENT
:
457 case PIPE_SHADER_VERTEX
:
459 case PIPE_SHADER_GEOMETRY
:
460 /* TODO: support and enable geometry programs */
462 case PIPE_SHADER_COMPUTE
:
464 case PIPE_SHADER_CAP_PREFERRED_IR
:
465 return PIPE_SHADER_IR_LLVM
;
470 /* TODO: support tessellation */
475 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
476 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
477 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
478 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
480 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
482 case PIPE_SHADER_CAP_MAX_INPUTS
:
484 case PIPE_SHADER_CAP_MAX_TEMPS
:
485 return 256; /* Max native temporaries. */
486 case PIPE_SHADER_CAP_MAX_ADDRS
:
487 /* FIXME Isn't this equal to TEMPS? */
488 return 1; /* Max native address registers */
489 case PIPE_SHADER_CAP_MAX_CONSTS
:
490 return 4096; /* actually only memory limits this */
491 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
493 case PIPE_SHADER_CAP_MAX_PREDS
:
494 return 0; /* FIXME */
495 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
497 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
499 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
500 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
501 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
502 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
504 case PIPE_SHADER_CAP_INTEGERS
:
506 case PIPE_SHADER_CAP_SUBROUTINES
:
508 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
510 case PIPE_SHADER_CAP_PREFERRED_IR
:
511 return PIPE_SHADER_IR_TGSI
;
516 static int r600_get_video_param(struct pipe_screen
*screen
,
517 enum pipe_video_profile profile
,
518 enum pipe_video_cap param
)
521 case PIPE_VIDEO_CAP_SUPPORTED
:
522 return vl_profile_supported(screen
, profile
);
523 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
525 case PIPE_VIDEO_CAP_MAX_WIDTH
:
526 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
527 return vl_video_buffer_max_size(screen
);
528 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
529 return PIPE_FORMAT_NV12
;
535 static int r600_get_compute_param(struct pipe_screen
*screen
,
536 enum pipe_compute_cap param
,
539 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
540 //TODO: select these params by asic
542 case PIPE_COMPUTE_CAP_IR_TARGET
: {
543 const char *gpu
= r600_get_llvm_processor_name(rscreen
->family
);
545 sprintf(ret
, "%s-r600--", gpu
);
547 return (8 + strlen(gpu
)) * sizeof(char);
549 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
551 uint64_t * grid_dimension
= ret
;
552 grid_dimension
[0] = 3;
554 return 1 * sizeof(uint64_t);
555 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
557 uint64_t * grid_size
= ret
;
558 grid_size
[0] = 65535;
559 grid_size
[1] = 65535;
562 return 3 * sizeof(uint64_t) ;
564 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
566 uint64_t * block_size
= ret
;
571 return 3 * sizeof(uint64_t);
572 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
574 uint64_t * max_threads_per_block
= ret
;
575 *max_threads_per_block
= 256;
577 return sizeof(uint64_t);
580 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
585 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
587 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
592 if (rscreen
->fences
.bo
) {
593 struct r600_fence_block
*entry
, *tmp
;
595 LIST_FOR_EACH_ENTRY_SAFE(entry
, tmp
, &rscreen
->fences
.blocks
, head
) {
596 LIST_DEL(&entry
->head
);
600 rscreen
->ws
->buffer_unmap(rscreen
->fences
.bo
->cs_buf
);
601 si_resource_reference(&rscreen
->fences
.bo
, NULL
);
605 if (rscreen
->trace_bo
) {
606 rscreen
->ws
->buffer_unmap(rscreen
->trace_bo
->cs_buf
);
607 pipe_resource_reference((struct pipe_resource
**)&rscreen
->trace_bo
, NULL
);
611 pipe_mutex_destroy(rscreen
->fences
.mutex
);
613 rscreen
->ws
->destroy(rscreen
->ws
);
617 static void r600_fence_reference(struct pipe_screen
*pscreen
,
618 struct pipe_fence_handle
**ptr
,
619 struct pipe_fence_handle
*fence
)
621 struct r600_fence
**oldf
= (struct r600_fence
**)ptr
;
622 struct r600_fence
*newf
= (struct r600_fence
*)fence
;
624 if (pipe_reference(&(*oldf
)->reference
, &newf
->reference
)) {
625 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
626 pipe_mutex_lock(rscreen
->fences
.mutex
);
627 si_resource_reference(&(*oldf
)->sleep_bo
, NULL
);
628 LIST_ADDTAIL(&(*oldf
)->head
, &rscreen
->fences
.pool
);
629 pipe_mutex_unlock(rscreen
->fences
.mutex
);
635 static boolean
r600_fence_signalled(struct pipe_screen
*pscreen
,
636 struct pipe_fence_handle
*fence
)
638 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
639 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
641 return rscreen
->fences
.data
[rfence
->index
] != 0;
644 static boolean
r600_fence_finish(struct pipe_screen
*pscreen
,
645 struct pipe_fence_handle
*fence
,
648 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
649 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
650 int64_t start_time
= 0;
653 if (timeout
!= PIPE_TIMEOUT_INFINITE
) {
654 start_time
= os_time_get();
656 /* Convert to microseconds. */
660 while (rscreen
->fences
.data
[rfence
->index
] == 0) {
661 /* Special-case infinite timeout - wait for the dummy BO to become idle */
662 if (timeout
== PIPE_TIMEOUT_INFINITE
) {
663 rscreen
->ws
->buffer_wait(rfence
->sleep_bo
->buf
, RADEON_USAGE_READWRITE
);
667 /* The dummy BO will be busy until the CS including the fence has completed, or
668 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
669 if (!rscreen
->ws
->buffer_is_busy(rfence
->sleep_bo
->buf
, RADEON_USAGE_READWRITE
))
679 if (timeout
!= PIPE_TIMEOUT_INFINITE
&&
680 os_time_get() - start_time
>= timeout
) {
685 return rscreen
->fences
.data
[rfence
->index
] != 0;
688 static int evergreen_interpret_tiling(struct r600_screen
*rscreen
, uint32_t tiling_config
)
690 switch (tiling_config
& 0xf) {
692 rscreen
->tiling_info
.num_channels
= 1;
695 rscreen
->tiling_info
.num_channels
= 2;
698 rscreen
->tiling_info
.num_channels
= 4;
701 rscreen
->tiling_info
.num_channels
= 8;
707 switch ((tiling_config
& 0xf0) >> 4) {
709 rscreen
->tiling_info
.num_banks
= 4;
712 rscreen
->tiling_info
.num_banks
= 8;
715 rscreen
->tiling_info
.num_banks
= 16;
721 switch ((tiling_config
& 0xf00) >> 8) {
723 rscreen
->tiling_info
.group_bytes
= 256;
726 rscreen
->tiling_info
.group_bytes
= 512;
734 static int r600_init_tiling(struct r600_screen
*rscreen
)
736 uint32_t tiling_config
= rscreen
->info
.r600_tiling_config
;
738 /* set default group bytes, overridden by tiling info ioctl */
739 rscreen
->tiling_info
.group_bytes
= 512;
744 return evergreen_interpret_tiling(rscreen
, tiling_config
);
747 static unsigned radeon_family_from_device(unsigned device
)
750 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
751 #include "pci_ids/radeonsi_pci_ids.h"
758 struct pipe_screen
*radeonsi_screen_create(struct radeon_winsys
*ws
)
760 struct r600_screen
*rscreen
= CALLOC_STRUCT(r600_screen
);
761 if (rscreen
== NULL
) {
766 ws
->query_info(ws
, &rscreen
->info
);
768 rscreen
->family
= radeon_family_from_device(rscreen
->info
.pci_id
);
769 if (rscreen
->family
== CHIP_UNKNOWN
) {
770 fprintf(stderr
, "r600: Unknown chipset 0x%04X\n", rscreen
->info
.pci_id
);
776 if (rscreen
->family
>= CHIP_TAHITI
) {
777 rscreen
->chip_class
= TAHITI
;
779 fprintf(stderr
, "r600: Unsupported family %d\n", rscreen
->family
);
784 if (r600_init_tiling(rscreen
)) {
789 rscreen
->screen
.destroy
= r600_destroy_screen
;
790 rscreen
->screen
.get_name
= r600_get_name
;
791 rscreen
->screen
.get_vendor
= r600_get_vendor
;
792 rscreen
->screen
.get_param
= r600_get_param
;
793 rscreen
->screen
.get_shader_param
= r600_get_shader_param
;
794 rscreen
->screen
.get_paramf
= r600_get_paramf
;
795 rscreen
->screen
.get_compute_param
= r600_get_compute_param
;
796 rscreen
->screen
.is_format_supported
= si_is_format_supported
;
797 rscreen
->screen
.context_create
= r600_create_context
;
798 rscreen
->screen
.fence_reference
= r600_fence_reference
;
799 rscreen
->screen
.fence_signalled
= r600_fence_signalled
;
800 rscreen
->screen
.fence_finish
= r600_fence_finish
;
801 r600_init_screen_resource_functions(&rscreen
->screen
);
803 if (rscreen
->info
.has_uvd
) {
804 rscreen
->screen
.get_video_param
= ruvd_get_video_param
;
805 rscreen
->screen
.is_video_format_supported
= ruvd_is_format_supported
;
807 rscreen
->screen
.get_video_param
= r600_get_video_param
;
808 rscreen
->screen
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
811 util_format_s3tc_init();
813 rscreen
->fences
.bo
= NULL
;
814 rscreen
->fences
.data
= NULL
;
815 rscreen
->fences
.next_index
= 0;
816 LIST_INITHEAD(&rscreen
->fences
.pool
);
817 LIST_INITHEAD(&rscreen
->fences
.blocks
);
818 pipe_mutex_init(rscreen
->fences
.mutex
);
821 rscreen
->cs_count
= 0;
822 if (rscreen
->info
.drm_minor
>= 28) {
823 rscreen
->trace_bo
= (struct si_resource
*)pipe_buffer_create(&rscreen
->screen
,
827 if (rscreen
->trace_bo
) {
828 rscreen
->trace_ptr
= rscreen
->ws
->buffer_map(rscreen
->trace_bo
->cs_buf
, NULL
,
829 PIPE_TRANSFER_UNSYNCHRONIZED
);
834 return &rscreen
->screen
;