src/gallium/drivers/radeonsi/radeonsi_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_simple_shaders.h"
  41 #include "util/u_upload_mgr.h"
  42 #include "vl/vl_decoder.h"
  43 #include "vl/vl_video_buffer.h"
  44 #include "os/os_time.h"
  45 #include "pipebuffer/pb_buffer.h"
  46 #include "radeonsi_pipe.h"
  47 #include "radeon/radeon_uvd.h"
  48 #include "r600.h"
  49 #include "sid.h"
  50 #include "r600_resource.h"
  51 #include "radeonsi_pipe.h"
  52 #include "r600_hw_context_priv.h"
  53 #include "si_state.h"
  54
  55 /*
  56  * pipe_context
  57  */
  58 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  59 {
  60         struct r600_screen *rscreen = rctx->screen;
  61         struct r600_fence *fence = NULL;
  62
  63         pipe_mutex_lock(rscreen->fences.mutex);
  64
  65         if (!rscreen->fences.bo) {
  66                 /* Create the shared buffer object */
  67                 rscreen->fences.bo = si_resource_create_custom(&rscreen->screen,
  68                                                                PIPE_USAGE_STAGING,
  69                                                                4096);
  70                 if (!rscreen->fences.bo) {
  71                         R600_ERR("r600: failed to create bo for fence objects\n");
  72                         goto out;
  73                 }
  74                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  75                                                            rctx->cs,
  76                                                            PIPE_TRANSFER_READ_WRITE);
  77         }
  78
  79         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  80                 struct r600_fence *entry;
  81
  82                 /* Try to find a freed fence that has been signalled */
  83                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  84                         if (rscreen->fences.data[entry->index] != 0) {
  85                                 LIST_DELINIT(&entry->head);
  86                                 fence = entry;
  87                                 break;
  88                         }
  89                 }
  90         }
  91
  92         if (!fence) {
  93                 /* Allocate a new fence */
  94                 struct r600_fence_block *block;
  95                 unsigned index;
  96
  97                 if ((rscreen->fences.next_index + 1) >= 1024) {
  98                         R600_ERR("r600: too many concurrent fences\n");
  99                         goto out;
 100                 }
 101
 102                 index = rscreen->fences.next_index++;
 103
 104                 if (!(index % FENCE_BLOCK_SIZE)) {
 105                         /* Allocate a new block */
 106                         block = CALLOC_STRUCT(r600_fence_block);
 107                         if (block == NULL)
 108                                 goto out;
 109
 110                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 111                 } else {
 112                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 113                 }
 114
 115                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 116                 fence->index = index;
 117         }
 118
 119         pipe_reference_init(&fence->reference, 1);
 120
 121         rscreen->fences.data[fence->index] = 0;
 122         si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 123
 124         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 125         fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
 126
 127         /* Add the fence as a dummy relocation. */
 128         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 129
 130 out:
 131         pipe_mutex_unlock(rscreen->fences.mutex);
 132         return fence;
 133 }
 134
 135
 136 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 137                     unsigned flags)
 138 {
 139         struct r600_context *rctx = (struct r600_context *)ctx;
 140         struct r600_fence **rfence = (struct r600_fence**)fence;
 141         struct pipe_query *render_cond = NULL;
 142         boolean render_cond_cond = FALSE;
 143         unsigned render_cond_mode = 0;
 144
 145         if (rfence)
 146                 *rfence = r600_create_fence(rctx);
 147
 148         /* Disable render condition. */
 149         if (rctx->current_render_cond) {
 150                 render_cond = rctx->current_render_cond;
 151                 render_cond_cond = rctx->current_render_cond_cond;
 152                 render_cond_mode = rctx->current_render_cond_mode;
 153                 ctx->render_condition(ctx, NULL, FALSE, 0);
 154         }
 155
 156         si_context_flush(rctx, flags);
 157
 158         /* Re-enable render condition. */
 159         if (render_cond) {
 160                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
 161         }
 162 }
 163
 164 static void r600_flush_from_st(struct pipe_context *ctx,
 165                                struct pipe_fence_handle **fence,
 166                                unsigned flags)
 167 {
 168         radeonsi_flush(ctx, fence,
 169                        flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
 170 }
 171
 172 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 173 {
 174         radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
 175 }
 176
 177 static void r600_destroy_context(struct pipe_context *context)
 178 {
 179         struct r600_context *rctx = (struct r600_context *)context;
 180
 181         si_release_all_descriptors(rctx);
 182
 183         si_resource_reference(&rctx->border_color_table, NULL);
 184
 185         if (rctx->dummy_pixel_shader) {
 186                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 187         }
 188         for (int i = 0; i < 8; i++) {
 189                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth_stencil[i]);
 190                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth[i]);
 191                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_stencil[i]);
 192         }
 193         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_inplace);
 194         rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
 195         rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
 196         util_unreference_framebuffer_state(&rctx->framebuffer);
 197
 198         util_blitter_destroy(rctx->blitter);
 199
 200         if (rctx->uploader) {
 201                 u_upload_destroy(rctx->uploader);
 202         }
 203         util_slab_destroy(&rctx->pool_transfers);
 204         FREE(rctx);
 205 }
 206
 207 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 208 {
 209         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 210         struct r600_screen* rscreen = (struct r600_screen *)screen;
 211
 212         if (rctx == NULL)
 213                 return NULL;
 214
 215         rctx->context.screen = screen;
 216         rctx->context.priv = priv;
 217         rctx->context.destroy = r600_destroy_context;
 218         rctx->context.flush = r600_flush_from_st;
 219
 220         /* Easy accessing of screen/winsys. */
 221         rctx->screen = rscreen;
 222         rctx->ws = rscreen->ws;
 223         rctx->family = rscreen->family;
 224         rctx->chip_class = rscreen->chip_class;
 225
 226         si_init_blit_functions(rctx);
 227         r600_init_query_functions(rctx);
 228         r600_init_context_resource_functions(rctx);
 229         si_init_surface_functions(rctx);
 230         si_init_compute_functions(rctx);
 231
 232         if (rscreen->info.has_uvd) {
 233                 rctx->context.create_video_codec = radeonsi_uvd_create_decoder;
 234                 rctx->context.create_video_buffer = radeonsi_video_buffer_create;
 235         } else {
 236                 rctx->context.create_video_codec = vl_create_decoder;
 237                 rctx->context.create_video_buffer = vl_video_buffer_create;
 238         }
 239
 240         rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
 241
 242         si_init_all_descriptors(rctx);
 243
 244         switch (rctx->chip_class) {
 245         case SI:
 246         case CIK:
 247                 si_init_state_functions(rctx);
 248                 LIST_INITHEAD(&rctx->active_query_list);
 249                 rctx->max_db = 8;
 250                 si_init_config(rctx);
 251                 break;
 252         default:
 253                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 254                 r600_destroy_context(&rctx->context);
 255                 return NULL;
 256         }
 257
 258         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 259
 260         util_slab_create(&rctx->pool_transfers,
 261                          sizeof(struct pipe_transfer), 64,
 262                          UTIL_SLAB_SINGLETHREADED);
 263
 264         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 265                                          PIPE_BIND_INDEX_BUFFER |
 266                                          PIPE_BIND_CONSTANT_BUFFER);
 267         if (!rctx->uploader) {
 268                 r600_destroy_context(&rctx->context);
 269                 return NULL;
 270         }
 271
 272         rctx->blitter = util_blitter_create(&rctx->context);
 273         if (rctx->blitter == NULL) {
 274                 r600_destroy_context(&rctx->context);
 275                 return NULL;
 276         }
 277
 278         si_get_backend_mask(rctx); /* this emits commands and must be last */
 279
 280         rctx->dummy_pixel_shader =
 281                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 282                                                      TGSI_SEMANTIC_GENERIC,
 283                                                      TGSI_INTERPOLATE_CONSTANT);
 284         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 285
 286         return &rctx->context;
 287 }
 288
 289 /*
 290  * pipe_screen
 291  */
 292 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 293 {
 294         return "X.Org";
 295 }
 296
 297 const char *r600_get_llvm_processor_name(enum radeon_family family)
 298 {
 299         switch (family) {
 300                 case CHIP_TAHITI: return "tahiti";
 301                 case CHIP_PITCAIRN: return "pitcairn";
 302                 case CHIP_VERDE: return "verde";
 303                 case CHIP_OLAND: return "oland";
 304                 case CHIP_HAINAN: return "hainan";
 305                 case CHIP_BONAIRE: return "bonaire";
 306                 case CHIP_KABINI: return "kabini";
 307                 case CHIP_KAVERI: return "kaveri";
 308                 default: return "";
 309         }
 310 }
 311
 312 static const char *r600_get_family_name(enum radeon_family family)
 313 {
 314         switch(family) {
 315         case CHIP_TAHITI: return "AMD TAHITI";
 316         case CHIP_PITCAIRN: return "AMD PITCAIRN";
 317         case CHIP_VERDE: return "AMD CAPE VERDE";
 318         case CHIP_OLAND: return "AMD OLAND";
 319         case CHIP_HAINAN: return "AMD HAINAN";
 320         case CHIP_BONAIRE: return "AMD BONAIRE";
 321         case CHIP_KAVERI: return "AMD KAVERI";
 322         case CHIP_KABINI: return "AMD KABINI";
 323         default: return "AMD unknown";
 324         }
 325 }
 326
 327 static const char* r600_get_name(struct pipe_screen* pscreen)
 328 {
 329         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 330
 331         return r600_get_family_name(rscreen->family);
 332 }
 333
 334 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 335 {
 336         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 337
 338         switch (param) {
 339         /* Supported features (boolean caps). */
 340         case PIPE_CAP_TWO_SIDED_STENCIL:
 341         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 342         case PIPE_CAP_ANISOTROPIC_FILTER:
 343         case PIPE_CAP_POINT_SPRITE:
 344         case PIPE_CAP_OCCLUSION_QUERY:
 345         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 346         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 347         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 348         case PIPE_CAP_TEXTURE_SWIZZLE:
 349         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 350         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 351         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 352         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 353         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 354         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 355         case PIPE_CAP_SM3:
 356         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 357         case PIPE_CAP_PRIMITIVE_RESTART:
 358         case PIPE_CAP_CONDITIONAL_RENDER:
 359         case PIPE_CAP_TEXTURE_BARRIER:
 360         case PIPE_CAP_INDEP_BLEND_ENABLE:
 361         case PIPE_CAP_INDEP_BLEND_FUNC:
 362         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 363         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 364         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 365         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 366         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 367         case PIPE_CAP_USER_INDEX_BUFFERS:
 368         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 369         case PIPE_CAP_START_INSTANCE:
 370         case PIPE_CAP_NPOT_TEXTURES:
 371         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 372         case PIPE_CAP_TGSI_INSTANCEID:
 373         case PIPE_CAP_COMPUTE:
 374                 return 1;
 375
 376         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 377                 return HAVE_LLVM >= 0x0304 && rscreen->chip_class == SI;
 378
 379         case PIPE_CAP_TGSI_TEXCOORD:
 380                 return 0;
 381
 382         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 383                 return 64;
 384
 385         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 386                 return 256;
 387
 388         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 389                 return 130;
 390
 391         /* Unsupported features. */
 392         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 393         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 394         case PIPE_CAP_SCALED_RESOLVE:
 395         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 396         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 397         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 398         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 399         case PIPE_CAP_USER_VERTEX_BUFFERS:
 400         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 401         case PIPE_CAP_CUBE_MAP_ARRAY:
 402         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 403         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 404         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 405         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 406                 return 0;
 407
 408         /* Stream output. */
 409 #if 0
 410         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 411                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 412         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 413                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
 414         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 415         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 416                 return 16*4;
 417 #endif
 418         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 419         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 420         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 421         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 422                 return 0;
 423
 424         /* Texturing. */
 425         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 426         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 427         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 428                         return 15;
 429         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 430                 return 16384;
 431         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 432                 return 32;
 433
 434         /* Render targets. */
 435         case PIPE_CAP_MAX_RENDER_TARGETS:
 436                 /* FIXME some r6xx are buggy and can only do 4 */
 437                 return 8;
 438
 439         /* Timer queries, present when the clock frequency is non zero. */
 440         case PIPE_CAP_QUERY_TIMESTAMP:
 441         case PIPE_CAP_QUERY_TIME_ELAPSED:
 442                 return rscreen->info.r600_clock_crystal_freq != 0;
 443
 444         case PIPE_CAP_MIN_TEXEL_OFFSET:
 445                 return -8;
 446
 447         case PIPE_CAP_MAX_TEXEL_OFFSET:
 448                 return 7;
 449         case PIPE_CAP_ENDIANNESS:
 450                 return PIPE_ENDIAN_LITTLE;
 451         }
 452         return 0;
 453 }
 454
 455 static float r600_get_paramf(struct pipe_screen* pscreen,
 456                              enum pipe_capf param)
 457 {
 458         switch (param) {
 459         case PIPE_CAPF_MAX_LINE_WIDTH:
 460         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 461         case PIPE_CAPF_MAX_POINT_WIDTH:
 462         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 463                 return 16384.0f;
 464         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 465                 return 16.0f;
 466         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 467                 return 16.0f;
 468         case PIPE_CAPF_GUARD_BAND_LEFT:
 469         case PIPE_CAPF_GUARD_BAND_TOP:
 470         case PIPE_CAPF_GUARD_BAND_RIGHT:
 471         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 472                 return 0.0f;
 473         }
 474         return 0.0f;
 475 }
 476
 477 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 478 {
 479         switch(shader)
 480         {
 481         case PIPE_SHADER_FRAGMENT:
 482         case PIPE_SHADER_VERTEX:
 483                 break;
 484         case PIPE_SHADER_GEOMETRY:
 485                 /* TODO: support and enable geometry programs */
 486                 return 0;
 487         case PIPE_SHADER_COMPUTE:
 488                 switch (param) {
 489                 case PIPE_SHADER_CAP_PREFERRED_IR:
 490                         return PIPE_SHADER_IR_LLVM;
 491                 default:
 492                         return 0;
 493                 }
 494         default:
 495                 /* TODO: support tessellation */
 496                 return 0;
 497         }
 498
 499         switch (param) {
 500         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 501         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 502         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 503         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 504                 return 16384;
 505         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 506                 return 32;
 507         case PIPE_SHADER_CAP_MAX_INPUTS:
 508                 return 32;
 509         case PIPE_SHADER_CAP_MAX_TEMPS:
 510                 return 256; /* Max native temporaries. */
 511         case PIPE_SHADER_CAP_MAX_ADDRS:
 512                 /* FIXME Isn't this equal to TEMPS? */
 513                 return 1; /* Max native address registers */
 514         case PIPE_SHADER_CAP_MAX_CONSTS:
 515                 return 4096; /* actually only memory limits this */
 516         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 517                 return 1;
 518         case PIPE_SHADER_CAP_MAX_PREDS:
 519                 return 0; /* FIXME */
 520         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 521                 return 1;
 522         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 523                 return 0;
 524         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 525         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 526         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 527         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 528                 return 1;
 529         case PIPE_SHADER_CAP_INTEGERS:
 530                 return 1;
 531         case PIPE_SHADER_CAP_SUBROUTINES:
 532                 return 0;
 533         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 534                 return 16;
 535         case PIPE_SHADER_CAP_PREFERRED_IR:
 536                 return PIPE_SHADER_IR_TGSI;
 537         }
 538         return 0;
 539 }
 540
 541 static int r600_get_video_param(struct pipe_screen *screen,
 542                                 enum pipe_video_profile profile,
 543                                 enum pipe_video_entrypoint entrypoint,
 544                                 enum pipe_video_cap param)
 545 {
 546         switch (param) {
 547         case PIPE_VIDEO_CAP_SUPPORTED:
 548                 return vl_profile_supported(screen, profile, entrypoint);
 549         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 550                 return 1;
 551         case PIPE_VIDEO_CAP_MAX_WIDTH:
 552         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 553                 return vl_video_buffer_max_size(screen);
 554         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 555                 return PIPE_FORMAT_NV12;
 556         case PIPE_VIDEO_CAP_MAX_LEVEL:
 557                 return vl_level_supported(screen, profile);
 558         default:
 559                 return 0;
 560         }
 561 }
 562
 563 static int r600_get_compute_param(struct pipe_screen *screen,
 564         enum pipe_compute_cap param,
 565         void *ret)
 566 {
 567         struct r600_screen *rscreen = (struct r600_screen *)screen;
 568         //TODO: select these params by asic
 569         switch (param) {
 570         case PIPE_COMPUTE_CAP_IR_TARGET: {
 571                 const char *gpu = r600_get_llvm_processor_name(rscreen->family);
 572                 if (ret) {
 573                         sprintf(ret, "%s-r600--", gpu);
 574                 }
 575                 return (8 + strlen(gpu)) * sizeof(char);
 576         }
 577         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 578                 if (ret) {
 579                         uint64_t * grid_dimension = ret;
 580                         grid_dimension[0] = 3;
 581                 }
 582                 return 1 * sizeof(uint64_t);
 583         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 584                 if (ret) {
 585                         uint64_t * grid_size = ret;
 586                         grid_size[0] = 65535;
 587                         grid_size[1] = 65535;
 588                         grid_size[2] = 1;
 589                 }
 590                 return 3 * sizeof(uint64_t) ;
 591
 592         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 593                 if (ret) {
 594                         uint64_t * block_size = ret;
 595                         block_size[0] = 256;
 596                         block_size[1] = 256;
 597                         block_size[2] = 256;
 598                 }
 599                 return 3 * sizeof(uint64_t);
 600         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 601                 if (ret) {
 602                         uint64_t * max_threads_per_block = ret;
 603                         *max_threads_per_block = 256;
 604                 }
 605                 return sizeof(uint64_t);
 606
 607         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 608                 if (ret) {
 609                         uint64_t *max_global_size = ret;
 610                         /* XXX: Not sure what to put here. */
 611                         *max_global_size = 2000000000;
 612                 }
 613                 return sizeof(uint64_t);
 614
 615         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 616                 if (ret) {
 617                         uint64_t max_global_size;
 618                         uint64_t *max_mem_alloc_size = ret;
 619                         r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
 620                         *max_mem_alloc_size = max_global_size / 4;
 621                 }
 622                 return sizeof(uint64_t);
 623         default:
 624                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 625                 return 0;
 626         }
 627 }
 628
 629 static void r600_destroy_screen(struct pipe_screen* pscreen)
 630 {
 631         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 632
 633         if (rscreen == NULL)
 634                 return;
 635
 636         if (rscreen->fences.bo) {
 637                 struct r600_fence_block *entry, *tmp;
 638
 639                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 640                         LIST_DEL(&entry->head);
 641                         FREE(entry);
 642                 }
 643
 644                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 645                 si_resource_reference(&rscreen->fences.bo, NULL);
 646         }
 647
 648 #if R600_TRACE_CS
 649         if (rscreen->trace_bo) {
 650                 rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 651                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 652         }
 653 #endif
 654
 655         pipe_mutex_destroy(rscreen->fences.mutex);
 656
 657         rscreen->ws->destroy(rscreen->ws);
 658         FREE(rscreen);
 659 }
 660
 661 static void r600_fence_reference(struct pipe_screen *pscreen,
 662                                  struct pipe_fence_handle **ptr,
 663                                  struct pipe_fence_handle *fence)
 664 {
 665         struct r600_fence **oldf = (struct r600_fence**)ptr;
 666         struct r600_fence *newf = (struct r600_fence*)fence;
 667
 668         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 669                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 670                 pipe_mutex_lock(rscreen->fences.mutex);
 671                 si_resource_reference(&(*oldf)->sleep_bo, NULL);
 672                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 673                 pipe_mutex_unlock(rscreen->fences.mutex);
 674         }
 675
 676         *ptr = fence;
 677 }
 678
 679 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 680                                     struct pipe_fence_handle *fence)
 681 {
 682         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 683         struct r600_fence *rfence = (struct r600_fence*)fence;
 684
 685         return rscreen->fences.data[rfence->index] != 0;
 686 }
 687
 688 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 689                                  struct pipe_fence_handle *fence,
 690                                  uint64_t timeout)
 691 {
 692         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 693         struct r600_fence *rfence = (struct r600_fence*)fence;
 694         int64_t start_time = 0;
 695         unsigned spins = 0;
 696
 697         if (timeout != PIPE_TIMEOUT_INFINITE) {
 698                 start_time = os_time_get();
 699
 700                 /* Convert to microseconds. */
 701                 timeout /= 1000;
 702         }
 703
 704         while (rscreen->fences.data[rfence->index] == 0) {
 705                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 706                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 707                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 708                         break;
 709                 }
 710
 711                 /* The dummy BO will be busy until the CS including the fence has completed, or
 712                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 713                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 714                         break;
 715
 716                 if (++spins % 256)
 717                         continue;
 718 #ifdef PIPE_OS_UNIX
 719                 sched_yield();
 720 #else
 721                 os_time_sleep(10);
 722 #endif
 723                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 724                     os_time_get() - start_time >= timeout) {
 725                         break;
 726                 }
 727         }
 728
 729         return rscreen->fences.data[rfence->index] != 0;
 730 }
 731
 732 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 733 {
 734         switch (tiling_config & 0xf) {
 735         case 0:
 736                 rscreen->tiling_info.num_channels = 1;
 737                 break;
 738         case 1:
 739                 rscreen->tiling_info.num_channels = 2;
 740                 break;
 741         case 2:
 742                 rscreen->tiling_info.num_channels = 4;
 743                 break;
 744         case 3:
 745                 rscreen->tiling_info.num_channels = 8;
 746                 break;
 747         default:
 748                 return -EINVAL;
 749         }
 750
 751         switch ((tiling_config & 0xf0) >> 4) {
 752         case 0:
 753                 rscreen->tiling_info.num_banks = 4;
 754                 break;
 755         case 1:
 756                 rscreen->tiling_info.num_banks = 8;
 757                 break;
 758         case 2:
 759                 rscreen->tiling_info.num_banks = 16;
 760                 break;
 761         default:
 762                 return -EINVAL;
 763         }
 764
 765         switch ((tiling_config & 0xf00) >> 8) {
 766         case 0:
 767                 rscreen->tiling_info.group_bytes = 256;
 768                 break;
 769         case 1:
 770                 rscreen->tiling_info.group_bytes = 512;
 771                 break;
 772         default:
 773                 return -EINVAL;
 774         }
 775         return 0;
 776 }
 777
 778 static int r600_init_tiling(struct r600_screen *rscreen)
 779 {
 780         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 781
 782         /* set default group bytes, overridden by tiling info ioctl */
 783         rscreen->tiling_info.group_bytes = 512;
 784
 785         if (!tiling_config)
 786                 return 0;
 787
 788         return evergreen_interpret_tiling(rscreen, tiling_config);
 789 }
 790
 791 static unsigned radeon_family_from_device(unsigned device)
 792 {
 793         switch (device) {
 794 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 795 #include "pci_ids/radeonsi_pci_ids.h"
 796 #undef CHIPSET
 797         default:
 798                 return CHIP_UNKNOWN;
 799         }
 800 }
 801
 802 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 803 {
 804         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 805         if (rscreen == NULL) {
 806                 return NULL;
 807         }
 808
 809         rscreen->ws = ws;
 810         ws->query_info(ws, &rscreen->info);
 811
 812         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 813         if (rscreen->family == CHIP_UNKNOWN) {
 814                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 815                 FREE(rscreen);
 816                 return NULL;
 817         }
 818
 819         /* setup class */
 820         if (rscreen->family >= CHIP_BONAIRE) {
 821                 rscreen->chip_class = CIK;
 822         } else if (rscreen->family >= CHIP_TAHITI) {
 823                 rscreen->chip_class = SI;
 824         } else {
 825                 fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family);
 826                 FREE(rscreen);
 827                 return NULL;
 828         }
 829
 830         if (r600_init_tiling(rscreen)) {
 831                 FREE(rscreen);
 832                 return NULL;
 833         }
 834
 835         rscreen->screen.destroy = r600_destroy_screen;
 836         rscreen->screen.get_name = r600_get_name;
 837         rscreen->screen.get_vendor = r600_get_vendor;
 838         rscreen->screen.get_param = r600_get_param;
 839         rscreen->screen.get_shader_param = r600_get_shader_param;
 840         rscreen->screen.get_paramf = r600_get_paramf;
 841         rscreen->screen.get_compute_param = r600_get_compute_param;
 842         rscreen->screen.is_format_supported = si_is_format_supported;
 843         rscreen->screen.context_create = r600_create_context;
 844         rscreen->screen.fence_reference = r600_fence_reference;
 845         rscreen->screen.fence_signalled = r600_fence_signalled;
 846         rscreen->screen.fence_finish = r600_fence_finish;
 847         r600_init_screen_resource_functions(&rscreen->screen);
 848
 849         if (rscreen->info.has_uvd) {
 850                 rscreen->screen.get_video_param = ruvd_get_video_param;
 851                 rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
 852         } else {
 853                 rscreen->screen.get_video_param = r600_get_video_param;
 854                 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 855         }
 856
 857         util_format_s3tc_init();
 858
 859         rscreen->fences.bo = NULL;
 860         rscreen->fences.data = NULL;
 861         rscreen->fences.next_index = 0;
 862         LIST_INITHEAD(&rscreen->fences.pool);
 863         LIST_INITHEAD(&rscreen->fences.blocks);
 864         pipe_mutex_init(rscreen->fences.mutex);
 865
 866 #if R600_TRACE_CS
 867         rscreen->cs_count = 0;
 868         if (rscreen->info.drm_minor >= 28) {
 869                 rscreen->trace_bo = (struct si_resource*)pipe_buffer_create(&rscreen->screen,
 870                                                                                 PIPE_BIND_CUSTOM,
 871                                                                                 PIPE_USAGE_STAGING,
 872                                                                                 4096);
 873                 if (rscreen->trace_bo) {
 874                         rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 875                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 876                 }
 877         }
 878 #endif
 879
 880         return &rscreen->screen;
 881 }