src/gallium/drivers/radeonsi/radeonsi_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "r600.h"
  46 #include "sid.h"
  47 #include "r600_resource.h"
  48 #include "radeonsi_pipe.h"
  49 #include "r600_hw_context_priv.h"
  50
  51 /*
  52  * pipe_context
  53  */
  54 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  55 {
  56         struct r600_screen *rscreen = rctx->screen;
  57         struct r600_fence *fence = NULL;
  58
  59         pipe_mutex_lock(rscreen->fences.mutex);
  60
  61         if (!rscreen->fences.bo) {
  62                 /* Create the shared buffer object */
  63                 rscreen->fences.bo = (struct r600_resource*)
  64                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  65                                            PIPE_USAGE_STAGING, 4096);
  66                 if (!rscreen->fences.bo) {
  67                         R600_ERR("r600: failed to create bo for fence objects\n");
  68                         goto out;
  69                 }
  70                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
  71                                                            rctx->cs,
  72                                                            PIPE_TRANSFER_READ_WRITE);
  73         }
  74
  75         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  76                 struct r600_fence *entry;
  77
  78                 /* Try to find a freed fence that has been signalled */
  79                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  80                         if (rscreen->fences.data[entry->index] != 0) {
  81                                 LIST_DELINIT(&entry->head);
  82                                 fence = entry;
  83                                 break;
  84                         }
  85                 }
  86         }
  87
  88         if (!fence) {
  89                 /* Allocate a new fence */
  90                 struct r600_fence_block *block;
  91                 unsigned index;
  92
  93                 if ((rscreen->fences.next_index + 1) >= 1024) {
  94                         R600_ERR("r600: too many concurrent fences\n");
  95                         goto out;
  96                 }
  97
  98                 index = rscreen->fences.next_index++;
  99
 100                 if (!(index % FENCE_BLOCK_SIZE)) {
 101                         /* Allocate a new block */
 102                         block = CALLOC_STRUCT(r600_fence_block);
 103                         if (block == NULL)
 104                                 goto out;
 105
 106                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 107                 } else {
 108                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 109                 }
 110
 111                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 112                 fence->index = index;
 113         }
 114
 115         pipe_reference_init(&fence->reference, 1);
 116
 117         rscreen->fences.data[fence->index] = 0;
 118         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 119
 120         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 121         fence->sleep_bo = (struct r600_resource*)
 122                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 123                                            PIPE_USAGE_STAGING, 1);
 124         /* Add the fence as a dummy relocation. */
 125         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 126
 127 out:
 128         pipe_mutex_unlock(rscreen->fences.mutex);
 129         return fence;
 130 }
 131
 132
 133 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 134                     unsigned flags)
 135 {
 136         struct r600_context *rctx = (struct r600_context *)ctx;
 137         struct r600_fence **rfence = (struct r600_fence**)fence;
 138         struct pipe_query *render_cond = NULL;
 139         unsigned render_cond_mode = 0;
 140
 141         if (rfence)
 142                 *rfence = r600_create_fence(rctx);
 143
 144         /* Disable render condition. */
 145         if (rctx->current_render_cond) {
 146                 render_cond = rctx->current_render_cond;
 147                 render_cond_mode = rctx->current_render_cond_mode;
 148                 ctx->render_condition(ctx, NULL, 0);
 149         }
 150
 151         r600_context_flush(rctx, flags);
 152
 153         /* Re-enable render condition. */
 154         if (render_cond) {
 155                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 156         }
 157 }
 158
 159 static void r600_flush_from_st(struct pipe_context *ctx,
 160                                struct pipe_fence_handle **fence)
 161 {
 162         radeonsi_flush(ctx, fence, 0);
 163 }
 164
 165 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 166 {
 167         radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
 168 }
 169
 170 static void r600_destroy_context(struct pipe_context *context)
 171 {
 172         struct r600_context *rctx = (struct r600_context *)context;
 173
 174         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 175         util_unreference_framebuffer_state(&rctx->framebuffer);
 176
 177         r600_context_fini(rctx);
 178
 179         util_blitter_destroy(rctx->blitter);
 180
 181         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 182                 free(rctx->states[i]);
 183         }
 184
 185         if (rctx->uploader) {
 186                 u_upload_destroy(rctx->uploader);
 187         }
 188         util_slab_destroy(&rctx->pool_transfers);
 189         FREE(rctx);
 190 }
 191
 192 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 193 {
 194         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 195         struct r600_screen* rscreen = (struct r600_screen *)screen;
 196
 197         if (rctx == NULL)
 198                 return NULL;
 199
 200         rctx->context.screen = screen;
 201         rctx->context.priv = priv;
 202         rctx->context.destroy = r600_destroy_context;
 203         rctx->context.flush = r600_flush_from_st;
 204
 205         /* Easy accessing of screen/winsys. */
 206         rctx->screen = rscreen;
 207         rctx->ws = rscreen->ws;
 208         rctx->family = rscreen->family;
 209         rctx->chip_class = rscreen->chip_class;
 210
 211         r600_init_blit_functions(rctx);
 212         r600_init_query_functions(rctx);
 213         r600_init_context_resource_functions(rctx);
 214         r600_init_surface_functions(rctx);
 215         rctx->context.draw_vbo = r600_draw_vbo;
 216
 217         rctx->context.create_video_decoder = vl_create_decoder;
 218         rctx->context.create_video_buffer = vl_video_buffer_create;
 219
 220         r600_init_common_atoms(rctx);
 221
 222         switch (rctx->chip_class) {
 223         case TAHITI:
 224                 cayman_init_state_functions(rctx);
 225                 if (si_context_init(rctx)) {
 226                         r600_destroy_context(&rctx->context);
 227                         return NULL;
 228                 }
 229                 si_init_config(rctx);
 230                 rctx->custom_dsa_flush = cayman_create_db_flush_dsa(rctx);
 231                 break;
 232         default:
 233                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 234                 r600_destroy_context(&rctx->context);
 235                 return NULL;
 236         }
 237
 238         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 239
 240         util_slab_create(&rctx->pool_transfers,
 241                          sizeof(struct pipe_transfer), 64,
 242                          UTIL_SLAB_SINGLETHREADED);
 243
 244         rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
 245                                          PIPE_BIND_INDEX_BUFFER |
 246                                          PIPE_BIND_CONSTANT_BUFFER);
 247         if (!rctx->uploader) {
 248                 r600_destroy_context(&rctx->context);
 249                 return NULL;
 250         }
 251
 252         rctx->blitter = util_blitter_create(&rctx->context);
 253         if (rctx->blitter == NULL) {
 254                 r600_destroy_context(&rctx->context);
 255                 return NULL;
 256         }
 257
 258         LIST_INITHEAD(&rctx->dirty_states);
 259
 260         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 261
 262         return &rctx->context;
 263 }
 264
 265 /*
 266  * pipe_screen
 267  */
 268 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 269 {
 270         return "X.Org";
 271 }
 272
 273 static const char *r600_get_family_name(enum radeon_family family)
 274 {
 275         switch(family) {
 276         case CHIP_CAYMAN: return "AMD CAYMAN";
 277         default: return "AMD unknown";
 278         }
 279 }
 280
 281 static const char* r600_get_name(struct pipe_screen* pscreen)
 282 {
 283         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 284
 285         return r600_get_family_name(rscreen->family);
 286 }
 287
 288 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 289 {
 290         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 291         enum radeon_family family = rscreen->family;
 292
 293         switch (param) {
 294         /* Supported features (boolean caps). */
 295         case PIPE_CAP_NPOT_TEXTURES:
 296         case PIPE_CAP_TWO_SIDED_STENCIL:
 297         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 298         case PIPE_CAP_ANISOTROPIC_FILTER:
 299         case PIPE_CAP_POINT_SPRITE:
 300         case PIPE_CAP_OCCLUSION_QUERY:
 301         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 302         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 303         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 304         case PIPE_CAP_TEXTURE_SWIZZLE:
 305         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 306         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 307         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 308         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 309         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 310         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 311         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 312         case PIPE_CAP_SM3:
 313         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 314         case PIPE_CAP_PRIMITIVE_RESTART:
 315         case PIPE_CAP_CONDITIONAL_RENDER:
 316         case PIPE_CAP_TEXTURE_BARRIER:
 317         case PIPE_CAP_INDEP_BLEND_ENABLE:
 318         case PIPE_CAP_INDEP_BLEND_FUNC:
 319         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 320         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 321         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 322         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 323         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 324         case PIPE_CAP_USER_INDEX_BUFFERS:
 325         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 326                 return 1;
 327
 328         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 329                 return 256;
 330
 331         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 332                 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
 333
 334         /* Unsupported features. */
 335         case PIPE_CAP_TGSI_INSTANCEID:
 336         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 337         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 338         case PIPE_CAP_SCALED_RESOLVE:
 339         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 340         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 341         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 342         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 343         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 344         case PIPE_CAP_USER_VERTEX_BUFFERS:
 345                 return 0;
 346
 347         /* Stream output. */
 348         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 349                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 350         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 351                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
 352         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 353         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 354                 return 16*4;
 355
 356         /* Texturing. */
 357         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 358         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 359         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 360                         return 15;
 361         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 362                 return rscreen->info.drm_minor >= 9 ? 16384 : 0;
 363         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 364                 return 32;
 365
 366         /* Render targets. */
 367         case PIPE_CAP_MAX_RENDER_TARGETS:
 368                 /* FIXME some r6xx are buggy and can only do 4 */
 369                 return 8;
 370
 371         /* Timer queries, present when the clock frequency is non zero. */
 372         case PIPE_CAP_TIMER_QUERY:
 373                 return rscreen->info.r600_clock_crystal_freq != 0;
 374
 375         case PIPE_CAP_MIN_TEXEL_OFFSET:
 376                 return -8;
 377
 378         case PIPE_CAP_MAX_TEXEL_OFFSET:
 379                 return 7;
 380         }
 381         return 0;
 382 }
 383
 384 static float r600_get_paramf(struct pipe_screen* pscreen,
 385                              enum pipe_capf param)
 386 {
 387         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 388         enum radeon_family family = rscreen->family;
 389
 390         switch (param) {
 391         case PIPE_CAPF_MAX_LINE_WIDTH:
 392         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 393         case PIPE_CAPF_MAX_POINT_WIDTH:
 394         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 395                 return 16384.0f;
 396         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 397                 return 16.0f;
 398         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 399                 return 16.0f;
 400         case PIPE_CAPF_GUARD_BAND_LEFT:
 401         case PIPE_CAPF_GUARD_BAND_TOP:
 402         case PIPE_CAPF_GUARD_BAND_RIGHT:
 403         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 404                 return 0.0f;
 405         }
 406         return 0.0f;
 407 }
 408
 409 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 410 {
 411         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 412         switch(shader)
 413         {
 414         case PIPE_SHADER_FRAGMENT:
 415         case PIPE_SHADER_VERTEX:
 416                 break;
 417         case PIPE_SHADER_GEOMETRY:
 418                 /* TODO: support and enable geometry programs */
 419                 return 0;
 420         default:
 421                 /* TODO: support tessellation */
 422                 return 0;
 423         }
 424
 425         /* TODO: all these should be fixed, since r600 surely supports much more! */
 426         switch (param) {
 427         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 428         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 429         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 430         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 431                 return 16384;
 432         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 433                 return 8; /* FIXME */
 434         case PIPE_SHADER_CAP_MAX_INPUTS:
 435                 if(shader == PIPE_SHADER_FRAGMENT)
 436                         return 34;
 437                 else
 438                         return 32;
 439         case PIPE_SHADER_CAP_MAX_TEMPS:
 440                 return 256; /* Max native temporaries. */
 441         case PIPE_SHADER_CAP_MAX_ADDRS:
 442                 /* FIXME Isn't this equal to TEMPS? */
 443                 return 1; /* Max native address registers */
 444         case PIPE_SHADER_CAP_MAX_CONSTS:
 445                 return R600_MAX_CONST_BUFFER_SIZE;
 446         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 447                 return R600_MAX_CONST_BUFFERS;
 448         case PIPE_SHADER_CAP_MAX_PREDS:
 449                 return 0; /* FIXME */
 450         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 451                 return 1;
 452         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 453         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 454         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 455         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 456         case PIPE_SHADER_CAP_INTEGERS:
 457                 return 0;
 458         case PIPE_SHADER_CAP_SUBROUTINES:
 459                 return 0;
 460         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 461                 return 16;
 462         }
 463         return 0;
 464 }
 465
 466 static int r600_get_video_param(struct pipe_screen *screen,
 467                                 enum pipe_video_profile profile,
 468                                 enum pipe_video_cap param)
 469 {
 470         switch (param) {
 471         case PIPE_VIDEO_CAP_SUPPORTED:
 472                 return vl_profile_supported(screen, profile);
 473         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 474                 return 1;
 475         case PIPE_VIDEO_CAP_MAX_WIDTH:
 476         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 477                 return vl_video_buffer_max_size(screen);
 478         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 479                 return PIPE_FORMAT_NV12;
 480         default:
 481                 return 0;
 482         }
 483 }
 484
 485 static void r600_destroy_screen(struct pipe_screen* pscreen)
 486 {
 487         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 488
 489         if (rscreen == NULL)
 490                 return;
 491
 492         if (rscreen->fences.bo) {
 493                 struct r600_fence_block *entry, *tmp;
 494
 495                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 496                         LIST_DEL(&entry->head);
 497                         FREE(entry);
 498                 }
 499
 500                 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
 501                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 502         }
 503         pipe_mutex_destroy(rscreen->fences.mutex);
 504
 505         rscreen->ws->destroy(rscreen->ws);
 506         FREE(rscreen);
 507 }
 508
 509 static void r600_fence_reference(struct pipe_screen *pscreen,
 510                                  struct pipe_fence_handle **ptr,
 511                                  struct pipe_fence_handle *fence)
 512 {
 513         struct r600_fence **oldf = (struct r600_fence**)ptr;
 514         struct r600_fence *newf = (struct r600_fence*)fence;
 515
 516         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 517                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 518                 pipe_mutex_lock(rscreen->fences.mutex);
 519                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 520                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 521                 pipe_mutex_unlock(rscreen->fences.mutex);
 522         }
 523
 524         *ptr = fence;
 525 }
 526
 527 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 528                                     struct pipe_fence_handle *fence)
 529 {
 530         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 531         struct r600_fence *rfence = (struct r600_fence*)fence;
 532
 533         return rscreen->fences.data[rfence->index];
 534 }
 535
 536 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 537                                  struct pipe_fence_handle *fence,
 538                                  uint64_t timeout)
 539 {
 540         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 541         struct r600_fence *rfence = (struct r600_fence*)fence;
 542         int64_t start_time = 0;
 543         unsigned spins = 0;
 544
 545         if (timeout != PIPE_TIMEOUT_INFINITE) {
 546                 start_time = os_time_get();
 547
 548                 /* Convert to microseconds. */
 549                 timeout /= 1000;
 550         }
 551
 552         while (rscreen->fences.data[rfence->index] == 0) {
 553                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 554                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 555                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 556                         break;
 557                 }
 558
 559                 /* The dummy BO will be busy until the CS including the fence has completed, or
 560                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 561                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 562                         break;
 563
 564                 if (++spins % 256)
 565                         continue;
 566 #ifdef PIPE_OS_UNIX
 567                 sched_yield();
 568 #else
 569                 os_time_sleep(10);
 570 #endif
 571                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 572                     os_time_get() - start_time >= timeout) {
 573                         break;
 574                 }
 575         }
 576
 577         return rscreen->fences.data[rfence->index] != 0;
 578 }
 579
 580 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 581 {
 582         switch (tiling_config & 0xf) {
 583         case 0:
 584                 rscreen->tiling_info.num_channels = 1;
 585                 break;
 586         case 1:
 587                 rscreen->tiling_info.num_channels = 2;
 588                 break;
 589         case 2:
 590                 rscreen->tiling_info.num_channels = 4;
 591                 break;
 592         case 3:
 593                 rscreen->tiling_info.num_channels = 8;
 594                 break;
 595         default:
 596                 return -EINVAL;
 597         }
 598
 599         switch ((tiling_config & 0xf0) >> 4) {
 600         case 0:
 601                 rscreen->tiling_info.num_banks = 4;
 602                 break;
 603         case 1:
 604                 rscreen->tiling_info.num_banks = 8;
 605                 break;
 606         case 2:
 607                 rscreen->tiling_info.num_banks = 16;
 608                 break;
 609         default:
 610                 return -EINVAL;
 611         }
 612
 613         switch ((tiling_config & 0xf00) >> 8) {
 614         case 0:
 615                 rscreen->tiling_info.group_bytes = 256;
 616                 break;
 617         case 1:
 618                 rscreen->tiling_info.group_bytes = 512;
 619                 break;
 620         default:
 621                 return -EINVAL;
 622         }
 623         return 0;
 624 }
 625
 626 static int r600_init_tiling(struct r600_screen *rscreen)
 627 {
 628         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 629
 630         /* set default group bytes, overridden by tiling info ioctl */
 631         rscreen->tiling_info.group_bytes = 512;
 632
 633         if (!tiling_config)
 634                 return 0;
 635
 636         return evergreen_interpret_tiling(rscreen, tiling_config);
 637 }
 638
 639 static unsigned radeon_family_from_device(unsigned device)
 640 {
 641         switch (device) {
 642 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 643 #include "pci_ids/radeonsi_pci_ids.h"
 644 #undef CHIPSET
 645         default:
 646                 return CHIP_UNKNOWN;
 647         }
 648 }
 649
 650 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 651 {
 652         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 653         if (rscreen == NULL) {
 654                 return NULL;
 655         }
 656
 657         rscreen->ws = ws;
 658         ws->query_info(ws, &rscreen->info);
 659
 660         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 661         if (rscreen->family == CHIP_UNKNOWN) {
 662                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 663                 FREE(rscreen);
 664                 return NULL;
 665         }
 666
 667         /* setup class */
 668         if (rscreen->family >= CHIP_TAHITI) {
 669                 rscreen->chip_class = TAHITI;
 670         } else {
 671                 fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family);
 672                 FREE(rscreen);
 673                 return NULL;
 674         }
 675
 676         if (r600_init_tiling(rscreen)) {
 677                 FREE(rscreen);
 678                 return NULL;
 679         }
 680
 681         rscreen->screen.destroy = r600_destroy_screen;
 682         rscreen->screen.get_name = r600_get_name;
 683         rscreen->screen.get_vendor = r600_get_vendor;
 684         rscreen->screen.get_param = r600_get_param;
 685         rscreen->screen.get_shader_param = r600_get_shader_param;
 686         rscreen->screen.get_paramf = r600_get_paramf;
 687         rscreen->screen.get_video_param = r600_get_video_param;
 688         rscreen->screen.is_format_supported = si_is_format_supported;
 689         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 690         rscreen->screen.context_create = r600_create_context;
 691         rscreen->screen.fence_reference = r600_fence_reference;
 692         rscreen->screen.fence_signalled = r600_fence_signalled;
 693         rscreen->screen.fence_finish = r600_fence_finish;
 694         r600_init_screen_resource_functions(&rscreen->screen);
 695
 696         util_format_s3tc_init();
 697
 698         rscreen->fences.bo = NULL;
 699         rscreen->fences.data = NULL;
 700         rscreen->fences.next_index = 0;
 701         LIST_INITHEAD(&rscreen->fences.pool);
 702         LIST_INITHEAD(&rscreen->fences.blocks);
 703         pipe_mutex_init(rscreen->fences.mutex);
 704
 705         return &rscreen->screen;
 706 }