2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef RADEONSI_PIPE_H
27 #define RADEONSI_PIPE_H
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_format.h"
35 #include "util/u_math.h"
36 #include "util/u_slab.h"
38 #include "radeonsi_public.h"
39 #include "radeonsi_pm4.h"
41 #include "r600_resource.h"
44 #ifdef PIPE_ARCH_BIG_ENDIAN
45 #define R600_BIG_ENDIAN 1
47 #define R600_BIG_ENDIAN 0
50 struct r600_pipe_fences
{
51 struct si_resource
*bo
;
54 /* linked list of preallocated blocks */
55 struct list_head blocks
;
56 /* linked list of freed fences */
57 struct list_head pool
;
62 struct pipe_screen screen
;
63 struct radeon_winsys
*ws
;
65 enum chip_class chip_class
;
66 struct radeon_info info
;
67 struct r600_tiling_info tiling_info
;
68 struct util_slab_mempool pool_buffers
;
69 struct r600_pipe_fences fences
;
72 struct si_pipe_sampler_view
{
73 struct pipe_sampler_view base
;
74 struct si_resource
*resource
;
78 struct si_pipe_sampler_state
{
80 float border_color
[4];
83 /* needed for blitter save */
84 #define NUM_TEX_UNITS 16
86 struct r600_textures_info
{
87 struct si_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
88 struct si_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
92 bool is_array_sampler
[NUM_TEX_UNITS
];
96 struct pipe_reference reference
;
97 unsigned index
; /* in the shared bo */
98 struct si_resource
*sleep_bo
;
99 struct list_head head
;
102 #define FENCE_BLOCK_SIZE 16
104 struct r600_fence_block
{
105 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
106 struct list_head head
;
109 #define R600_CONSTANT_ARRAY_SIZE 256
110 #define R600_RESOURCE_ARRAY_SIZE 160
112 struct r600_context
{
113 struct pipe_context context
;
114 struct blitter_context
*blitter
;
115 enum radeon_family family
;
116 enum chip_class chip_class
;
117 void *custom_dsa_flush
;
118 struct r600_screen
*screen
;
119 struct radeon_winsys
*ws
;
120 struct si_vertex_element
*vertex_elements
;
121 struct pipe_framebuffer_state framebuffer
;
122 unsigned pa_sc_line_stipple
;
123 unsigned pa_su_sc_mode_cntl
;
124 unsigned pa_cl_clip_cntl
;
125 unsigned pa_cl_vs_out_cntl
;
126 /* for saving when using blitter */
127 struct pipe_stencil_ref stencil_ref
;
128 struct si_pipe_shader_selector
*ps_shader
;
129 struct si_pipe_shader_selector
*vs_shader
;
130 struct pipe_query
*current_render_cond
;
131 unsigned current_render_cond_mode
;
132 struct pipe_query
*saved_render_cond
;
133 unsigned saved_render_cond_mode
;
134 /* shader information */
135 unsigned sprite_coord_enable
;
136 unsigned export_16bpc
;
137 unsigned spi_shader_col_format
;
138 struct r600_textures_info vs_samplers
;
139 struct r600_textures_info ps_samplers
;
140 struct si_resource
*border_color_table
;
141 unsigned border_color_offset
;
143 struct u_upload_mgr
*uploader
;
144 struct util_slab_mempool pool_transfers
;
145 boolean have_depth_texture
, have_depth_fb
;
147 unsigned default_ps_gprs
, default_vs_gprs
;
149 /* Below are variables from the old r600_context.
151 struct radeon_winsys_cs
*cs
;
153 unsigned pm4_dirty_cdwords
;
155 /* The list of active queries. Only one query of each type can be active. */
156 struct list_head active_query_list
;
157 unsigned num_cs_dw_queries_suspend
;
158 unsigned num_cs_dw_streamout_end
;
160 unsigned backend_mask
;
161 unsigned max_db
; /* for OQ */
163 boolean predicate_drawing
;
165 unsigned num_so_targets
;
166 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
167 boolean streamout_start
;
168 unsigned streamout_append_bitmask
;
169 unsigned *vs_so_stride_in_dw
;
170 unsigned *vs_shader_so_strides
;
172 /* Vertex and index buffers. */
173 bool vertex_buffers_dirty
;
174 struct pipe_index_buffer index_buffer
;
175 struct pipe_vertex_buffer vertex_buffer
[PIPE_MAX_ATTRIBS
];
176 unsigned nr_vertex_buffers
;
178 /* With rasterizer discard, there doesn't have to be a pixel shader.
179 * In that case, we bind this one: */
180 struct si_pipe_shader
*dummy_pixel_shader
;
182 /* SI state handling */
183 union si_state queued
;
184 union si_state emitted
;
188 void si_init_blit_functions(struct r600_context
*rctx
);
189 void si_blit_uncompress_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
190 void r600_blit_push_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
191 void si_flush_depth_textures(struct r600_context
*rctx
);
194 bool si_init_resource(struct r600_screen
*rscreen
,
195 struct si_resource
*res
,
196 unsigned size
, unsigned alignment
,
197 boolean use_reusable_pool
, unsigned usage
);
198 struct pipe_resource
*si_buffer_create(struct pipe_screen
*screen
,
199 const struct pipe_resource
*templ
);
200 void r600_upload_index_buffer(struct r600_context
*rctx
,
201 struct pipe_index_buffer
*ib
, unsigned count
);
205 void radeonsi_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
209 void r600_init_query_functions(struct r600_context
*rctx
);
211 /* r600_resource.c */
212 void r600_init_context_resource_functions(struct r600_context
*r600
);
215 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
216 void si_init_surface_functions(struct r600_context
*r600
);
218 /* r600_translate.c */
219 void r600_translate_index_buffer(struct r600_context
*r600
,
220 struct pipe_index_buffer
*ib
,
226 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
228 return value
* (1 << frac_bits
);
230 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
232 static INLINE
unsigned si_map_swizzle(unsigned swizzle
)
235 case UTIL_FORMAT_SWIZZLE_Y
:
236 return V_008F0C_SQ_SEL_Y
;
237 case UTIL_FORMAT_SWIZZLE_Z
:
238 return V_008F0C_SQ_SEL_Z
;
239 case UTIL_FORMAT_SWIZZLE_W
:
240 return V_008F0C_SQ_SEL_W
;
241 case UTIL_FORMAT_SWIZZLE_0
:
242 return V_008F0C_SQ_SEL_0
;
243 case UTIL_FORMAT_SWIZZLE_1
:
244 return V_008F0C_SQ_SEL_1
;
245 default: /* UTIL_FORMAT_SWIZZLE_X */
246 return V_008F0C_SQ_SEL_X
;
250 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
252 if (filter
<= 1) return 0;
253 if (filter
<= 2) return 1;
254 if (filter
<= 4) return 2;
255 if (filter
<= 8) return 3;
259 /* 12.4 fixed-point */
260 static INLINE
unsigned r600_pack_float_12p4(float x
)
263 x
>= 4096 ? 0xffff : x
* 16;
266 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
268 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
269 struct si_resource
*rresource
= (struct si_resource
*)resource
;
271 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);