src/gallium/drivers/radeonsi/radeonsi_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef RADEONSI_PIPE_H
  27 #define RADEONSI_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_format.h"
  35 #include "util/u_math.h"
  36 #include "util/u_slab.h"
  37 #include "r600.h"
  38 #include "radeonsi_public.h"
  39 #include "radeonsi_pm4.h"
  40 #include "si_state.h"
  41 #include "r600_resource.h"
  42 #include "sid.h"
  43
  44 #define R600_MAX_CONST_BUFFERS 1
  45 #define R600_MAX_CONST_BUFFER_SIZE 4096
  46
  47 #ifdef PIPE_ARCH_BIG_ENDIAN
  48 #define R600_BIG_ENDIAN 1
  49 #else
  50 #define R600_BIG_ENDIAN 0
  51 #endif
  52
  53 enum r600_atom_flags {
  54         /* When set, atoms are added at the beginning of the dirty list
  55          * instead of the end. */
  56         EMIT_EARLY = (1 << 0)
  57 };
  58
  59 /* This encapsulates a state or an operation which can emitted into the GPU
  60  * command stream. It's not limited to states only, it can be used for anything
  61  * that wants to write commands into the CS (e.g. cache flushes). */
  62 struct r600_atom {
  63         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  64
  65         unsigned                num_dw;
  66         enum r600_atom_flags    flags;
  67         bool                    dirty;
  68
  69         struct list_head        head;
  70 };
  71
  72 struct r600_atom_surface_sync {
  73         struct r600_atom atom;
  74         unsigned flush_flags; /* CP_COHER_CNTL */
  75 };
  76
  77 enum r600_pipe_state_id {
  78         R600_PIPE_STATE_CONFIG,
  79         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  80         R600_PIPE_STATE_VGT,
  81         R600_PIPE_STATE_DSA,
  82         R600_PIPE_STATE_STENCIL_REF,
  83         R600_PIPE_STATE_PS_SHADER,
  84         R600_PIPE_STATE_VS_SHADER,
  85         R600_PIPE_STATE_CONSTANT,
  86         R600_PIPE_STATE_SAMPLER,
  87         R600_PIPE_STATE_RESOURCE,
  88         R600_PIPE_STATE_POLYGON_OFFSET,
  89         R600_PIPE_NSTATES
  90 };
  91
  92 struct r600_pipe_fences {
  93         struct r600_resource            *bo;
  94         unsigned                        *data;
  95         unsigned                        next_index;
  96         /* linked list of preallocated blocks */
  97         struct list_head                blocks;
  98         /* linked list of freed fences */
  99         struct list_head                pool;
 100         pipe_mutex                      mutex;
 101 };
 102
 103 struct r600_screen {
 104         struct pipe_screen              screen;
 105         struct radeon_winsys            *ws;
 106         unsigned                        family;
 107         enum chip_class                 chip_class;
 108         struct radeon_info              info;
 109         struct r600_tiling_info         tiling_info;
 110         struct util_slab_mempool        pool_buffers;
 111         struct r600_pipe_fences         fences;
 112 };
 113
 114 struct si_pipe_sampler_view {
 115         struct pipe_sampler_view        base;
 116         uint32_t                        state[8];
 117 };
 118
 119 struct si_pipe_sampler_state {
 120         uint32_t                        val[4];
 121 };
 122
 123 struct r600_pipe_dsa {
 124         struct r600_pipe_state          rstate;
 125         unsigned                        alpha_ref;
 126         unsigned                        db_render_override;
 127         unsigned                        db_render_control;
 128         ubyte                           valuemask[2];
 129         ubyte                           writemask[2];
 130 };
 131
 132 struct r600_vertex_element
 133 {
 134         unsigned                        count;
 135         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 136 };
 137
 138 struct r600_shader_io {
 139         unsigned                name;
 140         unsigned                gpr;
 141         unsigned                done;
 142         int                     sid;
 143         unsigned                param_offset;
 144         unsigned                interpolate;
 145         boolean                 centroid;
 146 };
 147
 148 struct r600_shader {
 149         unsigned                ninput;
 150         unsigned                noutput;
 151         struct r600_shader_io   input[32];
 152         struct r600_shader_io   output[32];
 153         boolean                 uses_kill;
 154         boolean                 fs_write_all;
 155         unsigned                nr_cbufs;
 156 };
 157
 158 struct si_pipe_shader {
 159         struct r600_shader              shader;
 160         struct r600_pipe_state          rstate;
 161         struct r600_resource            *bo;
 162         struct r600_vertex_element      vertex_elements;
 163         struct tgsi_token               *tokens;
 164         unsigned                        num_sgprs;
 165         unsigned                        num_vgprs;
 166         unsigned                        spi_ps_input_ena;
 167         unsigned        sprite_coord_enable;
 168         struct pipe_stream_output_info  so;
 169         unsigned                        so_strides[4];
 170 };
 171
 172 /* needed for blitter save */
 173 #define NUM_TEX_UNITS 16
 174
 175 struct r600_textures_info {
 176         struct r600_pipe_state          views_state;
 177         struct r600_pipe_state          samplers_state;
 178         struct si_pipe_sampler_view     *views[NUM_TEX_UNITS];
 179         struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
 180         unsigned                        n_views;
 181         unsigned                        n_samplers;
 182         bool                            samplers_dirty;
 183         bool                            is_array_sampler[NUM_TEX_UNITS];
 184 };
 185
 186 struct r600_fence {
 187         struct pipe_reference           reference;
 188         unsigned                        index; /* in the shared bo */
 189         struct r600_resource            *sleep_bo;
 190         struct list_head                head;
 191 };
 192
 193 #define FENCE_BLOCK_SIZE 16
 194
 195 struct r600_fence_block {
 196         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 197         struct list_head                head;
 198 };
 199
 200 #define R600_CONSTANT_ARRAY_SIZE 256
 201 #define R600_RESOURCE_ARRAY_SIZE 160
 202
 203 struct r600_stencil_ref
 204 {
 205         ubyte ref_value[2];
 206         ubyte valuemask[2];
 207         ubyte writemask[2];
 208 };
 209
 210 struct r600_context {
 211         struct pipe_context             context;
 212         struct blitter_context          *blitter;
 213         enum radeon_family              family;
 214         enum chip_class                 chip_class;
 215         void                            *custom_dsa_flush;
 216         struct r600_screen              *screen;
 217         struct radeon_winsys            *ws;
 218         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 219         struct r600_vertex_element      *vertex_elements;
 220         struct pipe_framebuffer_state   framebuffer;
 221         unsigned                        pa_sc_line_stipple;
 222         unsigned                        pa_su_sc_mode_cntl;
 223         unsigned                        pa_cl_clip_cntl;
 224         unsigned                        pa_cl_vs_out_cntl;
 225         /* for saving when using blitter */
 226         struct pipe_stencil_ref         stencil_ref;
 227         struct r600_pipe_state          config;
 228         struct si_pipe_shader   *ps_shader;
 229         struct si_pipe_shader   *vs_shader;
 230         struct r600_pipe_state          vs_const_buffer;
 231         struct r600_pipe_state          vs_user_data;
 232         struct r600_pipe_state          ps_const_buffer;
 233         struct r600_pipe_state          vgt;
 234         struct r600_pipe_state          spi;
 235         struct pipe_query               *current_render_cond;
 236         unsigned                        current_render_cond_mode;
 237         struct pipe_query               *saved_render_cond;
 238         unsigned                        saved_render_cond_mode;
 239         /* shader information */
 240         unsigned                        sprite_coord_enable;
 241         boolean                         export_16bpc;
 242         unsigned                        alpha_ref;
 243         boolean                         alpha_ref_dirty;
 244         struct r600_textures_info       vs_samplers;
 245         struct r600_textures_info       ps_samplers;
 246         boolean                         shader_dirty;
 247
 248         struct u_upload_mgr             *uploader;
 249         struct util_slab_mempool        pool_transfers;
 250         boolean                         have_depth_texture, have_depth_fb;
 251
 252         unsigned default_ps_gprs, default_vs_gprs;
 253
 254         /* States based on r600_state. */
 255         struct list_head                dirty_states;
 256         struct r600_atom_surface_sync   atom_surface_sync;
 257         struct r600_atom                atom_r6xx_flush_and_inv;
 258
 259         /* Below are variables from the old r600_context.
 260          */
 261         struct radeon_winsys_cs *cs;
 262
 263         struct r600_range       *range;
 264         unsigned                nblocks;
 265         struct r600_block       **blocks;
 266         struct list_head        dirty;
 267         struct list_head        enable_list;
 268         unsigned                pm4_dirty_cdwords;
 269         unsigned                ctx_pm4_ndwords;
 270         unsigned                init_dwords;
 271
 272         /* The list of active queries. Only one query of each type can be active. */
 273         struct list_head        active_query_list;
 274         unsigned                num_cs_dw_queries_suspend;
 275         unsigned                num_cs_dw_streamout_end;
 276
 277         unsigned                backend_mask;
 278         unsigned                max_db; /* for OQ */
 279         unsigned                flags;
 280         boolean                 predicate_drawing;
 281
 282         unsigned                num_so_targets;
 283         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 284         boolean                 streamout_start;
 285         unsigned                streamout_append_bitmask;
 286         unsigned                *vs_so_stride_in_dw;
 287         unsigned                *vs_shader_so_strides;
 288
 289         /* Vertex and index buffers. */
 290         bool                    vertex_buffers_dirty;
 291         struct pipe_index_buffer index_buffer;
 292         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 293         unsigned                nr_vertex_buffers;
 294
 295         /* SI state handling */
 296         union si_state  queued;
 297         union si_state  emitted;
 298 };
 299
 300 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 301 {
 302         atom->emit(rctx, atom);
 303         atom->dirty = false;
 304         if (atom->head.next && atom->head.prev)
 305                 LIST_DELINIT(&atom->head);
 306 }
 307
 308 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 309 {
 310         if (!state->dirty) {
 311                 if (state->flags & EMIT_EARLY) {
 312                         LIST_ADD(&state->head, &rctx->dirty_states);
 313                 } else {
 314                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 315                 }
 316                 state->dirty = true;
 317         }
 318 }
 319
 320 /* evergreen_state.c */
 321 void cayman_init_state_functions(struct r600_context *rctx);
 322 void si_init_config(struct r600_context *rctx);
 323 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader);
 324 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader);
 325 void si_update_spi_map(struct r600_context *rctx);
 326 void *cayman_create_db_flush_dsa(struct r600_context *rctx);
 327 void cayman_polygon_offset_update(struct r600_context *rctx);
 328 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
 329                                    enum pipe_format format,
 330                                    const struct util_format_description *desc,
 331                                    int first_non_void);
 332 boolean si_is_format_supported(struct pipe_screen *screen,
 333                                enum pipe_format format,
 334                                enum pipe_texture_target target,
 335                                unsigned sample_count,
 336                                unsigned usage);
 337
 338 /* r600_blit.c */
 339 void r600_init_blit_functions(struct r600_context *rctx);
 340 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 341 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 342 void r600_flush_depth_textures(struct r600_context *rctx);
 343
 344 /* r600_buffer.c */
 345 bool r600_init_resource(struct r600_screen *rscreen,
 346                         struct r600_resource *res,
 347                         unsigned size, unsigned alignment,
 348                         unsigned bind, unsigned usage);
 349 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 350                                          const struct pipe_resource *templ);
 351 void r600_upload_index_buffer(struct r600_context *rctx,
 352                               struct pipe_index_buffer *ib, unsigned count);
 353
 354
 355 /* r600_pipe.c */
 356 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 357                     unsigned flags);
 358
 359 /* r600_query.c */
 360 void r600_init_query_functions(struct r600_context *rctx);
 361
 362 /* r600_resource.c */
 363 void r600_init_context_resource_functions(struct r600_context *r600);
 364
 365 /* radeonsi_shader.c */
 366 int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
 367 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
 368
 369 /* r600_texture.c */
 370 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 371 void r600_init_surface_functions(struct r600_context *r600);
 372 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 373                                         unsigned level, unsigned layer);
 374
 375 /* r600_translate.c */
 376 void r600_translate_index_buffer(struct r600_context *r600,
 377                                  struct pipe_index_buffer *ib,
 378                                  unsigned count);
 379
 380 /* r600_state_common.c */
 381 void r600_init_common_atoms(struct r600_context *rctx);
 382 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 383 void r600_texture_barrier(struct pipe_context *ctx);
 384 void r600_set_index_buffer(struct pipe_context *ctx,
 385                            const struct pipe_index_buffer *ib);
 386 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 387                              const struct pipe_vertex_buffer *buffers);
 388 void *si_create_vertex_elements(struct pipe_context *ctx,
 389                                 unsigned count,
 390                                 const struct pipe_vertex_element *elements);
 391 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 392 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 393 void r600_sampler_view_destroy(struct pipe_context *ctx,
 394                                struct pipe_sampler_view *state);
 395 void r600_delete_state(struct pipe_context *ctx, void *state);
 396 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 397 void *si_create_shader_state(struct pipe_context *ctx,
 398                              const struct pipe_shader_state *state);
 399 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 400 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 401 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 402 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 403 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 404                               struct pipe_constant_buffer *cb);
 405 struct pipe_stream_output_target *
 406 r600_create_so_target(struct pipe_context *ctx,
 407                       struct pipe_resource *buffer,
 408                       unsigned buffer_offset,
 409                       unsigned buffer_size);
 410 void r600_so_target_destroy(struct pipe_context *ctx,
 411                             struct pipe_stream_output_target *target);
 412 void r600_set_so_targets(struct pipe_context *ctx,
 413                          unsigned num_targets,
 414                          struct pipe_stream_output_target **targets,
 415                          unsigned append_bitmask);
 416 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 417                                const struct pipe_stencil_ref *state);
 418 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 419
 420 /*
 421  * common helpers
 422  */
 423 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 424 {
 425         return value * (1 << frac_bits);
 426 }
 427 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 428
 429 static INLINE unsigned si_map_swizzle(unsigned swizzle)
 430 {
 431         switch (swizzle) {
 432         case UTIL_FORMAT_SWIZZLE_Y:
 433                 return V_008F0C_SQ_SEL_Y;
 434         case UTIL_FORMAT_SWIZZLE_Z:
 435                 return V_008F0C_SQ_SEL_Z;
 436         case UTIL_FORMAT_SWIZZLE_W:
 437                 return V_008F0C_SQ_SEL_W;
 438         case UTIL_FORMAT_SWIZZLE_0:
 439                 return V_008F0C_SQ_SEL_0;
 440         case UTIL_FORMAT_SWIZZLE_1:
 441                 return V_008F0C_SQ_SEL_1;
 442         default: /* UTIL_FORMAT_SWIZZLE_X */
 443                 return V_008F0C_SQ_SEL_X;
 444         }
 445 }
 446
 447 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 448 {
 449         if (filter <= 1)   return 0;
 450         if (filter <= 2)   return 1;
 451         if (filter <= 4)   return 2;
 452         if (filter <= 8)   return 3;
 453          /* else */        return 4;
 454 }
 455
 456 /* 12.4 fixed-point */
 457 static INLINE unsigned r600_pack_float_12p4(float x)
 458 {
 459         return x <= 0    ? 0 :
 460                x >= 4096 ? 0xffff : x * 16;
 461 }
 462
 463 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 464 {
 465         struct r600_screen *rscreen = (struct r600_screen*)screen;
 466         struct r600_resource *rresource = (struct r600_resource*)resource;
 467
 468         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 469 }
 470
 471 #endif