src/gallium/drivers/radeonsi/radeonsi_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef RADEONSI_PIPE_H
  27 #define RADEONSI_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_format.h"
  35 #include "util/u_math.h"
  36 #include "util/u_slab.h"
  37 #include "r600.h"
  38 #include "radeonsi_public.h"
  39 #include "radeonsi_pm4.h"
  40 #include "si_state.h"
  41 #include "r600_resource.h"
  42 #include "sid.h"
  43
  44 #ifdef PIPE_ARCH_BIG_ENDIAN
  45 #define R600_BIG_ENDIAN 1
  46 #else
  47 #define R600_BIG_ENDIAN 0
  48 #endif
  49
  50 #define R600_TRACE_CS 0
  51 #define R600_TRACE_CS_DWORDS            6
  52
  53 struct si_pipe_compute;
  54
  55 struct r600_pipe_fences {
  56         struct si_resource              *bo;
  57         unsigned                        *data;
  58         unsigned                        next_index;
  59         /* linked list of preallocated blocks */
  60         struct list_head                blocks;
  61         /* linked list of freed fences */
  62         struct list_head                pool;
  63         pipe_mutex                      mutex;
  64 };
  65
  66 struct r600_screen {
  67         struct pipe_screen              screen;
  68         struct radeon_winsys            *ws;
  69         unsigned                        family;
  70         enum chip_class                 chip_class;
  71         struct radeon_info              info;
  72         struct r600_tiling_info         tiling_info;
  73         struct util_slab_mempool        pool_buffers;
  74         struct r600_pipe_fences         fences;
  75 #if R600_TRACE_CS
  76         struct si_resource              *trace_bo;
  77         uint32_t                        *trace_ptr;
  78         unsigned                        cs_count;
  79 #endif
  80 };
  81
  82 struct si_pipe_sampler_view {
  83         struct pipe_sampler_view        base;
  84         struct si_resource              *resource;
  85         uint32_t                        state[8];
  86 };
  87
  88 struct si_pipe_sampler_state {
  89         uint32_t                        val[4];
  90         uint32_t                        border_color[4];
  91 };
  92
  93 struct si_cs_shader_state {
  94         struct si_pipe_compute          *program;
  95 };
  96
  97 /* needed for blitter save */
  98 #define NUM_TEX_UNITS 16
  99
 100 struct r600_textures_info {
 101         struct si_pipe_sampler_view     *views[NUM_TEX_UNITS];
 102         struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
 103         unsigned                        n_views;
 104         uint32_t                        depth_texture_mask; /* which textures are depth */
 105         unsigned                        n_samplers;
 106         bool                            samplers_dirty;
 107         bool                            is_array_sampler[NUM_TEX_UNITS];
 108 };
 109
 110 struct r600_fence {
 111         struct pipe_reference           reference;
 112         unsigned                        index; /* in the shared bo */
 113         struct si_resource            *sleep_bo;
 114         struct list_head                head;
 115 };
 116
 117 #define FENCE_BLOCK_SIZE 16
 118
 119 struct r600_fence_block {
 120         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 121         struct list_head                head;
 122 };
 123
 124 #define R600_CONSTANT_ARRAY_SIZE 256
 125 #define R600_RESOURCE_ARRAY_SIZE 160
 126
 127 struct r600_constbuf_state
 128 {
 129         struct pipe_constant_buffer     cb[2];
 130         uint32_t                        enabled_mask;
 131         uint32_t                        dirty_mask;
 132 };
 133
 134 struct r600_context {
 135         struct pipe_context             context;
 136         struct blitter_context          *blitter;
 137         enum radeon_family              family;
 138         enum chip_class                 chip_class;
 139         void                            *custom_dsa_flush_depth_stencil;
 140         void                            *custom_dsa_flush_depth;
 141         void                            *custom_dsa_flush_stencil;
 142         void                            *custom_dsa_flush_inplace;
 143         struct r600_screen              *screen;
 144         struct radeon_winsys            *ws;
 145         struct si_vertex_element        *vertex_elements;
 146         struct pipe_framebuffer_state   framebuffer;
 147         unsigned                        pa_sc_line_stipple;
 148         unsigned                        pa_su_sc_mode_cntl;
 149         /* for saving when using blitter */
 150         struct pipe_stencil_ref         stencil_ref;
 151         struct si_pipe_shader_selector  *ps_shader;
 152         struct si_pipe_shader_selector  *vs_shader;
 153         struct si_cs_shader_state       cs_shader_state;
 154         struct pipe_query               *current_render_cond;
 155         unsigned                        current_render_cond_mode;
 156         boolean                         current_render_cond_cond;
 157         struct pipe_query               *saved_render_cond;
 158         unsigned                        saved_render_cond_mode;
 159         boolean                         saved_render_cond_cond;
 160         /* shader information */
 161         unsigned                        sprite_coord_enable;
 162         unsigned                        export_16bpc;
 163         struct r600_constbuf_state      constbuf_state[PIPE_SHADER_TYPES];
 164         struct r600_textures_info       vs_samplers;
 165         struct r600_textures_info       ps_samplers;
 166         struct si_resource              *border_color_table;
 167         unsigned                        border_color_offset;
 168
 169         struct u_upload_mgr             *uploader;
 170         struct util_slab_mempool        pool_transfers;
 171
 172         unsigned default_ps_gprs, default_vs_gprs;
 173
 174         /* Below are variables from the old r600_context.
 175          */
 176         struct radeon_winsys_cs *cs;
 177
 178         unsigned                pm4_dirty_cdwords;
 179
 180         /* The list of active queries. Only one query of each type can be active. */
 181         struct list_head        active_query_list;
 182         unsigned                num_cs_dw_queries_suspend;
 183         unsigned                num_cs_dw_streamout_end;
 184
 185         unsigned                backend_mask;
 186         unsigned                max_db; /* for OQ */
 187         unsigned                flags;
 188         boolean                 predicate_drawing;
 189
 190         unsigned                num_so_targets;
 191         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 192         boolean                 streamout_start;
 193         unsigned                streamout_append_bitmask;
 194         unsigned                *vs_so_stride_in_dw;
 195         unsigned                *vs_shader_so_strides;
 196
 197         /* Vertex and index buffers. */
 198         bool                    vertex_buffers_dirty;
 199         struct pipe_index_buffer index_buffer;
 200         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 201         unsigned                nr_vertex_buffers;
 202
 203         /* With rasterizer discard, there doesn't have to be a pixel shader.
 204          * In that case, we bind this one: */
 205         struct si_pipe_shader   *dummy_pixel_shader;
 206
 207         /* SI state handling */
 208         union si_state  queued;
 209         union si_state  emitted;
 210 };
 211
 212 /* r600_blit.c */
 213 void si_init_blit_functions(struct r600_context *rctx);
 214 void si_blit_uncompress_depth(struct pipe_context *ctx,
 215                 struct r600_texture *texture,
 216                 struct r600_texture *staging,
 217                 unsigned first_level, unsigned last_level,
 218                 unsigned first_layer, unsigned last_layer);
 219 void si_flush_depth_textures(struct r600_context *rctx,
 220                              struct r600_textures_info *textures);
 221
 222 /* r600_buffer.c */
 223 bool si_init_resource(struct r600_screen *rscreen,
 224                       struct si_resource *res,
 225                       unsigned size, unsigned alignment,
 226                       boolean use_reusable_pool, unsigned usage);
 227 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 228                                        const struct pipe_resource *templ);
 229 void r600_upload_index_buffer(struct r600_context *rctx,
 230                               struct pipe_index_buffer *ib, unsigned count);
 231
 232
 233 /* r600_pipe.c */
 234 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 235                     unsigned flags);
 236 const char *r600_get_llvm_processor_name(enum radeon_family family);
 237
 238 /* r600_query.c */
 239 void r600_init_query_functions(struct r600_context *rctx);
 240
 241 /* r600_resource.c */
 242 void r600_init_context_resource_functions(struct r600_context *r600);
 243
 244 /* r600_texture.c */
 245 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 246 void si_init_surface_functions(struct r600_context *r600);
 247
 248 /* r600_translate.c */
 249 void r600_translate_index_buffer(struct r600_context *r600,
 250                                  struct pipe_index_buffer *ib,
 251                                  unsigned count);
 252
 253 #if R600_TRACE_CS
 254 void r600_trace_emit(struct r600_context *rctx);
 255 #endif
 256
 257 /* radeonsi_compute.c */
 258 void si_init_compute_functions(struct r600_context *rctx);
 259
 260 /* radeonsi_uvd.c */
 261 struct pipe_video_decoder *radeonsi_uvd_create_decoder(struct pipe_context *context,
 262                                                        enum pipe_video_profile profile,
 263                                                        enum pipe_video_entrypoint entrypoint,
 264                                                        enum pipe_video_chroma_format chroma_format,
 265                                                        unsigned width, unsigned height,
 266                                                        unsigned max_references, bool expect_chunked_decode);
 267
 268 struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe,
 269                                                        const struct pipe_video_buffer *tmpl);
 270
 271 /*
 272  * common helpers
 273  */
 274 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 275 {
 276         return value * (1 << frac_bits);
 277 }
 278 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 279
 280 static INLINE unsigned si_map_swizzle(unsigned swizzle)
 281 {
 282         switch (swizzle) {
 283         case UTIL_FORMAT_SWIZZLE_Y:
 284                 return V_008F0C_SQ_SEL_Y;
 285         case UTIL_FORMAT_SWIZZLE_Z:
 286                 return V_008F0C_SQ_SEL_Z;
 287         case UTIL_FORMAT_SWIZZLE_W:
 288                 return V_008F0C_SQ_SEL_W;
 289         case UTIL_FORMAT_SWIZZLE_0:
 290                 return V_008F0C_SQ_SEL_0;
 291         case UTIL_FORMAT_SWIZZLE_1:
 292                 return V_008F0C_SQ_SEL_1;
 293         default: /* UTIL_FORMAT_SWIZZLE_X */
 294                 return V_008F0C_SQ_SEL_X;
 295         }
 296 }
 297
 298 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 299 {
 300         if (filter <= 1)   return 0;
 301         if (filter <= 2)   return 1;
 302         if (filter <= 4)   return 2;
 303         if (filter <= 8)   return 3;
 304          /* else */        return 4;
 305 }
 306
 307 /* 12.4 fixed-point */
 308 static INLINE unsigned r600_pack_float_12p4(float x)
 309 {
 310         return x <= 0    ? 0 :
 311                x >= 4096 ? 0xffff : x * 16;
 312 }
 313
 314 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 315 {
 316         struct r600_screen *rscreen = (struct r600_screen*)screen;
 317         struct si_resource *rresource = (struct si_resource*)resource;
 318
 319         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 320 }
 321
 322 #endif