src/gallium/drivers/radeonsi/radeonsi_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef RADEONSI_PIPE_H
  27 #define RADEONSI_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_format.h"
  35 #include "util/u_math.h"
  36 #include "util/u_slab.h"
  37 #include "r600.h"
  38 #include "radeonsi_public.h"
  39 #include "radeonsi_pm4.h"
  40 #include "si_state.h"
  41 #include "r600_resource.h"
  42 #include "sid.h"
  43
  44 #define R600_MAX_CONST_BUFFERS 1
  45 #define R600_MAX_CONST_BUFFER_SIZE 4096
  46
  47 #ifdef PIPE_ARCH_BIG_ENDIAN
  48 #define R600_BIG_ENDIAN 1
  49 #else
  50 #define R600_BIG_ENDIAN 0
  51 #endif
  52
  53 enum r600_atom_flags {
  54         /* When set, atoms are added at the beginning of the dirty list
  55          * instead of the end. */
  56         EMIT_EARLY = (1 << 0)
  57 };
  58
  59 /* This encapsulates a state or an operation which can emitted into the GPU
  60  * command stream. It's not limited to states only, it can be used for anything
  61  * that wants to write commands into the CS (e.g. cache flushes). */
  62 struct r600_atom {
  63         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  64
  65         unsigned                num_dw;
  66         enum r600_atom_flags    flags;
  67         bool                    dirty;
  68
  69         struct list_head        head;
  70 };
  71
  72 struct r600_atom_surface_sync {
  73         struct r600_atom atom;
  74         unsigned flush_flags; /* CP_COHER_CNTL */
  75 };
  76
  77 enum r600_pipe_state_id {
  78         R600_PIPE_STATE_CONFIG,
  79         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  80         R600_PIPE_STATE_VGT,
  81         R600_PIPE_STATE_PS_SHADER,
  82         R600_PIPE_STATE_VS_SHADER,
  83         R600_PIPE_STATE_CONSTANT,
  84         R600_PIPE_STATE_SAMPLER,
  85         R600_PIPE_STATE_RESOURCE,
  86         R600_PIPE_NSTATES
  87 };
  88
  89 struct r600_pipe_fences {
  90         struct r600_resource            *bo;
  91         unsigned                        *data;
  92         unsigned                        next_index;
  93         /* linked list of preallocated blocks */
  94         struct list_head                blocks;
  95         /* linked list of freed fences */
  96         struct list_head                pool;
  97         pipe_mutex                      mutex;
  98 };
  99
 100 struct r600_screen {
 101         struct pipe_screen              screen;
 102         struct radeon_winsys            *ws;
 103         unsigned                        family;
 104         enum chip_class                 chip_class;
 105         struct radeon_info              info;
 106         struct r600_tiling_info         tiling_info;
 107         struct util_slab_mempool        pool_buffers;
 108         struct r600_pipe_fences         fences;
 109 };
 110
 111 struct si_pipe_sampler_view {
 112         struct pipe_sampler_view        base;
 113         uint32_t                        state[8];
 114 };
 115
 116 struct si_pipe_sampler_state {
 117         uint32_t                        val[4];
 118 };
 119
 120 struct r600_vertex_element
 121 {
 122         unsigned                        count;
 123         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 124 };
 125
 126 struct r600_shader_io {
 127         unsigned                name;
 128         unsigned                gpr;
 129         unsigned                done;
 130         int                     sid;
 131         unsigned                param_offset;
 132         unsigned                interpolate;
 133         boolean                 centroid;
 134 };
 135
 136 struct r600_shader {
 137         unsigned                ninput;
 138         unsigned                noutput;
 139         struct r600_shader_io   input[32];
 140         struct r600_shader_io   output[32];
 141         boolean                 uses_kill;
 142         boolean                 fs_write_all;
 143         unsigned                nr_cbufs;
 144 };
 145
 146 struct si_pipe_shader {
 147         struct r600_shader              shader;
 148         struct r600_pipe_state          rstate;
 149         struct r600_resource            *bo;
 150         struct r600_vertex_element      vertex_elements;
 151         struct tgsi_token               *tokens;
 152         unsigned                        num_sgprs;
 153         unsigned                        num_vgprs;
 154         unsigned                        spi_ps_input_ena;
 155         unsigned        sprite_coord_enable;
 156         struct pipe_stream_output_info  so;
 157         unsigned                        so_strides[4];
 158 };
 159
 160 /* needed for blitter save */
 161 #define NUM_TEX_UNITS 16
 162
 163 struct r600_textures_info {
 164         struct r600_pipe_state          views_state;
 165         struct r600_pipe_state          samplers_state;
 166         struct si_pipe_sampler_view     *views[NUM_TEX_UNITS];
 167         struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
 168         unsigned                        n_views;
 169         unsigned                        n_samplers;
 170         bool                            samplers_dirty;
 171         bool                            is_array_sampler[NUM_TEX_UNITS];
 172 };
 173
 174 struct r600_fence {
 175         struct pipe_reference           reference;
 176         unsigned                        index; /* in the shared bo */
 177         struct r600_resource            *sleep_bo;
 178         struct list_head                head;
 179 };
 180
 181 #define FENCE_BLOCK_SIZE 16
 182
 183 struct r600_fence_block {
 184         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 185         struct list_head                head;
 186 };
 187
 188 #define R600_CONSTANT_ARRAY_SIZE 256
 189 #define R600_RESOURCE_ARRAY_SIZE 160
 190
 191 struct r600_context {
 192         struct pipe_context             context;
 193         struct blitter_context          *blitter;
 194         enum radeon_family              family;
 195         enum chip_class                 chip_class;
 196         void                            *custom_dsa_flush;
 197         struct r600_screen              *screen;
 198         struct radeon_winsys            *ws;
 199         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 200         struct r600_vertex_element      *vertex_elements;
 201         struct pipe_framebuffer_state   framebuffer;
 202         unsigned                        pa_sc_line_stipple;
 203         unsigned                        pa_su_sc_mode_cntl;
 204         unsigned                        pa_cl_clip_cntl;
 205         unsigned                        pa_cl_vs_out_cntl;
 206         /* for saving when using blitter */
 207         struct pipe_stencil_ref         stencil_ref;
 208         struct r600_pipe_state          config;
 209         struct si_pipe_shader   *ps_shader;
 210         struct si_pipe_shader   *vs_shader;
 211         struct r600_pipe_state          vs_const_buffer;
 212         struct r600_pipe_state          vs_user_data;
 213         struct r600_pipe_state          ps_const_buffer;
 214         struct r600_pipe_state          vgt;
 215         struct r600_pipe_state          spi;
 216         struct pipe_query               *current_render_cond;
 217         unsigned                        current_render_cond_mode;
 218         struct pipe_query               *saved_render_cond;
 219         unsigned                        saved_render_cond_mode;
 220         /* shader information */
 221         unsigned                        sprite_coord_enable;
 222         boolean                         export_16bpc;
 223         unsigned                        alpha_ref;
 224         boolean                         alpha_ref_dirty;
 225         struct r600_textures_info       vs_samplers;
 226         struct r600_textures_info       ps_samplers;
 227         boolean                         shader_dirty;
 228
 229         struct u_upload_mgr             *uploader;
 230         struct util_slab_mempool        pool_transfers;
 231         boolean                         have_depth_texture, have_depth_fb;
 232
 233         unsigned default_ps_gprs, default_vs_gprs;
 234
 235         /* States based on r600_state. */
 236         struct list_head                dirty_states;
 237         struct r600_atom_surface_sync   atom_surface_sync;
 238         struct r600_atom                atom_r6xx_flush_and_inv;
 239
 240         /* Below are variables from the old r600_context.
 241          */
 242         struct radeon_winsys_cs *cs;
 243
 244         struct r600_range       *range;
 245         unsigned                nblocks;
 246         struct r600_block       **blocks;
 247         struct list_head        dirty;
 248         struct list_head        enable_list;
 249         unsigned                pm4_dirty_cdwords;
 250         unsigned                ctx_pm4_ndwords;
 251         unsigned                init_dwords;
 252
 253         /* The list of active queries. Only one query of each type can be active. */
 254         struct list_head        active_query_list;
 255         unsigned                num_cs_dw_queries_suspend;
 256         unsigned                num_cs_dw_streamout_end;
 257
 258         unsigned                backend_mask;
 259         unsigned                max_db; /* for OQ */
 260         unsigned                flags;
 261         boolean                 predicate_drawing;
 262
 263         unsigned                num_so_targets;
 264         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 265         boolean                 streamout_start;
 266         unsigned                streamout_append_bitmask;
 267         unsigned                *vs_so_stride_in_dw;
 268         unsigned                *vs_shader_so_strides;
 269
 270         /* Vertex and index buffers. */
 271         bool                    vertex_buffers_dirty;
 272         struct pipe_index_buffer index_buffer;
 273         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 274         unsigned                nr_vertex_buffers;
 275
 276         /* SI state handling */
 277         union si_state  queued;
 278         union si_state  emitted;
 279 };
 280
 281 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 282 {
 283         atom->emit(rctx, atom);
 284         atom->dirty = false;
 285         if (atom->head.next && atom->head.prev)
 286                 LIST_DELINIT(&atom->head);
 287 }
 288
 289 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 290 {
 291         if (!state->dirty) {
 292                 if (state->flags & EMIT_EARLY) {
 293                         LIST_ADD(&state->head, &rctx->dirty_states);
 294                 } else {
 295                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 296                 }
 297                 state->dirty = true;
 298         }
 299 }
 300
 301 /* evergreen_state.c */
 302 void cayman_init_state_functions(struct r600_context *rctx);
 303 void si_init_config(struct r600_context *rctx);
 304 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader);
 305 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader);
 306 void si_update_spi_map(struct r600_context *rctx);
 307 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
 308                                    enum pipe_format format,
 309                                    const struct util_format_description *desc,
 310                                    int first_non_void);
 311 boolean si_is_format_supported(struct pipe_screen *screen,
 312                                enum pipe_format format,
 313                                enum pipe_texture_target target,
 314                                unsigned sample_count,
 315                                unsigned usage);
 316
 317 /* r600_blit.c */
 318 void r600_init_blit_functions(struct r600_context *rctx);
 319 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 320 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 321 void r600_flush_depth_textures(struct r600_context *rctx);
 322
 323 /* r600_buffer.c */
 324 bool r600_init_resource(struct r600_screen *rscreen,
 325                         struct r600_resource *res,
 326                         unsigned size, unsigned alignment,
 327                         unsigned bind, unsigned usage);
 328 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 329                                          const struct pipe_resource *templ);
 330 void r600_upload_index_buffer(struct r600_context *rctx,
 331                               struct pipe_index_buffer *ib, unsigned count);
 332
 333
 334 /* r600_pipe.c */
 335 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 336                     unsigned flags);
 337
 338 /* r600_query.c */
 339 void r600_init_query_functions(struct r600_context *rctx);
 340
 341 /* r600_resource.c */
 342 void r600_init_context_resource_functions(struct r600_context *r600);
 343
 344 /* radeonsi_shader.c */
 345 int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
 346 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
 347
 348 /* r600_texture.c */
 349 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 350 void r600_init_surface_functions(struct r600_context *r600);
 351 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 352                                         unsigned level, unsigned layer);
 353
 354 /* r600_translate.c */
 355 void r600_translate_index_buffer(struct r600_context *r600,
 356                                  struct pipe_index_buffer *ib,
 357                                  unsigned count);
 358
 359 /* r600_state_common.c */
 360 void r600_init_common_atoms(struct r600_context *rctx);
 361 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 362 void r600_texture_barrier(struct pipe_context *ctx);
 363 void r600_set_index_buffer(struct pipe_context *ctx,
 364                            const struct pipe_index_buffer *ib);
 365 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 366                              const struct pipe_vertex_buffer *buffers);
 367 void *si_create_vertex_elements(struct pipe_context *ctx,
 368                                 unsigned count,
 369                                 const struct pipe_vertex_element *elements);
 370 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 371 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 372 void r600_sampler_view_destroy(struct pipe_context *ctx,
 373                                struct pipe_sampler_view *state);
 374 void r600_delete_state(struct pipe_context *ctx, void *state);
 375 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 376 void *si_create_shader_state(struct pipe_context *ctx,
 377                              const struct pipe_shader_state *state);
 378 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 379 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 380 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 381 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 382 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 383                               struct pipe_constant_buffer *cb);
 384 struct pipe_stream_output_target *
 385 r600_create_so_target(struct pipe_context *ctx,
 386                       struct pipe_resource *buffer,
 387                       unsigned buffer_offset,
 388                       unsigned buffer_size);
 389 void r600_so_target_destroy(struct pipe_context *ctx,
 390                             struct pipe_stream_output_target *target);
 391 void r600_set_so_targets(struct pipe_context *ctx,
 392                          unsigned num_targets,
 393                          struct pipe_stream_output_target **targets,
 394                          unsigned append_bitmask);
 395 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 396
 397 /*
 398  * common helpers
 399  */
 400 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 401 {
 402         return value * (1 << frac_bits);
 403 }
 404 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 405
 406 static INLINE unsigned si_map_swizzle(unsigned swizzle)
 407 {
 408         switch (swizzle) {
 409         case UTIL_FORMAT_SWIZZLE_Y:
 410                 return V_008F0C_SQ_SEL_Y;
 411         case UTIL_FORMAT_SWIZZLE_Z:
 412                 return V_008F0C_SQ_SEL_Z;
 413         case UTIL_FORMAT_SWIZZLE_W:
 414                 return V_008F0C_SQ_SEL_W;
 415         case UTIL_FORMAT_SWIZZLE_0:
 416                 return V_008F0C_SQ_SEL_0;
 417         case UTIL_FORMAT_SWIZZLE_1:
 418                 return V_008F0C_SQ_SEL_1;
 419         default: /* UTIL_FORMAT_SWIZZLE_X */
 420                 return V_008F0C_SQ_SEL_X;
 421         }
 422 }
 423
 424 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 425 {
 426         if (filter <= 1)   return 0;
 427         if (filter <= 2)   return 1;
 428         if (filter <= 4)   return 2;
 429         if (filter <= 8)   return 3;
 430          /* else */        return 4;
 431 }
 432
 433 /* 12.4 fixed-point */
 434 static INLINE unsigned r600_pack_float_12p4(float x)
 435 {
 436         return x <= 0    ? 0 :
 437                x >= 4096 ? 0xffff : x * 16;
 438 }
 439
 440 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 441 {
 442         struct r600_screen *rscreen = (struct r600_screen*)screen;
 443         struct r600_resource *rresource = (struct r600_resource*)resource;
 444
 445         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 446 }
 447
 448 #endif