radeonsi: convert constant buffers to si_descriptors
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef RADEONSI_PIPE_H
27 #define RADEONSI_PIPE_H
28
29 #include "../radeon/r600_pipe_common.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_context.h"
33 #include "util/u_format.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "r600.h"
37 #include "radeonsi_public.h"
38 #include "radeonsi_pm4.h"
39 #include "si_state.h"
40 #include "r600_resource.h"
41 #include "sid.h"
42
43 #ifdef PIPE_ARCH_BIG_ENDIAN
44 #define R600_BIG_ENDIAN 1
45 #else
46 #define R600_BIG_ENDIAN 0
47 #endif
48
49 #define R600_TRACE_CS 0
50 #define R600_TRACE_CS_DWORDS 6
51
52 #define SI_MAX_DRAW_CS_DWORDS 18
53
54 struct si_pipe_compute;
55
56 struct r600_pipe_fences {
57 struct r600_resource *bo;
58 unsigned *data;
59 unsigned next_index;
60 /* linked list of preallocated blocks */
61 struct list_head blocks;
62 /* linked list of freed fences */
63 struct list_head pool;
64 pipe_mutex mutex;
65 };
66
67 struct r600_screen {
68 struct r600_common_screen b;
69 struct r600_tiling_info tiling_info;
70 struct util_slab_mempool pool_buffers;
71 struct r600_pipe_fences fences;
72 #if R600_TRACE_CS
73 struct r600_resource *trace_bo;
74 uint32_t *trace_ptr;
75 unsigned cs_count;
76 #endif
77 };
78
79 struct si_pipe_sampler_view {
80 struct pipe_sampler_view base;
81 struct r600_resource *resource;
82 uint32_t state[8];
83 uint32_t fmask_state[8];
84 };
85
86 struct si_pipe_sampler_state {
87 uint32_t val[4];
88 uint32_t border_color[4];
89 };
90
91 struct si_cs_shader_state {
92 struct si_pipe_compute *program;
93 };
94
95 struct r600_textures_info {
96 struct si_sampler_views views;
97 struct si_pipe_sampler_state *samplers[NUM_TEX_UNITS];
98 unsigned n_views;
99 uint32_t depth_texture_mask; /* which textures are depth */
100 uint32_t compressed_colortex_mask;
101 unsigned n_samplers;
102 };
103
104 struct r600_fence {
105 struct pipe_reference reference;
106 unsigned index; /* in the shared bo */
107 struct r600_resource *sleep_bo;
108 struct list_head head;
109 };
110
111 #define FENCE_BLOCK_SIZE 16
112
113 struct r600_fence_block {
114 struct r600_fence fences[FENCE_BLOCK_SIZE];
115 struct list_head head;
116 };
117
118 #define SI_NUM_ATOMS(rctx) (sizeof((rctx)->atoms)/sizeof((rctx)->atoms.array[0]))
119 #define SI_NUM_SHADERS (PIPE_SHADER_FRAGMENT+1)
120
121 struct r600_context {
122 struct r600_common_context b;
123 struct blitter_context *blitter;
124 void *custom_dsa_flush_depth_stencil[8];
125 void *custom_dsa_flush_depth[8];
126 void *custom_dsa_flush_stencil[8];
127 void *custom_dsa_flush_inplace;
128 void *custom_blend_resolve;
129 void *custom_blend_decompress;
130 struct r600_screen *screen;
131
132 union {
133 struct {
134 struct r600_atom *const_buffers[SI_NUM_SHADERS];
135 struct r600_atom *sampler_views[SI_NUM_SHADERS];
136 };
137 struct r600_atom *array[0];
138 } atoms;
139
140 struct si_vertex_element *vertex_elements;
141 struct pipe_framebuffer_state framebuffer;
142 unsigned fb_log_samples;
143 unsigned fb_cb0_is_integer;
144 unsigned fb_compressed_cb_mask;
145 unsigned pa_sc_line_stipple;
146 unsigned pa_su_sc_mode_cntl;
147 /* for saving when using blitter */
148 struct pipe_stencil_ref stencil_ref;
149 struct si_pipe_shader_selector *ps_shader;
150 struct si_pipe_shader_selector *vs_shader;
151 struct si_cs_shader_state cs_shader_state;
152 struct pipe_query *current_render_cond;
153 unsigned current_render_cond_mode;
154 boolean current_render_cond_cond;
155 struct pipe_query *saved_render_cond;
156 unsigned saved_render_cond_mode;
157 boolean saved_render_cond_cond;
158 /* shader information */
159 unsigned sprite_coord_enable;
160 unsigned export_16bpc;
161 struct si_buffer_resources const_buffers[SI_NUM_SHADERS];
162 struct r600_textures_info samplers[SI_NUM_SHADERS];
163 struct r600_resource *border_color_table;
164 unsigned border_color_offset;
165
166 struct u_upload_mgr *uploader;
167 struct util_slab_mempool pool_transfers;
168
169 unsigned default_ps_gprs, default_vs_gprs;
170
171 /* Below are variables from the old r600_context.
172 */
173 unsigned pm4_dirty_cdwords;
174
175 /* The list of active queries. Only one query of each type can be active. */
176 struct list_head active_nontimer_query_list;
177 unsigned num_cs_dw_nontimer_queries_suspend;
178 unsigned num_cs_dw_streamout_end;
179
180 unsigned backend_mask;
181 unsigned max_db; /* for OQ */
182 unsigned flags;
183 boolean predicate_drawing;
184
185 unsigned num_so_targets;
186 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
187 boolean streamout_start;
188 unsigned streamout_append_bitmask;
189 unsigned *vs_so_stride_in_dw;
190 unsigned *vs_shader_so_strides;
191
192 /* Vertex and index buffers. */
193 bool vertex_buffers_dirty;
194 struct pipe_index_buffer index_buffer;
195 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
196 unsigned nr_vertex_buffers;
197
198 /* With rasterizer discard, there doesn't have to be a pixel shader.
199 * In that case, we bind this one: */
200 struct si_pipe_shader *dummy_pixel_shader;
201
202 /* SI state handling */
203 union si_state queued;
204 union si_state emitted;
205
206 bool flush_and_inv_cb_meta;
207 };
208
209 /* r600_blit.c */
210 void si_init_blit_functions(struct r600_context *rctx);
211 void r600_blit_decompress_depth(struct pipe_context *ctx,
212 struct r600_texture *texture,
213 struct r600_texture *staging,
214 unsigned first_level, unsigned last_level,
215 unsigned first_layer, unsigned last_layer,
216 unsigned first_sample, unsigned last_sample);
217 void si_flush_depth_textures(struct r600_context *rctx,
218 struct r600_textures_info *textures);
219 void r600_decompress_color_textures(struct r600_context *rctx,
220 struct r600_textures_info *textures);
221
222 /* r600_buffer.c */
223 bool si_init_resource(struct r600_screen *rscreen,
224 struct r600_resource *res,
225 unsigned size, unsigned alignment,
226 boolean use_reusable_pool, unsigned usage);
227 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
228 const struct pipe_resource *templ);
229 void r600_upload_index_buffer(struct r600_context *rctx,
230 struct pipe_index_buffer *ib, unsigned count);
231
232
233 /* r600_pipe.c */
234 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
235 unsigned flags);
236 const char *r600_get_llvm_processor_name(enum radeon_family family);
237
238 /* r600_query.c */
239 void r600_init_query_functions(struct r600_context *rctx);
240
241 /* r600_resource.c */
242 void r600_init_context_resource_functions(struct r600_context *r600);
243
244 /* r600_texture.c */
245 void r600_init_screen_texture_functions(struct pipe_screen *screen);
246 void si_init_surface_functions(struct r600_context *r600);
247
248 /* r600_translate.c */
249 void r600_translate_index_buffer(struct r600_context *r600,
250 struct pipe_index_buffer *ib,
251 unsigned count);
252
253 #if R600_TRACE_CS
254 void r600_trace_emit(struct r600_context *rctx);
255 #endif
256
257 /* radeonsi_compute.c */
258 void si_init_compute_functions(struct r600_context *rctx);
259
260 /* radeonsi_uvd.c */
261 struct pipe_video_codec *radeonsi_uvd_create_decoder(struct pipe_context *context,
262 const struct pipe_video_codec *templ);
263
264 struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe,
265 const struct pipe_video_buffer *tmpl);
266
267 /*
268 * common helpers
269 */
270 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
271 {
272 return value * (1 << frac_bits);
273 }
274 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
275
276 static INLINE unsigned si_map_swizzle(unsigned swizzle)
277 {
278 switch (swizzle) {
279 case UTIL_FORMAT_SWIZZLE_Y:
280 return V_008F0C_SQ_SEL_Y;
281 case UTIL_FORMAT_SWIZZLE_Z:
282 return V_008F0C_SQ_SEL_Z;
283 case UTIL_FORMAT_SWIZZLE_W:
284 return V_008F0C_SQ_SEL_W;
285 case UTIL_FORMAT_SWIZZLE_0:
286 return V_008F0C_SQ_SEL_0;
287 case UTIL_FORMAT_SWIZZLE_1:
288 return V_008F0C_SQ_SEL_1;
289 default: /* UTIL_FORMAT_SWIZZLE_X */
290 return V_008F0C_SQ_SEL_X;
291 }
292 }
293
294 static inline unsigned r600_tex_aniso_filter(unsigned filter)
295 {
296 if (filter <= 1) return 0;
297 if (filter <= 2) return 1;
298 if (filter <= 4) return 2;
299 if (filter <= 8) return 3;
300 /* else */ return 4;
301 }
302
303 /* 12.4 fixed-point */
304 static INLINE unsigned r600_pack_float_12p4(float x)
305 {
306 return x <= 0 ? 0 :
307 x >= 4096 ? 0xffff : x * 16;
308 }
309
310 #endif