src/gallium/drivers/radeonsi/radeonsi_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef RADEONSI_PIPE_H
  27 #define RADEONSI_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_format.h"
  35 #include "util/u_math.h"
  36 #include "util/u_slab.h"
  37 #include "r600.h"
  38 #include "radeonsi_public.h"
  39 #include "radeonsi_pm4.h"
  40 #include "si_state.h"
  41 #include "r600_resource.h"
  42 #include "sid.h"
  43
  44 #ifdef PIPE_ARCH_BIG_ENDIAN
  45 #define R600_BIG_ENDIAN 1
  46 #else
  47 #define R600_BIG_ENDIAN 0
  48 #endif
  49
  50 #define R600_TRACE_CS 0
  51 #define R600_TRACE_CS_DWORDS            6
  52
  53 struct si_pipe_compute;
  54
  55 struct r600_pipe_fences {
  56         struct si_resource              *bo;
  57         unsigned                        *data;
  58         unsigned                        next_index;
  59         /* linked list of preallocated blocks */
  60         struct list_head                blocks;
  61         /* linked list of freed fences */
  62         struct list_head                pool;
  63         pipe_mutex                      mutex;
  64 };
  65
  66 struct r600_screen {
  67         struct pipe_screen              screen;
  68         struct radeon_winsys            *ws;
  69         unsigned                        family;
  70         enum chip_class                 chip_class;
  71         struct radeon_info              info;
  72         struct r600_tiling_info         tiling_info;
  73         struct util_slab_mempool        pool_buffers;
  74         struct r600_pipe_fences         fences;
  75 #if R600_TRACE_CS
  76         struct si_resource              *trace_bo;
  77         uint32_t                        *trace_ptr;
  78         unsigned                        cs_count;
  79 #endif
  80 };
  81
  82 struct si_pipe_sampler_view {
  83         struct pipe_sampler_view        base;
  84         struct si_resource              *resource;
  85         uint32_t                        state[8];
  86         uint32_t                        fmask_state[8];
  87 };
  88
  89 struct si_pipe_sampler_state {
  90         uint32_t                        val[4];
  91         uint32_t                        border_color[4];
  92 };
  93
  94 struct si_cs_shader_state {
  95         struct si_pipe_compute          *program;
  96 };
  97
  98 struct r600_textures_info {
  99         struct si_sampler_views         views;
 100         struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
 101         unsigned                        n_views;
 102         uint32_t                        depth_texture_mask; /* which textures are depth */
 103         uint32_t                        compressed_colortex_mask;
 104         unsigned                        n_samplers;
 105         bool                            samplers_dirty;
 106         bool                            is_array_sampler[NUM_TEX_UNITS];
 107 };
 108
 109 struct r600_fence {
 110         struct pipe_reference           reference;
 111         unsigned                        index; /* in the shared bo */
 112         struct si_resource            *sleep_bo;
 113         struct list_head                head;
 114 };
 115
 116 #define FENCE_BLOCK_SIZE 16
 117
 118 struct r600_fence_block {
 119         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 120         struct list_head                head;
 121 };
 122
 123 #define R600_CONSTANT_ARRAY_SIZE 256
 124 #define R600_RESOURCE_ARRAY_SIZE 160
 125
 126 struct r600_constbuf_state
 127 {
 128         struct pipe_constant_buffer     cb[2];
 129         uint32_t                        enabled_mask;
 130         uint32_t                        dirty_mask;
 131 };
 132
 133 #define SI_NUM_ATOMS(rctx) (sizeof((rctx)->atoms)/sizeof((rctx)->atoms.array[0]))
 134 #define SI_NUM_SHADERS (PIPE_SHADER_FRAGMENT+1)
 135
 136 struct r600_context {
 137         struct pipe_context             context;
 138         struct blitter_context          *blitter;
 139         enum radeon_family              family;
 140         enum chip_class                 chip_class;
 141         void                            *custom_dsa_flush_depth_stencil[8];
 142         void                            *custom_dsa_flush_depth[8];
 143         void                            *custom_dsa_flush_stencil[8];
 144         void                            *custom_dsa_flush_inplace;
 145         void                            *custom_blend_resolve;
 146         void                            *custom_blend_decompress;
 147         struct r600_screen              *screen;
 148         struct radeon_winsys            *ws;
 149
 150         union {
 151                 struct {
 152                         struct si_atom *sampler_views[SI_NUM_SHADERS];
 153                 };
 154                 struct si_atom *array[0];
 155         } atoms;
 156
 157         struct si_vertex_element        *vertex_elements;
 158         struct pipe_framebuffer_state   framebuffer;
 159         unsigned                        fb_log_samples;
 160         unsigned                        fb_cb0_is_integer;
 161         unsigned                        fb_compressed_cb_mask;
 162         unsigned                        pa_sc_line_stipple;
 163         unsigned                        pa_su_sc_mode_cntl;
 164         /* for saving when using blitter */
 165         struct pipe_stencil_ref         stencil_ref;
 166         struct si_pipe_shader_selector  *ps_shader;
 167         struct si_pipe_shader_selector  *vs_shader;
 168         struct si_cs_shader_state       cs_shader_state;
 169         struct pipe_query               *current_render_cond;
 170         unsigned                        current_render_cond_mode;
 171         boolean                         current_render_cond_cond;
 172         struct pipe_query               *saved_render_cond;
 173         unsigned                        saved_render_cond_mode;
 174         boolean                         saved_render_cond_cond;
 175         /* shader information */
 176         unsigned                        sprite_coord_enable;
 177         unsigned                        export_16bpc;
 178         struct r600_constbuf_state      constbuf_state[PIPE_SHADER_TYPES];
 179         struct r600_textures_info       samplers[SI_NUM_SHADERS];
 180         struct si_resource              *border_color_table;
 181         unsigned                        border_color_offset;
 182
 183         struct u_upload_mgr             *uploader;
 184         struct util_slab_mempool        pool_transfers;
 185
 186         unsigned default_ps_gprs, default_vs_gprs;
 187
 188         /* Below are variables from the old r600_context.
 189          */
 190         struct radeon_winsys_cs *cs;
 191
 192         unsigned                pm4_dirty_cdwords;
 193
 194         /* The list of active queries. Only one query of each type can be active. */
 195         struct list_head        active_query_list;
 196         unsigned                num_cs_dw_queries_suspend;
 197         unsigned                num_cs_dw_streamout_end;
 198
 199         unsigned                backend_mask;
 200         unsigned                max_db; /* for OQ */
 201         unsigned                flags;
 202         boolean                 predicate_drawing;
 203
 204         unsigned                num_so_targets;
 205         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 206         boolean                 streamout_start;
 207         unsigned                streamout_append_bitmask;
 208         unsigned                *vs_so_stride_in_dw;
 209         unsigned                *vs_shader_so_strides;
 210
 211         /* Vertex and index buffers. */
 212         bool                    vertex_buffers_dirty;
 213         struct pipe_index_buffer index_buffer;
 214         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 215         unsigned                nr_vertex_buffers;
 216
 217         /* With rasterizer discard, there doesn't have to be a pixel shader.
 218          * In that case, we bind this one: */
 219         struct si_pipe_shader   *dummy_pixel_shader;
 220
 221         /* SI state handling */
 222         union si_state  queued;
 223         union si_state  emitted;
 224
 225         bool flush_and_inv_cb_meta;
 226 };
 227
 228 /* r600_blit.c */
 229 void si_init_blit_functions(struct r600_context *rctx);
 230 void r600_blit_decompress_depth(struct pipe_context *ctx,
 231                 struct r600_texture *texture,
 232                 struct r600_texture *staging,
 233                 unsigned first_level, unsigned last_level,
 234                 unsigned first_layer, unsigned last_layer,
 235                 unsigned first_sample, unsigned last_sample);
 236 void si_flush_depth_textures(struct r600_context *rctx,
 237                              struct r600_textures_info *textures);
 238 void r600_decompress_color_textures(struct r600_context *rctx,
 239                                     struct r600_textures_info *textures);
 240
 241 /* r600_buffer.c */
 242 bool si_init_resource(struct r600_screen *rscreen,
 243                       struct si_resource *res,
 244                       unsigned size, unsigned alignment,
 245                       boolean use_reusable_pool, unsigned usage);
 246 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 247                                        const struct pipe_resource *templ);
 248 void r600_upload_index_buffer(struct r600_context *rctx,
 249                               struct pipe_index_buffer *ib, unsigned count);
 250
 251
 252 /* r600_pipe.c */
 253 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 254                     unsigned flags);
 255 const char *r600_get_llvm_processor_name(enum radeon_family family);
 256
 257 /* r600_query.c */
 258 void r600_init_query_functions(struct r600_context *rctx);
 259
 260 /* r600_resource.c */
 261 void r600_init_context_resource_functions(struct r600_context *r600);
 262
 263 /* r600_texture.c */
 264 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 265 void si_init_surface_functions(struct r600_context *r600);
 266
 267 /* r600_translate.c */
 268 void r600_translate_index_buffer(struct r600_context *r600,
 269                                  struct pipe_index_buffer *ib,
 270                                  unsigned count);
 271
 272 #if R600_TRACE_CS
 273 void r600_trace_emit(struct r600_context *rctx);
 274 #endif
 275
 276 /* radeonsi_compute.c */
 277 void si_init_compute_functions(struct r600_context *rctx);
 278
 279 /* radeonsi_uvd.c */
 280 struct pipe_video_decoder *radeonsi_uvd_create_decoder(struct pipe_context *context,
 281                                                        enum pipe_video_profile profile,
 282                                                        enum pipe_video_entrypoint entrypoint,
 283                                                        enum pipe_video_chroma_format chroma_format,
 284                                                        unsigned width, unsigned height,
 285                                                        unsigned max_references, bool expect_chunked_decode);
 286
 287 struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe,
 288                                                        const struct pipe_video_buffer *tmpl);
 289
 290 /*
 291  * common helpers
 292  */
 293 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 294 {
 295         return value * (1 << frac_bits);
 296 }
 297 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 298
 299 static INLINE unsigned si_map_swizzle(unsigned swizzle)
 300 {
 301         switch (swizzle) {
 302         case UTIL_FORMAT_SWIZZLE_Y:
 303                 return V_008F0C_SQ_SEL_Y;
 304         case UTIL_FORMAT_SWIZZLE_Z:
 305                 return V_008F0C_SQ_SEL_Z;
 306         case UTIL_FORMAT_SWIZZLE_W:
 307                 return V_008F0C_SQ_SEL_W;
 308         case UTIL_FORMAT_SWIZZLE_0:
 309                 return V_008F0C_SQ_SEL_0;
 310         case UTIL_FORMAT_SWIZZLE_1:
 311                 return V_008F0C_SQ_SEL_1;
 312         default: /* UTIL_FORMAT_SWIZZLE_X */
 313                 return V_008F0C_SQ_SEL_X;
 314         }
 315 }
 316
 317 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 318 {
 319         if (filter <= 1)   return 0;
 320         if (filter <= 2)   return 1;
 321         if (filter <= 4)   return 2;
 322         if (filter <= 8)   return 3;
 323          /* else */        return 4;
 324 }
 325
 326 /* 12.4 fixed-point */
 327 static INLINE unsigned r600_pack_float_12p4(float x)
 328 {
 329         return x <= 0    ? 0 :
 330                x >= 4096 ? 0xffff : x * 16;
 331 }
 332
 333 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 334 {
 335         struct r600_screen *rscreen = (struct r600_screen*)screen;
 336         struct si_resource *rresource = (struct si_resource*)resource;
 337
 338         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 339 }
 340
 341 #endif