src/gallium/drivers/radeonsi/radeonsi_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef RADEONSI_PIPE_H
  27 #define RADEONSI_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_format.h"
  35 #include "util/u_math.h"
  36 #include "util/u_slab.h"
  37 #include "r600.h"
  38 #include "radeonsi_public.h"
  39 #include "radeonsi_pm4.h"
  40 #include "si_state.h"
  41 #include "r600_resource.h"
  42 #include "sid.h"
  43
  44 #ifdef PIPE_ARCH_BIG_ENDIAN
  45 #define R600_BIG_ENDIAN 1
  46 #else
  47 #define R600_BIG_ENDIAN 0
  48 #endif
  49
  50 struct r600_pipe_fences {
  51         struct si_resource              *bo;
  52         unsigned                        *data;
  53         unsigned                        next_index;
  54         /* linked list of preallocated blocks */
  55         struct list_head                blocks;
  56         /* linked list of freed fences */
  57         struct list_head                pool;
  58         pipe_mutex                      mutex;
  59 };
  60
  61 struct r600_screen {
  62         struct pipe_screen              screen;
  63         struct radeon_winsys            *ws;
  64         unsigned                        family;
  65         enum chip_class                 chip_class;
  66         struct radeon_info              info;
  67         struct r600_tiling_info         tiling_info;
  68         struct util_slab_mempool        pool_buffers;
  69         struct r600_pipe_fences         fences;
  70 };
  71
  72 struct si_pipe_sampler_view {
  73         struct pipe_sampler_view        base;
  74         struct si_resource              *resource;
  75         uint32_t                        state[8];
  76 };
  77
  78 struct si_pipe_sampler_state {
  79         uint32_t                        val[4];
  80         float                           border_color[4];
  81 };
  82
  83 /* needed for blitter save */
  84 #define NUM_TEX_UNITS 16
  85
  86 struct r600_textures_info {
  87         struct si_pipe_sampler_view     *views[NUM_TEX_UNITS];
  88         struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
  89         unsigned                        n_views;
  90         unsigned                        n_samplers;
  91         bool                            samplers_dirty;
  92         bool                            is_array_sampler[NUM_TEX_UNITS];
  93 };
  94
  95 struct r600_fence {
  96         struct pipe_reference           reference;
  97         unsigned                        index; /* in the shared bo */
  98         struct si_resource            *sleep_bo;
  99         struct list_head                head;
 100 };
 101
 102 #define FENCE_BLOCK_SIZE 16
 103
 104 struct r600_fence_block {
 105         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 106         struct list_head                head;
 107 };
 108
 109 #define R600_CONSTANT_ARRAY_SIZE 256
 110 #define R600_RESOURCE_ARRAY_SIZE 160
 111
 112 struct r600_context {
 113         struct pipe_context             context;
 114         struct blitter_context          *blitter;
 115         enum radeon_family              family;
 116         enum chip_class                 chip_class;
 117         void                            *custom_dsa_flush;
 118         struct r600_screen              *screen;
 119         struct radeon_winsys            *ws;
 120         struct si_vertex_element        *vertex_elements;
 121         struct pipe_framebuffer_state   framebuffer;
 122         unsigned                        pa_sc_line_stipple;
 123         unsigned                        pa_su_sc_mode_cntl;
 124         unsigned                        pa_cl_clip_cntl;
 125         unsigned                        pa_cl_vs_out_cntl;
 126         /* for saving when using blitter */
 127         struct pipe_stencil_ref         stencil_ref;
 128         struct si_pipe_shader_selector  *ps_shader;
 129         struct si_pipe_shader_selector  *vs_shader;
 130         struct pipe_query               *current_render_cond;
 131         unsigned                        current_render_cond_mode;
 132         struct pipe_query               *saved_render_cond;
 133         unsigned                        saved_render_cond_mode;
 134         /* shader information */
 135         unsigned                        sprite_coord_enable;
 136         unsigned                        export_16bpc;
 137         struct r600_textures_info       vs_samplers;
 138         struct r600_textures_info       ps_samplers;
 139         struct si_resource              *border_color_table;
 140         unsigned                        border_color_offset;
 141
 142         struct u_upload_mgr             *uploader;
 143         struct util_slab_mempool        pool_transfers;
 144         boolean                         have_depth_texture, have_depth_fb;
 145
 146         unsigned default_ps_gprs, default_vs_gprs;
 147
 148         /* Below are variables from the old r600_context.
 149          */
 150         struct radeon_winsys_cs *cs;
 151
 152         unsigned                pm4_dirty_cdwords;
 153
 154         /* The list of active queries. Only one query of each type can be active. */
 155         struct list_head        active_query_list;
 156         unsigned                num_cs_dw_queries_suspend;
 157         unsigned                num_cs_dw_streamout_end;
 158
 159         unsigned                backend_mask;
 160         unsigned                max_db; /* for OQ */
 161         unsigned                flags;
 162         boolean                 predicate_drawing;
 163
 164         unsigned                num_so_targets;
 165         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 166         boolean                 streamout_start;
 167         unsigned                streamout_append_bitmask;
 168         unsigned                *vs_so_stride_in_dw;
 169         unsigned                *vs_shader_so_strides;
 170
 171         /* Vertex and index buffers. */
 172         bool                    vertex_buffers_dirty;
 173         struct pipe_index_buffer index_buffer;
 174         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 175         unsigned                nr_vertex_buffers;
 176
 177         /* With rasterizer discard, there doesn't have to be a pixel shader.
 178          * In that case, we bind this one: */
 179         struct si_pipe_shader   *dummy_pixel_shader;
 180
 181         /* SI state handling */
 182         union si_state  queued;
 183         union si_state  emitted;
 184 };
 185
 186 /* r600_blit.c */
 187 void si_init_blit_functions(struct r600_context *rctx);
 188 void si_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 189 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 190 void si_flush_depth_textures(struct r600_context *rctx);
 191
 192 /* r600_buffer.c */
 193 bool si_init_resource(struct r600_screen *rscreen,
 194                       struct si_resource *res,
 195                       unsigned size, unsigned alignment,
 196                       boolean use_reusable_pool, unsigned usage);
 197 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 198                                        const struct pipe_resource *templ);
 199 void r600_upload_index_buffer(struct r600_context *rctx,
 200                               struct pipe_index_buffer *ib, unsigned count);
 201
 202
 203 /* r600_pipe.c */
 204 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 205                     unsigned flags);
 206
 207 /* r600_query.c */
 208 void r600_init_query_functions(struct r600_context *rctx);
 209
 210 /* r600_resource.c */
 211 void r600_init_context_resource_functions(struct r600_context *r600);
 212
 213 /* r600_texture.c */
 214 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 215 void si_init_surface_functions(struct r600_context *r600);
 216
 217 /* r600_translate.c */
 218 void r600_translate_index_buffer(struct r600_context *r600,
 219                                  struct pipe_index_buffer *ib,
 220                                  unsigned count);
 221
 222 /*
 223  * common helpers
 224  */
 225 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 226 {
 227         return value * (1 << frac_bits);
 228 }
 229 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 230
 231 static INLINE unsigned si_map_swizzle(unsigned swizzle)
 232 {
 233         switch (swizzle) {
 234         case UTIL_FORMAT_SWIZZLE_Y:
 235                 return V_008F0C_SQ_SEL_Y;
 236         case UTIL_FORMAT_SWIZZLE_Z:
 237                 return V_008F0C_SQ_SEL_Z;
 238         case UTIL_FORMAT_SWIZZLE_W:
 239                 return V_008F0C_SQ_SEL_W;
 240         case UTIL_FORMAT_SWIZZLE_0:
 241                 return V_008F0C_SQ_SEL_0;
 242         case UTIL_FORMAT_SWIZZLE_1:
 243                 return V_008F0C_SQ_SEL_1;
 244         default: /* UTIL_FORMAT_SWIZZLE_X */
 245                 return V_008F0C_SQ_SEL_X;
 246         }
 247 }
 248
 249 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 250 {
 251         if (filter <= 1)   return 0;
 252         if (filter <= 2)   return 1;
 253         if (filter <= 4)   return 2;
 254         if (filter <= 8)   return 3;
 255          /* else */        return 4;
 256 }
 257
 258 /* 12.4 fixed-point */
 259 static INLINE unsigned r600_pack_float_12p4(float x)
 260 {
 261         return x <= 0    ? 0 :
 262                x >= 4096 ? 0xffff : x * 16;
 263 }
 264
 265 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 266 {
 267         struct r600_screen *rscreen = (struct r600_screen*)screen;
 268         struct si_resource *rresource = (struct si_resource*)resource;
 269
 270         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 271 }
 272
 273 #endif