src/gallium/drivers/radeonsi/radeonsi_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef RADEONSI_PIPE_H
  27 #define RADEONSI_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_format.h"
  35 #include "util/u_math.h"
  36 #include "util/u_slab.h"
  37 #include "r600.h"
  38 #include "radeonsi_public.h"
  39 #include "radeonsi_pm4.h"
  40 #include "si_state.h"
  41 #include "r600_resource.h"
  42 #include "sid.h"
  43
  44 #define R600_MAX_CONST_BUFFERS 1
  45 #define R600_MAX_CONST_BUFFER_SIZE 4096
  46
  47 #ifdef PIPE_ARCH_BIG_ENDIAN
  48 #define R600_BIG_ENDIAN 1
  49 #else
  50 #define R600_BIG_ENDIAN 0
  51 #endif
  52
  53 enum r600_atom_flags {
  54         /* When set, atoms are added at the beginning of the dirty list
  55          * instead of the end. */
  56         EMIT_EARLY = (1 << 0)
  57 };
  58
  59 /* This encapsulates a state or an operation which can emitted into the GPU
  60  * command stream. It's not limited to states only, it can be used for anything
  61  * that wants to write commands into the CS (e.g. cache flushes). */
  62 struct r600_atom {
  63         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  64
  65         unsigned                num_dw;
  66         enum r600_atom_flags    flags;
  67         bool                    dirty;
  68
  69         struct list_head        head;
  70 };
  71
  72 struct r600_atom_surface_sync {
  73         struct r600_atom atom;
  74         unsigned flush_flags; /* CP_COHER_CNTL */
  75 };
  76
  77 enum r600_pipe_state_id {
  78         R600_PIPE_STATE_CONFIG,
  79         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  80         R600_PIPE_STATE_PS_SHADER,
  81         R600_PIPE_STATE_VS_SHADER,
  82         R600_PIPE_STATE_CONSTANT,
  83         R600_PIPE_STATE_SAMPLER,
  84         R600_PIPE_STATE_RESOURCE,
  85         R600_PIPE_NSTATES
  86 };
  87
  88 struct r600_pipe_fences {
  89         struct r600_resource            *bo;
  90         unsigned                        *data;
  91         unsigned                        next_index;
  92         /* linked list of preallocated blocks */
  93         struct list_head                blocks;
  94         /* linked list of freed fences */
  95         struct list_head                pool;
  96         pipe_mutex                      mutex;
  97 };
  98
  99 struct r600_screen {
 100         struct pipe_screen              screen;
 101         struct radeon_winsys            *ws;
 102         unsigned                        family;
 103         enum chip_class                 chip_class;
 104         struct radeon_info              info;
 105         struct r600_tiling_info         tiling_info;
 106         struct util_slab_mempool        pool_buffers;
 107         struct r600_pipe_fences         fences;
 108 };
 109
 110 struct si_pipe_sampler_view {
 111         struct pipe_sampler_view        base;
 112         uint32_t                        state[8];
 113 };
 114
 115 struct si_pipe_sampler_state {
 116         uint32_t                        val[4];
 117 };
 118
 119 /* needed for blitter save */
 120 #define NUM_TEX_UNITS 16
 121
 122 struct r600_textures_info {
 123         struct si_pipe_sampler_view     *views[NUM_TEX_UNITS];
 124         struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
 125         unsigned                        n_views;
 126         unsigned                        n_samplers;
 127         bool                            samplers_dirty;
 128         bool                            is_array_sampler[NUM_TEX_UNITS];
 129 };
 130
 131 struct r600_fence {
 132         struct pipe_reference           reference;
 133         unsigned                        index; /* in the shared bo */
 134         struct r600_resource            *sleep_bo;
 135         struct list_head                head;
 136 };
 137
 138 #define FENCE_BLOCK_SIZE 16
 139
 140 struct r600_fence_block {
 141         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 142         struct list_head                head;
 143 };
 144
 145 #define R600_CONSTANT_ARRAY_SIZE 256
 146 #define R600_RESOURCE_ARRAY_SIZE 160
 147
 148 struct r600_context {
 149         struct pipe_context             context;
 150         struct blitter_context          *blitter;
 151         enum radeon_family              family;
 152         enum chip_class                 chip_class;
 153         void                            *custom_dsa_flush;
 154         struct r600_screen              *screen;
 155         struct radeon_winsys            *ws;
 156         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 157         struct si_vertex_element        *vertex_elements;
 158         struct pipe_framebuffer_state   framebuffer;
 159         unsigned                        pa_sc_line_stipple;
 160         unsigned                        pa_su_sc_mode_cntl;
 161         unsigned                        pa_cl_clip_cntl;
 162         unsigned                        pa_cl_vs_out_cntl;
 163         /* for saving when using blitter */
 164         struct pipe_stencil_ref         stencil_ref;
 165         struct r600_pipe_state          config;
 166         struct si_pipe_shader   *ps_shader;
 167         struct si_pipe_shader   *vs_shader;
 168         struct r600_pipe_state          vs_const_buffer;
 169         struct r600_pipe_state          vs_user_data;
 170         struct r600_pipe_state          ps_const_buffer;
 171         struct pipe_query               *current_render_cond;
 172         unsigned                        current_render_cond_mode;
 173         struct pipe_query               *saved_render_cond;
 174         unsigned                        saved_render_cond_mode;
 175         /* shader information */
 176         unsigned                        sprite_coord_enable;
 177         boolean                         export_16bpc;
 178         unsigned                        alpha_ref;
 179         boolean                         alpha_ref_dirty;
 180         struct r600_textures_info       vs_samplers;
 181         struct r600_textures_info       ps_samplers;
 182         boolean                         shader_dirty;
 183
 184         struct u_upload_mgr             *uploader;
 185         struct util_slab_mempool        pool_transfers;
 186         boolean                         have_depth_texture, have_depth_fb;
 187
 188         unsigned default_ps_gprs, default_vs_gprs;
 189
 190         /* States based on r600_state. */
 191         struct list_head                dirty_states;
 192         struct r600_atom_surface_sync   atom_surface_sync;
 193         struct r600_atom                atom_r6xx_flush_and_inv;
 194
 195         /* Below are variables from the old r600_context.
 196          */
 197         struct radeon_winsys_cs *cs;
 198
 199         struct r600_range       *range;
 200         unsigned                nblocks;
 201         struct r600_block       **blocks;
 202         struct list_head        dirty;
 203         struct list_head        enable_list;
 204         unsigned                pm4_dirty_cdwords;
 205         unsigned                ctx_pm4_ndwords;
 206         unsigned                init_dwords;
 207
 208         /* The list of active queries. Only one query of each type can be active. */
 209         struct list_head        active_query_list;
 210         unsigned                num_cs_dw_queries_suspend;
 211         unsigned                num_cs_dw_streamout_end;
 212
 213         unsigned                backend_mask;
 214         unsigned                max_db; /* for OQ */
 215         unsigned                flags;
 216         boolean                 predicate_drawing;
 217
 218         unsigned                num_so_targets;
 219         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 220         boolean                 streamout_start;
 221         unsigned                streamout_append_bitmask;
 222         unsigned                *vs_so_stride_in_dw;
 223         unsigned                *vs_shader_so_strides;
 224
 225         /* Vertex and index buffers. */
 226         bool                    vertex_buffers_dirty;
 227         struct pipe_index_buffer index_buffer;
 228         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 229         unsigned                nr_vertex_buffers;
 230
 231         /* SI state handling */
 232         union si_state  queued;
 233         union si_state  emitted;
 234 };
 235
 236 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 237 {
 238         atom->emit(rctx, atom);
 239         atom->dirty = false;
 240         if (atom->head.next && atom->head.prev)
 241                 LIST_DELINIT(&atom->head);
 242 }
 243
 244 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 245 {
 246         if (!state->dirty) {
 247                 if (state->flags & EMIT_EARLY) {
 248                         LIST_ADD(&state->head, &rctx->dirty_states);
 249                 } else {
 250                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 251                 }
 252                 state->dirty = true;
 253         }
 254 }
 255
 256 /* evergreen_state.c */
 257 void cayman_init_state_functions(struct r600_context *rctx);
 258 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader);
 259 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader);
 260 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
 261                                    enum pipe_format format,
 262                                    const struct util_format_description *desc,
 263                                    int first_non_void);
 264 boolean si_is_format_supported(struct pipe_screen *screen,
 265                                enum pipe_format format,
 266                                enum pipe_texture_target target,
 267                                unsigned sample_count,
 268                                unsigned usage);
 269
 270 /* r600_blit.c */
 271 void r600_init_blit_functions(struct r600_context *rctx);
 272 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 273 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 274 void r600_flush_depth_textures(struct r600_context *rctx);
 275
 276 /* r600_buffer.c */
 277 bool r600_init_resource(struct r600_screen *rscreen,
 278                         struct r600_resource *res,
 279                         unsigned size, unsigned alignment,
 280                         unsigned bind, unsigned usage);
 281 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 282                                          const struct pipe_resource *templ);
 283 void r600_upload_index_buffer(struct r600_context *rctx,
 284                               struct pipe_index_buffer *ib, unsigned count);
 285
 286
 287 /* r600_pipe.c */
 288 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 289                     unsigned flags);
 290
 291 /* r600_query.c */
 292 void r600_init_query_functions(struct r600_context *rctx);
 293
 294 /* r600_resource.c */
 295 void r600_init_context_resource_functions(struct r600_context *r600);
 296
 297 /* radeonsi_shader.c */
 298 int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
 299 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
 300
 301 /* r600_texture.c */
 302 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 303 void r600_init_surface_functions(struct r600_context *r600);
 304 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 305                                         unsigned level, unsigned layer);
 306
 307 /* r600_translate.c */
 308 void r600_translate_index_buffer(struct r600_context *r600,
 309                                  struct pipe_index_buffer *ib,
 310                                  unsigned count);
 311
 312 /* r600_state_common.c */
 313 void r600_init_common_atoms(struct r600_context *rctx);
 314 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 315 void r600_texture_barrier(struct pipe_context *ctx);
 316 void r600_set_index_buffer(struct pipe_context *ctx,
 317                            const struct pipe_index_buffer *ib);
 318 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 319                              const struct pipe_vertex_buffer *buffers);
 320 void *si_create_vertex_elements(struct pipe_context *ctx,
 321                                 unsigned count,
 322                                 const struct pipe_vertex_element *elements);
 323 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 324 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 325 void r600_sampler_view_destroy(struct pipe_context *ctx,
 326                                struct pipe_sampler_view *state);
 327 void r600_delete_state(struct pipe_context *ctx, void *state);
 328 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 329 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 330 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 331 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 332 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 333 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 334                               struct pipe_constant_buffer *cb);
 335 struct pipe_stream_output_target *
 336 r600_create_so_target(struct pipe_context *ctx,
 337                       struct pipe_resource *buffer,
 338                       unsigned buffer_offset,
 339                       unsigned buffer_size);
 340 void r600_so_target_destroy(struct pipe_context *ctx,
 341                             struct pipe_stream_output_target *target);
 342 void r600_set_so_targets(struct pipe_context *ctx,
 343                          unsigned num_targets,
 344                          struct pipe_stream_output_target **targets,
 345                          unsigned append_bitmask);
 346 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 347
 348 /*
 349  * common helpers
 350  */
 351 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 352 {
 353         return value * (1 << frac_bits);
 354 }
 355 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 356
 357 static INLINE unsigned si_map_swizzle(unsigned swizzle)
 358 {
 359         switch (swizzle) {
 360         case UTIL_FORMAT_SWIZZLE_Y:
 361                 return V_008F0C_SQ_SEL_Y;
 362         case UTIL_FORMAT_SWIZZLE_Z:
 363                 return V_008F0C_SQ_SEL_Z;
 364         case UTIL_FORMAT_SWIZZLE_W:
 365                 return V_008F0C_SQ_SEL_W;
 366         case UTIL_FORMAT_SWIZZLE_0:
 367                 return V_008F0C_SQ_SEL_0;
 368         case UTIL_FORMAT_SWIZZLE_1:
 369                 return V_008F0C_SQ_SEL_1;
 370         default: /* UTIL_FORMAT_SWIZZLE_X */
 371                 return V_008F0C_SQ_SEL_X;
 372         }
 373 }
 374
 375 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 376 {
 377         if (filter <= 1)   return 0;
 378         if (filter <= 2)   return 1;
 379         if (filter <= 4)   return 2;
 380         if (filter <= 8)   return 3;
 381          /* else */        return 4;
 382 }
 383
 384 /* 12.4 fixed-point */
 385 static INLINE unsigned r600_pack_float_12p4(float x)
 386 {
 387         return x <= 0    ? 0 :
 388                x >= 4096 ? 0xffff : x * 16;
 389 }
 390
 391 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 392 {
 393         struct r600_screen *rscreen = (struct r600_screen*)screen;
 394         struct r600_resource *rresource = (struct r600_resource*)resource;
 395
 396         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 397 }
 398
 399 #endif