src/gallium/drivers/radeonsi/radeonsi_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef RADEONSI_PIPE_H
  27 #define RADEONSI_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_format.h"
  35 #include "util/u_math.h"
  36 #include "util/u_slab.h"
  37 #include "r600.h"
  38 #include "radeonsi_public.h"
  39 #include "radeonsi_pm4.h"
  40 #include "si_state.h"
  41 #include "r600_resource.h"
  42 #include "sid.h"
  43
  44 #define R600_MAX_CONST_BUFFERS 1
  45 #define R600_MAX_CONST_BUFFER_SIZE 4096
  46
  47 #ifdef PIPE_ARCH_BIG_ENDIAN
  48 #define R600_BIG_ENDIAN 1
  49 #else
  50 #define R600_BIG_ENDIAN 0
  51 #endif
  52
  53 enum r600_atom_flags {
  54         /* When set, atoms are added at the beginning of the dirty list
  55          * instead of the end. */
  56         EMIT_EARLY = (1 << 0)
  57 };
  58
  59 /* This encapsulates a state or an operation which can emitted into the GPU
  60  * command stream. It's not limited to states only, it can be used for anything
  61  * that wants to write commands into the CS (e.g. cache flushes). */
  62 struct r600_atom {
  63         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  64
  65         unsigned                num_dw;
  66         enum r600_atom_flags    flags;
  67         bool                    dirty;
  68
  69         struct list_head        head;
  70 };
  71
  72 struct r600_atom_surface_sync {
  73         struct r600_atom atom;
  74         unsigned flush_flags; /* CP_COHER_CNTL */
  75 };
  76
  77 enum r600_pipe_state_id {
  78         R600_PIPE_STATE_BLEND = 0,
  79         R600_PIPE_STATE_BLEND_COLOR,
  80         R600_PIPE_STATE_CONFIG,
  81         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  82         R600_PIPE_STATE_CLIP,
  83         R600_PIPE_STATE_SCISSOR,
  84         R600_PIPE_STATE_VIEWPORT,
  85         R600_PIPE_STATE_RASTERIZER,
  86         R600_PIPE_STATE_VGT,
  87         R600_PIPE_STATE_FRAMEBUFFER,
  88         R600_PIPE_STATE_DSA,
  89         R600_PIPE_STATE_STENCIL_REF,
  90         R600_PIPE_STATE_PS_SHADER,
  91         R600_PIPE_STATE_VS_SHADER,
  92         R600_PIPE_STATE_CONSTANT,
  93         R600_PIPE_STATE_SAMPLER,
  94         R600_PIPE_STATE_RESOURCE,
  95         R600_PIPE_STATE_POLYGON_OFFSET,
  96         R600_PIPE_NSTATES
  97 };
  98
  99 struct r600_pipe_fences {
 100         struct r600_resource            *bo;
 101         unsigned                        *data;
 102         unsigned                        next_index;
 103         /* linked list of preallocated blocks */
 104         struct list_head                blocks;
 105         /* linked list of freed fences */
 106         struct list_head                pool;
 107         pipe_mutex                      mutex;
 108 };
 109
 110 struct r600_screen {
 111         struct pipe_screen              screen;
 112         struct radeon_winsys            *ws;
 113         unsigned                        family;
 114         enum chip_class                 chip_class;
 115         struct radeon_info              info;
 116         struct r600_tiling_info         tiling_info;
 117         struct util_slab_mempool        pool_buffers;
 118         struct r600_pipe_fences         fences;
 119 };
 120
 121 struct si_pipe_sampler_view {
 122         struct pipe_sampler_view        base;
 123         uint32_t                        state[8];
 124 };
 125
 126 struct si_pipe_sampler_state {
 127         uint32_t                        val[4];
 128 };
 129
 130 struct r600_pipe_rasterizer {
 131         struct r600_pipe_state          rstate;
 132         boolean                         flatshade;
 133         unsigned                        sprite_coord_enable;
 134         unsigned                        pa_sc_line_stipple;
 135         unsigned                        pa_su_sc_mode_cntl;
 136         unsigned                        pa_cl_clip_cntl;
 137         unsigned                        pa_cl_vs_out_cntl;
 138         float                           offset_units;
 139         float                           offset_scale;
 140 };
 141
 142 struct r600_pipe_blend {
 143         struct r600_pipe_state          rstate;
 144         unsigned                        cb_target_mask;
 145         unsigned                        cb_color_control;
 146 };
 147
 148 struct r600_pipe_dsa {
 149         struct r600_pipe_state          rstate;
 150         unsigned                        alpha_ref;
 151         unsigned                        db_render_override;
 152         unsigned                        db_render_control;
 153         ubyte                           valuemask[2];
 154         ubyte                           writemask[2];
 155 };
 156
 157 struct r600_vertex_element
 158 {
 159         unsigned                        count;
 160         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 161 };
 162
 163 struct r600_shader_io {
 164         unsigned                name;
 165         unsigned                gpr;
 166         unsigned                done;
 167         int                     sid;
 168         unsigned                param_offset;
 169         unsigned                interpolate;
 170         boolean                 centroid;
 171 };
 172
 173 struct r600_shader {
 174         unsigned                ninput;
 175         unsigned                noutput;
 176         struct r600_shader_io   input[32];
 177         struct r600_shader_io   output[32];
 178         boolean                 uses_kill;
 179         boolean                 fs_write_all;
 180         unsigned                nr_cbufs;
 181 };
 182
 183 struct si_pipe_shader {
 184         struct r600_shader              shader;
 185         struct r600_pipe_state          rstate;
 186         struct r600_resource            *bo;
 187         struct r600_vertex_element      vertex_elements;
 188         struct tgsi_token               *tokens;
 189         unsigned                        num_sgprs;
 190         unsigned                        num_vgprs;
 191         unsigned                        spi_ps_input_ena;
 192         unsigned        sprite_coord_enable;
 193         struct pipe_stream_output_info  so;
 194         unsigned                        so_strides[4];
 195 };
 196
 197 /* needed for blitter save */
 198 #define NUM_TEX_UNITS 16
 199
 200 struct r600_textures_info {
 201         struct r600_pipe_state          views_state;
 202         struct r600_pipe_state          samplers_state;
 203         struct si_pipe_sampler_view     *views[NUM_TEX_UNITS];
 204         struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
 205         unsigned                        n_views;
 206         unsigned                        n_samplers;
 207         bool                            samplers_dirty;
 208         bool                            is_array_sampler[NUM_TEX_UNITS];
 209 };
 210
 211 struct r600_fence {
 212         struct pipe_reference           reference;
 213         unsigned                        index; /* in the shared bo */
 214         struct r600_resource            *sleep_bo;
 215         struct list_head                head;
 216 };
 217
 218 #define FENCE_BLOCK_SIZE 16
 219
 220 struct r600_fence_block {
 221         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 222         struct list_head                head;
 223 };
 224
 225 #define R600_CONSTANT_ARRAY_SIZE 256
 226 #define R600_RESOURCE_ARRAY_SIZE 160
 227
 228 struct r600_stencil_ref
 229 {
 230         ubyte ref_value[2];
 231         ubyte valuemask[2];
 232         ubyte writemask[2];
 233 };
 234
 235 struct r600_context {
 236         struct pipe_context             context;
 237         struct blitter_context          *blitter;
 238         enum radeon_family              family;
 239         enum chip_class                 chip_class;
 240         void                            *custom_dsa_flush;
 241         struct r600_screen              *screen;
 242         struct radeon_winsys            *ws;
 243         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 244         struct r600_vertex_element      *vertex_elements;
 245         struct pipe_framebuffer_state   framebuffer;
 246         unsigned                        cb_target_mask;
 247         unsigned                        cb_color_control;
 248         unsigned                        pa_sc_line_stipple;
 249         unsigned                        pa_su_sc_mode_cntl;
 250         unsigned                        pa_cl_clip_cntl;
 251         unsigned                        pa_cl_vs_out_cntl;
 252         /* for saving when using blitter */
 253         struct pipe_stencil_ref         stencil_ref;
 254         struct pipe_viewport_state      viewport;
 255         struct pipe_clip_state          clip;
 256         struct r600_pipe_state          config;
 257         struct si_pipe_shader   *ps_shader;
 258         struct si_pipe_shader   *vs_shader;
 259         struct r600_pipe_state          vs_const_buffer;
 260         struct r600_pipe_state          vs_user_data;
 261         struct r600_pipe_state          ps_const_buffer;
 262         struct r600_pipe_rasterizer     *rasterizer;
 263         struct r600_pipe_state          vgt;
 264         struct r600_pipe_state          spi;
 265         struct pipe_query               *current_render_cond;
 266         unsigned                        current_render_cond_mode;
 267         struct pipe_query               *saved_render_cond;
 268         unsigned                        saved_render_cond_mode;
 269         /* shader information */
 270         unsigned                        sprite_coord_enable;
 271         boolean                         export_16bpc;
 272         unsigned                        alpha_ref;
 273         boolean                         alpha_ref_dirty;
 274         unsigned                        nr_cbufs;
 275         struct r600_textures_info       vs_samplers;
 276         struct r600_textures_info       ps_samplers;
 277         boolean                         shader_dirty;
 278
 279         struct u_upload_mgr             *uploader;
 280         struct util_slab_mempool        pool_transfers;
 281         boolean                         have_depth_texture, have_depth_fb;
 282
 283         unsigned default_ps_gprs, default_vs_gprs;
 284
 285         /* States based on r600_state. */
 286         struct list_head                dirty_states;
 287         struct r600_atom_surface_sync   atom_surface_sync;
 288         struct r600_atom                atom_r6xx_flush_and_inv;
 289
 290         /* Below are variables from the old r600_context.
 291          */
 292         struct radeon_winsys_cs *cs;
 293
 294         struct r600_range       *range;
 295         unsigned                nblocks;
 296         struct r600_block       **blocks;
 297         struct list_head        dirty;
 298         struct list_head        enable_list;
 299         unsigned                pm4_dirty_cdwords;
 300         unsigned                ctx_pm4_ndwords;
 301         unsigned                init_dwords;
 302
 303         /* The list of active queries. Only one query of each type can be active. */
 304         struct list_head        active_query_list;
 305         unsigned                num_cs_dw_queries_suspend;
 306         unsigned                num_cs_dw_streamout_end;
 307
 308         unsigned                backend_mask;
 309         unsigned                max_db; /* for OQ */
 310         unsigned                flags;
 311         boolean                 predicate_drawing;
 312
 313         unsigned                num_so_targets;
 314         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 315         boolean                 streamout_start;
 316         unsigned                streamout_append_bitmask;
 317         unsigned                *vs_so_stride_in_dw;
 318         unsigned                *vs_shader_so_strides;
 319
 320         /* Vertex and index buffers. */
 321         bool                    vertex_buffers_dirty;
 322         struct pipe_index_buffer index_buffer;
 323         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 324         unsigned                nr_vertex_buffers;
 325
 326         /* SI state handling */
 327         union si_state  queued;
 328         union si_state  emitted;
 329 };
 330
 331 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 332 {
 333         atom->emit(rctx, atom);
 334         atom->dirty = false;
 335         if (atom->head.next && atom->head.prev)
 336                 LIST_DELINIT(&atom->head);
 337 }
 338
 339 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 340 {
 341         if (!state->dirty) {
 342                 if (state->flags & EMIT_EARLY) {
 343                         LIST_ADD(&state->head, &rctx->dirty_states);
 344                 } else {
 345                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 346                 }
 347                 state->dirty = true;
 348         }
 349 }
 350
 351 /* evergreen_state.c */
 352 void cayman_init_state_functions(struct r600_context *rctx);
 353 void si_init_config(struct r600_context *rctx);
 354 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader);
 355 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader);
 356 void si_update_spi_map(struct r600_context *rctx);
 357 void *cayman_create_db_flush_dsa(struct r600_context *rctx);
 358 void cayman_polygon_offset_update(struct r600_context *rctx);
 359 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
 360                                    enum pipe_format format,
 361                                    const struct util_format_description *desc,
 362                                    int first_non_void);
 363 boolean si_is_format_supported(struct pipe_screen *screen,
 364                                enum pipe_format format,
 365                                enum pipe_texture_target target,
 366                                unsigned sample_count,
 367                                unsigned usage);
 368
 369 /* r600_blit.c */
 370 void r600_init_blit_functions(struct r600_context *rctx);
 371 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 372 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 373 void r600_flush_depth_textures(struct r600_context *rctx);
 374
 375 /* r600_buffer.c */
 376 bool r600_init_resource(struct r600_screen *rscreen,
 377                         struct r600_resource *res,
 378                         unsigned size, unsigned alignment,
 379                         unsigned bind, unsigned usage);
 380 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 381                                          const struct pipe_resource *templ);
 382 void r600_upload_index_buffer(struct r600_context *rctx,
 383                               struct pipe_index_buffer *ib, unsigned count);
 384
 385
 386 /* r600_pipe.c */
 387 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 388                     unsigned flags);
 389
 390 /* r600_query.c */
 391 void r600_init_query_functions(struct r600_context *rctx);
 392
 393 /* r600_resource.c */
 394 void r600_init_context_resource_functions(struct r600_context *r600);
 395
 396 /* radeonsi_shader.c */
 397 int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
 398 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
 399
 400 /* r600_texture.c */
 401 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 402 void r600_init_surface_functions(struct r600_context *r600);
 403 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 404                                         unsigned level, unsigned layer);
 405
 406 /* r600_translate.c */
 407 void r600_translate_index_buffer(struct r600_context *r600,
 408                                  struct pipe_index_buffer *ib,
 409                                  unsigned count);
 410
 411 /* r600_state_common.c */
 412 void r600_init_common_atoms(struct r600_context *rctx);
 413 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 414 void r600_texture_barrier(struct pipe_context *ctx);
 415 void r600_set_index_buffer(struct pipe_context *ctx,
 416                            const struct pipe_index_buffer *ib);
 417 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 418                              const struct pipe_vertex_buffer *buffers);
 419 void *si_create_vertex_elements(struct pipe_context *ctx,
 420                                 unsigned count,
 421                                 const struct pipe_vertex_element *elements);
 422 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 423 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 424 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 425 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 426 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 427 void r600_sampler_view_destroy(struct pipe_context *ctx,
 428                                struct pipe_sampler_view *state);
 429 void r600_delete_state(struct pipe_context *ctx, void *state);
 430 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 431 void *si_create_shader_state(struct pipe_context *ctx,
 432                              const struct pipe_shader_state *state);
 433 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 434 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 435 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 436 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 437 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 438                               struct pipe_constant_buffer *cb);
 439 struct pipe_stream_output_target *
 440 r600_create_so_target(struct pipe_context *ctx,
 441                       struct pipe_resource *buffer,
 442                       unsigned buffer_offset,
 443                       unsigned buffer_size);
 444 void r600_so_target_destroy(struct pipe_context *ctx,
 445                             struct pipe_stream_output_target *target);
 446 void r600_set_so_targets(struct pipe_context *ctx,
 447                          unsigned num_targets,
 448                          struct pipe_stream_output_target **targets,
 449                          unsigned append_bitmask);
 450 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 451                                const struct pipe_stencil_ref *state);
 452 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 453
 454 /*
 455  * common helpers
 456  */
 457 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 458 {
 459         return value * (1 << frac_bits);
 460 }
 461 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 462
 463 static INLINE unsigned si_map_swizzle(unsigned swizzle)
 464 {
 465         switch (swizzle) {
 466         case UTIL_FORMAT_SWIZZLE_Y:
 467                 return V_008F0C_SQ_SEL_Y;
 468         case UTIL_FORMAT_SWIZZLE_Z:
 469                 return V_008F0C_SQ_SEL_Z;
 470         case UTIL_FORMAT_SWIZZLE_W:
 471                 return V_008F0C_SQ_SEL_W;
 472         case UTIL_FORMAT_SWIZZLE_0:
 473                 return V_008F0C_SQ_SEL_0;
 474         case UTIL_FORMAT_SWIZZLE_1:
 475                 return V_008F0C_SQ_SEL_1;
 476         default: /* UTIL_FORMAT_SWIZZLE_X */
 477                 return V_008F0C_SQ_SEL_X;
 478         }
 479 }
 480
 481 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 482 {
 483         if (filter <= 1)   return 0;
 484         if (filter <= 2)   return 1;
 485         if (filter <= 4)   return 2;
 486         if (filter <= 8)   return 3;
 487          /* else */        return 4;
 488 }
 489
 490 /* 12.4 fixed-point */
 491 static INLINE unsigned r600_pack_float_12p4(float x)
 492 {
 493         return x <= 0    ? 0 :
 494                x >= 4096 ? 0xffff : x * 16;
 495 }
 496
 497 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 498 {
 499         struct r600_screen *rscreen = (struct r600_screen*)screen;
 500         struct r600_resource *rresource = (struct r600_resource*)resource;
 501
 502         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 503 }
 504
 505 #endif