src/gallium/drivers/radeonsi/radeonsi_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef RADEONSI_PIPE_H
  27 #define RADEONSI_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_format.h"
  35 #include "util/u_math.h"
  36 #include "util/u_slab.h"
  37 #include "r600.h"
  38 #include "radeonsi_public.h"
  39 #include "radeonsi_pm4.h"
  40 #include "si_state.h"
  41 #include "r600_resource.h"
  42 #include "sid.h"
  43
  44 #define R600_MAX_CONST_BUFFERS 1
  45 #define R600_MAX_CONST_BUFFER_SIZE 4096
  46
  47 #ifdef PIPE_ARCH_BIG_ENDIAN
  48 #define R600_BIG_ENDIAN 1
  49 #else
  50 #define R600_BIG_ENDIAN 0
  51 #endif
  52
  53 enum r600_atom_flags {
  54         /* When set, atoms are added at the beginning of the dirty list
  55          * instead of the end. */
  56         EMIT_EARLY = (1 << 0)
  57 };
  58
  59 /* This encapsulates a state or an operation which can emitted into the GPU
  60  * command stream. It's not limited to states only, it can be used for anything
  61  * that wants to write commands into the CS (e.g. cache flushes). */
  62 struct r600_atom {
  63         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  64
  65         unsigned                num_dw;
  66         enum r600_atom_flags    flags;
  67         bool                    dirty;
  68
  69         struct list_head        head;
  70 };
  71
  72 struct r600_atom_surface_sync {
  73         struct r600_atom atom;
  74         unsigned flush_flags; /* CP_COHER_CNTL */
  75 };
  76
  77 enum r600_pipe_state_id {
  78         R600_PIPE_STATE_CONFIG,
  79         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  80         R600_PIPE_STATE_PS_SHADER,
  81         R600_PIPE_STATE_VS_SHADER,
  82         R600_PIPE_STATE_CONSTANT,
  83         R600_PIPE_STATE_SAMPLER,
  84         R600_PIPE_STATE_RESOURCE,
  85         R600_PIPE_NSTATES
  86 };
  87
  88 struct r600_pipe_fences {
  89         struct r600_resource            *bo;
  90         unsigned                        *data;
  91         unsigned                        next_index;
  92         /* linked list of preallocated blocks */
  93         struct list_head                blocks;
  94         /* linked list of freed fences */
  95         struct list_head                pool;
  96         pipe_mutex                      mutex;
  97 };
  98
  99 struct r600_screen {
 100         struct pipe_screen              screen;
 101         struct radeon_winsys            *ws;
 102         unsigned                        family;
 103         enum chip_class                 chip_class;
 104         struct radeon_info              info;
 105         struct r600_tiling_info         tiling_info;
 106         struct util_slab_mempool        pool_buffers;
 107         struct r600_pipe_fences         fences;
 108 };
 109
 110 struct si_pipe_sampler_view {
 111         struct pipe_sampler_view        base;
 112         uint32_t                        state[8];
 113 };
 114
 115 struct si_pipe_sampler_state {
 116         uint32_t                        val[4];
 117 };
 118
 119 struct r600_vertex_element
 120 {
 121         unsigned                        count;
 122         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 123 };
 124
 125 struct r600_shader_io {
 126         unsigned                name;
 127         unsigned                gpr;
 128         unsigned                done;
 129         int                     sid;
 130         unsigned                param_offset;
 131         unsigned                interpolate;
 132         boolean                 centroid;
 133 };
 134
 135 struct r600_shader {
 136         unsigned                ninput;
 137         unsigned                noutput;
 138         struct r600_shader_io   input[32];
 139         struct r600_shader_io   output[32];
 140         boolean                 uses_kill;
 141         boolean                 fs_write_all;
 142         unsigned                nr_cbufs;
 143 };
 144
 145 struct si_pipe_shader {
 146         struct r600_shader              shader;
 147         struct r600_pipe_state          rstate;
 148         struct r600_resource            *bo;
 149         struct r600_vertex_element      vertex_elements;
 150         struct tgsi_token               *tokens;
 151         unsigned                        num_sgprs;
 152         unsigned                        num_vgprs;
 153         unsigned                        spi_ps_input_ena;
 154         unsigned        sprite_coord_enable;
 155         struct pipe_stream_output_info  so;
 156         unsigned                        so_strides[4];
 157 };
 158
 159 /* needed for blitter save */
 160 #define NUM_TEX_UNITS 16
 161
 162 struct r600_textures_info {
 163         struct r600_pipe_state          views_state;
 164         struct r600_pipe_state          samplers_state;
 165         struct si_pipe_sampler_view     *views[NUM_TEX_UNITS];
 166         struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
 167         unsigned                        n_views;
 168         unsigned                        n_samplers;
 169         bool                            samplers_dirty;
 170         bool                            is_array_sampler[NUM_TEX_UNITS];
 171 };
 172
 173 struct r600_fence {
 174         struct pipe_reference           reference;
 175         unsigned                        index; /* in the shared bo */
 176         struct r600_resource            *sleep_bo;
 177         struct list_head                head;
 178 };
 179
 180 #define FENCE_BLOCK_SIZE 16
 181
 182 struct r600_fence_block {
 183         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 184         struct list_head                head;
 185 };
 186
 187 #define R600_CONSTANT_ARRAY_SIZE 256
 188 #define R600_RESOURCE_ARRAY_SIZE 160
 189
 190 struct r600_context {
 191         struct pipe_context             context;
 192         struct blitter_context          *blitter;
 193         enum radeon_family              family;
 194         enum chip_class                 chip_class;
 195         void                            *custom_dsa_flush;
 196         struct r600_screen              *screen;
 197         struct radeon_winsys            *ws;
 198         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 199         struct r600_vertex_element      *vertex_elements;
 200         struct pipe_framebuffer_state   framebuffer;
 201         unsigned                        pa_sc_line_stipple;
 202         unsigned                        pa_su_sc_mode_cntl;
 203         unsigned                        pa_cl_clip_cntl;
 204         unsigned                        pa_cl_vs_out_cntl;
 205         /* for saving when using blitter */
 206         struct pipe_stencil_ref         stencil_ref;
 207         struct r600_pipe_state          config;
 208         struct si_pipe_shader   *ps_shader;
 209         struct si_pipe_shader   *vs_shader;
 210         struct r600_pipe_state          vs_const_buffer;
 211         struct r600_pipe_state          vs_user_data;
 212         struct r600_pipe_state          ps_const_buffer;
 213         struct r600_pipe_state          spi;
 214         struct pipe_query               *current_render_cond;
 215         unsigned                        current_render_cond_mode;
 216         struct pipe_query               *saved_render_cond;
 217         unsigned                        saved_render_cond_mode;
 218         /* shader information */
 219         unsigned                        sprite_coord_enable;
 220         boolean                         export_16bpc;
 221         unsigned                        alpha_ref;
 222         boolean                         alpha_ref_dirty;
 223         struct r600_textures_info       vs_samplers;
 224         struct r600_textures_info       ps_samplers;
 225         boolean                         shader_dirty;
 226
 227         struct u_upload_mgr             *uploader;
 228         struct util_slab_mempool        pool_transfers;
 229         boolean                         have_depth_texture, have_depth_fb;
 230
 231         unsigned default_ps_gprs, default_vs_gprs;
 232
 233         /* States based on r600_state. */
 234         struct list_head                dirty_states;
 235         struct r600_atom_surface_sync   atom_surface_sync;
 236         struct r600_atom                atom_r6xx_flush_and_inv;
 237
 238         /* Below are variables from the old r600_context.
 239          */
 240         struct radeon_winsys_cs *cs;
 241
 242         struct r600_range       *range;
 243         unsigned                nblocks;
 244         struct r600_block       **blocks;
 245         struct list_head        dirty;
 246         struct list_head        enable_list;
 247         unsigned                pm4_dirty_cdwords;
 248         unsigned                ctx_pm4_ndwords;
 249         unsigned                init_dwords;
 250
 251         /* The list of active queries. Only one query of each type can be active. */
 252         struct list_head        active_query_list;
 253         unsigned                num_cs_dw_queries_suspend;
 254         unsigned                num_cs_dw_streamout_end;
 255
 256         unsigned                backend_mask;
 257         unsigned                max_db; /* for OQ */
 258         unsigned                flags;
 259         boolean                 predicate_drawing;
 260
 261         unsigned                num_so_targets;
 262         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 263         boolean                 streamout_start;
 264         unsigned                streamout_append_bitmask;
 265         unsigned                *vs_so_stride_in_dw;
 266         unsigned                *vs_shader_so_strides;
 267
 268         /* Vertex and index buffers. */
 269         bool                    vertex_buffers_dirty;
 270         struct pipe_index_buffer index_buffer;
 271         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 272         unsigned                nr_vertex_buffers;
 273
 274         /* SI state handling */
 275         union si_state  queued;
 276         union si_state  emitted;
 277 };
 278
 279 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 280 {
 281         atom->emit(rctx, atom);
 282         atom->dirty = false;
 283         if (atom->head.next && atom->head.prev)
 284                 LIST_DELINIT(&atom->head);
 285 }
 286
 287 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 288 {
 289         if (!state->dirty) {
 290                 if (state->flags & EMIT_EARLY) {
 291                         LIST_ADD(&state->head, &rctx->dirty_states);
 292                 } else {
 293                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 294                 }
 295                 state->dirty = true;
 296         }
 297 }
 298
 299 /* evergreen_state.c */
 300 void cayman_init_state_functions(struct r600_context *rctx);
 301 void si_init_config(struct r600_context *rctx);
 302 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader);
 303 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader);
 304 void si_update_spi_map(struct r600_context *rctx);
 305 uint32_t si_translate_vertexformat(struct pipe_screen *screen,
 306                                    enum pipe_format format,
 307                                    const struct util_format_description *desc,
 308                                    int first_non_void);
 309 boolean si_is_format_supported(struct pipe_screen *screen,
 310                                enum pipe_format format,
 311                                enum pipe_texture_target target,
 312                                unsigned sample_count,
 313                                unsigned usage);
 314
 315 /* r600_blit.c */
 316 void r600_init_blit_functions(struct r600_context *rctx);
 317 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 318 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 319 void r600_flush_depth_textures(struct r600_context *rctx);
 320
 321 /* r600_buffer.c */
 322 bool r600_init_resource(struct r600_screen *rscreen,
 323                         struct r600_resource *res,
 324                         unsigned size, unsigned alignment,
 325                         unsigned bind, unsigned usage);
 326 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 327                                          const struct pipe_resource *templ);
 328 void r600_upload_index_buffer(struct r600_context *rctx,
 329                               struct pipe_index_buffer *ib, unsigned count);
 330
 331
 332 /* r600_pipe.c */
 333 void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 334                     unsigned flags);
 335
 336 /* r600_query.c */
 337 void r600_init_query_functions(struct r600_context *rctx);
 338
 339 /* r600_resource.c */
 340 void r600_init_context_resource_functions(struct r600_context *r600);
 341
 342 /* radeonsi_shader.c */
 343 int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
 344 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
 345
 346 /* r600_texture.c */
 347 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 348 void r600_init_surface_functions(struct r600_context *r600);
 349 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 350                                         unsigned level, unsigned layer);
 351
 352 /* r600_translate.c */
 353 void r600_translate_index_buffer(struct r600_context *r600,
 354                                  struct pipe_index_buffer *ib,
 355                                  unsigned count);
 356
 357 /* r600_state_common.c */
 358 void r600_init_common_atoms(struct r600_context *rctx);
 359 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 360 void r600_texture_barrier(struct pipe_context *ctx);
 361 void r600_set_index_buffer(struct pipe_context *ctx,
 362                            const struct pipe_index_buffer *ib);
 363 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 364                              const struct pipe_vertex_buffer *buffers);
 365 void *si_create_vertex_elements(struct pipe_context *ctx,
 366                                 unsigned count,
 367                                 const struct pipe_vertex_element *elements);
 368 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 369 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 370 void r600_sampler_view_destroy(struct pipe_context *ctx,
 371                                struct pipe_sampler_view *state);
 372 void r600_delete_state(struct pipe_context *ctx, void *state);
 373 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 374 void *si_create_shader_state(struct pipe_context *ctx,
 375                              const struct pipe_shader_state *state);
 376 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 377 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 378 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 379 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 380 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 381                               struct pipe_constant_buffer *cb);
 382 struct pipe_stream_output_target *
 383 r600_create_so_target(struct pipe_context *ctx,
 384                       struct pipe_resource *buffer,
 385                       unsigned buffer_offset,
 386                       unsigned buffer_size);
 387 void r600_so_target_destroy(struct pipe_context *ctx,
 388                             struct pipe_stream_output_target *target);
 389 void r600_set_so_targets(struct pipe_context *ctx,
 390                          unsigned num_targets,
 391                          struct pipe_stream_output_target **targets,
 392                          unsigned append_bitmask);
 393 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 394
 395 /*
 396  * common helpers
 397  */
 398 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 399 {
 400         return value * (1 << frac_bits);
 401 }
 402 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 403
 404 static INLINE unsigned si_map_swizzle(unsigned swizzle)
 405 {
 406         switch (swizzle) {
 407         case UTIL_FORMAT_SWIZZLE_Y:
 408                 return V_008F0C_SQ_SEL_Y;
 409         case UTIL_FORMAT_SWIZZLE_Z:
 410                 return V_008F0C_SQ_SEL_Z;
 411         case UTIL_FORMAT_SWIZZLE_W:
 412                 return V_008F0C_SQ_SEL_W;
 413         case UTIL_FORMAT_SWIZZLE_0:
 414                 return V_008F0C_SQ_SEL_0;
 415         case UTIL_FORMAT_SWIZZLE_1:
 416                 return V_008F0C_SQ_SEL_1;
 417         default: /* UTIL_FORMAT_SWIZZLE_X */
 418                 return V_008F0C_SQ_SEL_X;
 419         }
 420 }
 421
 422 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 423 {
 424         if (filter <= 1)   return 0;
 425         if (filter <= 2)   return 1;
 426         if (filter <= 4)   return 2;
 427         if (filter <= 8)   return 3;
 428          /* else */        return 4;
 429 }
 430
 431 /* 12.4 fixed-point */
 432 static INLINE unsigned r600_pack_float_12p4(float x)
 433 {
 434         return x <= 0    ? 0 :
 435                x >= 4096 ? 0xffff : x * 16;
 436 }
 437
 438 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 439 {
 440         struct r600_screen *rscreen = (struct r600_screen*)screen;
 441         struct r600_resource *rresource = (struct r600_resource*)resource;
 442
 443         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 444 }
 445
 446 #endif