src/gallium/drivers/radeonsi/radeonsi_pm4.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #ifndef RADEONSI_PM4_H
  28 #define RADEONSI_PM4_H
  29
  30 #include "../../winsys/radeon/drm/radeon_winsys.h"
  31
  32 #define SI_PM4_MAX_DW   128
  33 #define SI_PM4_MAX_BO   32
  34
  35 // forward defines
  36 struct r600_context;
  37
  38 struct si_pm4_state
  39 {
  40         /* PKT3_SET_*_REG handling */
  41         unsigned        last_opcode;
  42         unsigned        last_reg;
  43         unsigned        last_pm4;
  44
  45         /* flush flags for SURFACE_SYNC */
  46         uint32_t        cp_coher_cntl;
  47
  48         /* commands for the DE */
  49         unsigned        ndw;
  50         uint32_t        pm4[SI_PM4_MAX_DW];
  51
  52         /* BO's referenced by this state */
  53         unsigned                nbo;
  54         struct r600_resource    *bo[SI_PM4_MAX_BO];
  55         enum radeon_bo_usage    bo_usage[SI_PM4_MAX_BO];
  56 };
  57
  58 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
  59 void si_pm4_add_bo(struct si_pm4_state *state,
  60                    struct r600_resource *bo,
  61                    enum radeon_bo_usage usage);
  62
  63 void si_pm4_inval_shader_cache(struct si_pm4_state *state);
  64 void si_pm4_inval_texture_cache(struct si_pm4_state *state);
  65 void si_pm4_inval_vertex_cache(struct si_pm4_state *state);
  66 void si_pm4_inval_fb_cache(struct si_pm4_state *state, unsigned nr_cbufs);
  67 void si_pm4_inval_zsbuf_cache(struct si_pm4_state *state);
  68
  69 void si_pm4_free_state(struct r600_context *rctx,
  70                        struct si_pm4_state *state,
  71                        unsigned idx);
  72 unsigned si_pm4_dirty_dw(struct r600_context *rctx);
  73 void si_pm4_emit_dirty(struct r600_context *rctx);
  74 void si_pm4_reset_emitted(struct r600_context *rctx);
  75
  76 #endif