3 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_tgsi.h"
35 #include "radeon_llvm.h"
36 #include "radeon_llvm_emit.h"
37 #include "tgsi/tgsi_info.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_scan.h"
40 #include "tgsi/tgsi_dump.h"
42 #include "radeonsi_pipe.h"
43 #include "radeonsi_shader.h"
52 static ps_remap_inputs(
53 struct tgsi_llvm_context * tl_ctx,
62 struct list_head head;
70 struct si_shader_context
72 struct radeon_llvm_context radeon_bld
;
73 struct r600_context
*rctx
;
74 struct tgsi_parse_context parse
;
75 struct tgsi_token
* tokens
;
76 struct si_pipe_shader
*shader
;
77 unsigned type
; /* TGSI_PROCESSOR_* specifies the type of shader. */
78 unsigned ninput_emitted
;
79 /* struct list_head inputs; */
80 /* unsigned * input_mappings *//* From TGSI to SI hw */
81 /* struct tgsi_shader_info info;*/
84 static struct si_shader_context
* si_shader_context(
85 struct lp_build_tgsi_context
* bld_base
)
87 return (struct si_shader_context
*)bld_base
;
91 #define PERSPECTIVE_BASE 0
94 #define SAMPLE_OFFSET 0
95 #define CENTER_OFFSET 2
96 #define CENTROID_OFSET 4
98 #define USE_SGPR_MAX_SUFFIX_LEN 5
99 #define CONST_ADDR_SPACE 2
100 #define USER_SGPR_ADDR_SPACE 8
104 SGPR_CONST_PTR_V4I32
,
105 SGPR_CONST_PTR_V8I32
,
111 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
113 * @param offset The offset parameter specifies the number of
114 * elements to offset, not the number of bytes or dwords. An element is the
115 * the type pointed to by the base_ptr parameter (e.g. int is the element of
118 * When LLVM lowers the load instruction, it will convert the element offset
119 * into a dword offset automatically.
122 static LLVMValueRef
build_indexed_load(
123 struct gallivm_state
* gallivm
,
124 LLVMValueRef base_ptr
,
127 LLVMValueRef computed_ptr
= LLVMBuildGEP(
128 gallivm
->builder
, base_ptr
, &offset
, 1, "");
130 return LLVMBuildLoad(gallivm
->builder
, computed_ptr
, "");
134 * Load a value stored in one of the user SGPRs
136 * @param sgpr This is the sgpr to load the value from. If you need to load a
137 * value that is stored in consecutive SGPR registers (e.g. a 64-bit pointer),
138 * then you should pass the index of the first SGPR that holds the value. For
139 * example, if you want to load a pointer that is stored in SGPRs 2 and 3, then
140 * use pass 2 for the sgpr parameter.
142 * The value of the sgpr parameter must also be aligned to the width of the type
143 * being loaded, so that the sgpr parameter is divisible by the dword width of the
144 * type. For example, if the value being loaded is two dwords wide, then the sgpr
145 * parameter must be divisible by two.
147 static LLVMValueRef
use_sgpr(
148 struct gallivm_state
* gallivm
,
152 LLVMValueRef sgpr_index
;
153 LLVMTypeRef ret_type
;
156 sgpr_index
= lp_build_const_int32(gallivm
, sgpr
);
159 case SGPR_CONST_PTR_F32
:
160 assert(sgpr
% 2 == 0);
161 ret_type
= LLVMFloatTypeInContext(gallivm
->context
);
162 ret_type
= LLVMPointerType(ret_type
, CONST_ADDR_SPACE
);
166 ret_type
= LLVMInt32TypeInContext(gallivm
->context
);
170 assert(sgpr
% 2 == 0);
171 ret_type
= LLVMInt64TypeInContext(gallivm
->context
);
174 case SGPR_CONST_PTR_V4I32
:
175 assert(sgpr
% 2 == 0);
176 ret_type
= LLVMInt32TypeInContext(gallivm
->context
);
177 ret_type
= LLVMVectorType(ret_type
, 4);
178 ret_type
= LLVMPointerType(ret_type
, CONST_ADDR_SPACE
);
181 case SGPR_CONST_PTR_V8I32
:
182 assert(sgpr
% 2 == 0);
183 ret_type
= LLVMInt32TypeInContext(gallivm
->context
);
184 ret_type
= LLVMVectorType(ret_type
, 8);
185 ret_type
= LLVMPointerType(ret_type
, CONST_ADDR_SPACE
);
189 assert(!"Unsupported SGPR type in use_sgpr()");
193 ret_type
= LLVMPointerType(ret_type
, USER_SGPR_ADDR_SPACE
);
194 ptr
= LLVMBuildIntToPtr(gallivm
->builder
, sgpr_index
, ret_type
, "");
195 return LLVMBuildLoad(gallivm
->builder
, ptr
, "");
198 static void declare_input_vs(
199 struct si_shader_context
* si_shader_ctx
,
200 unsigned input_index
,
201 const struct tgsi_full_declaration
*decl
)
203 LLVMValueRef t_list_ptr
;
204 LLVMValueRef t_offset
;
206 LLVMValueRef attribute_offset
;
207 LLVMValueRef buffer_index_reg
;
208 LLVMValueRef args
[3];
209 LLVMTypeRef vec4_type
;
211 struct lp_build_context
* uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
212 struct lp_build_context
* base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
;
213 struct r600_context
*rctx
= si_shader_ctx
->rctx
;
214 //struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[input_index];
217 /* Load the T list */
218 /* XXX: Communicate with the rest of the driver about which SGPR the T#
219 * list pointer is going to be stored in. Hard code to SGPR[6:7] for
221 t_list_ptr
= use_sgpr(base
->gallivm
, SGPR_CONST_PTR_V4I32
, 6);
223 t_offset
= lp_build_const_int32(base
->gallivm
, input_index
);
225 t_list
= build_indexed_load(base
->gallivm
, t_list_ptr
, t_offset
);
227 /* Build the attribute offset */
228 attribute_offset
= lp_build_const_int32(base
->gallivm
, 0);
230 /* Load the buffer index is always, which is always stored in VGPR0
231 * for Vertex Shaders */
232 buffer_index_reg
= build_intrinsic(base
->gallivm
->builder
,
233 "llvm.SI.vs.load.buffer.index", uint
->elem_type
, NULL
, 0,
234 LLVMReadNoneAttribute
);
236 vec4_type
= LLVMVectorType(base
->elem_type
, 4);
238 args
[1] = attribute_offset
;
239 args
[2] = buffer_index_reg
;
240 input
= lp_build_intrinsic(base
->gallivm
->builder
,
241 "llvm.SI.vs.load.input", vec4_type
, args
, 3);
243 /* Break up the vec4 into individual components */
244 for (chan
= 0; chan
< 4; chan
++) {
245 LLVMValueRef llvm_chan
= lp_build_const_int32(base
->gallivm
, chan
);
246 /* XXX: Use a helper function for this. There is one in
248 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, chan
)] =
249 LLVMBuildExtractElement(base
->gallivm
->builder
,
250 input
, llvm_chan
, "");
254 static void declare_input_fs(
255 struct si_shader_context
* si_shader_ctx
,
256 unsigned input_index
,
257 const struct tgsi_full_declaration
*decl
)
259 const char * intr_name
;
261 struct lp_build_context
* base
=
262 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
;
263 struct gallivm_state
* gallivm
= base
->gallivm
;
266 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
267 * quad begins a new primitive. Bit 0 always needs
269 * [32:16] ParamOffset
272 /* XXX: This register number must be identical to the S_00B02C_USER_SGPR
273 * register field value
275 LLVMValueRef params
= use_sgpr(base
->gallivm
, SGPR_I32
, 6);
278 /* XXX: Is this the input_index? */
279 LLVMValueRef attr_number
= lp_build_const_int32(gallivm
, input_index
);
281 /* XXX: Handle all possible interpolation modes */
282 switch (decl
->Interp
.Interpolate
) {
283 case TGSI_INTERPOLATE_COLOR
:
284 /* XXX: Flat shading hangs the GPU */
285 if (si_shader_ctx
->rctx
->queued
.named
.rasterizer
&&
286 si_shader_ctx
->rctx
->queued
.named
.rasterizer
->flatshade
) {
288 intr_name
= "llvm.SI.fs.interp.constant";
290 intr_name
= "llvm.SI.fs.interp.linear.center";
293 if (decl
->Interp
.Centroid
)
294 intr_name
= "llvm.SI.fs.interp.persp.centroid";
296 intr_name
= "llvm.SI.fs.interp.persp.center";
299 case TGSI_INTERPOLATE_CONSTANT
:
300 /* XXX: Flat shading hangs the GPU */
302 intr_name
= "llvm.SI.fs.interp.constant";
305 case TGSI_INTERPOLATE_LINEAR
:
306 if (decl
->Interp
.Centroid
)
307 intr_name
= "llvm.SI.fs.interp.linear.centroid";
309 intr_name
= "llvm.SI.fs.interp.linear.center";
311 case TGSI_INTERPOLATE_PERSPECTIVE
:
312 if (decl
->Interp
.Centroid
)
313 intr_name
= "llvm.SI.fs.interp.persp.centroid";
315 intr_name
= "llvm.SI.fs.interp.persp.center";
318 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
322 if (!si_shader_ctx
->ninput_emitted
++) {
323 /* Enable whole quad mode */
324 lp_build_intrinsic(gallivm
->builder
,
326 LLVMVoidTypeInContext(gallivm
->context
),
330 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
331 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
332 LLVMValueRef args
[3];
333 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
334 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
335 LLVMTypeRef input_type
= LLVMFloatTypeInContext(gallivm
->context
);
337 args
[1] = attr_number
;
339 si_shader_ctx
->radeon_bld
.inputs
[soa_index
] =
340 build_intrinsic(base
->gallivm
->builder
, intr_name
,
341 input_type
, args
, 3, LLVMReadOnlyAttribute
);
345 static void declare_input(
346 struct radeon_llvm_context
* radeon_bld
,
347 unsigned input_index
,
348 const struct tgsi_full_declaration
*decl
)
350 struct si_shader_context
* si_shader_ctx
=
351 si_shader_context(&radeon_bld
->soa
.bld_base
);
352 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
353 declare_input_vs(si_shader_ctx
, input_index
, decl
);
354 } else if (si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
355 declare_input_fs(si_shader_ctx
, input_index
, decl
);
357 fprintf(stderr
, "Warning: Unsupported shader type,\n");
361 static LLVMValueRef
fetch_constant(
362 struct lp_build_tgsi_context
* bld_base
,
363 const struct tgsi_full_src_register
*reg
,
364 enum tgsi_opcode_type type
,
367 struct lp_build_context
* base
= &bld_base
->base
;
370 LLVMValueRef const_ptr
;
374 /* currently not supported */
375 if (reg
->Register
.Indirect
) {
377 load
= lp_build_const_int32(base
->gallivm
, 0);
378 return bitcast(bld_base
, type
, load
);
381 /* XXX: Assume the pointer to the constant buffer is being stored in
383 const_ptr
= use_sgpr(base
->gallivm
, SGPR_CONST_PTR_F32
, 0);
385 /* XXX: This assumes that the constant buffer is not packed, so
386 * CONST[0].x will have an offset of 0 and CONST[1].x will have an
388 idx
= (reg
->Register
.Index
* 4) + swizzle
;
390 /* index loads above 255 are currently not supported */
395 offset
= lp_build_const_int32(base
->gallivm
, idx
);
397 load
= build_indexed_load(base
->gallivm
, const_ptr
, offset
);
398 return bitcast(bld_base
, type
, load
);
401 /* Initialize arguments for the shader export intrinsic */
402 static void si_llvm_init_export_args(struct lp_build_tgsi_context
*bld_base
,
403 struct tgsi_full_declaration
*d
,
408 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
409 struct lp_build_context
*uint
=
410 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
411 struct lp_build_context
*base
= &bld_base
->base
;
412 unsigned compressed
= 0;
415 if (si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
416 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
418 if (cbuf
>= 0 && cbuf
< 8) {
419 struct r600_context
*rctx
= si_shader_ctx
->rctx
;
420 compressed
= (rctx
->export_16bpc
>> cbuf
) & 0x1;
425 /* Pixel shader needs to pack output values before export */
426 for (chan
= 0; chan
< 2; chan
++ ) {
427 LLVMValueRef
*out_ptr
=
428 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
];
429 args
[0] = LLVMBuildLoad(base
->gallivm
->builder
,
430 out_ptr
[2 * chan
], "");
431 args
[1] = LLVMBuildLoad(base
->gallivm
->builder
,
432 out_ptr
[2 * chan
+ 1], "");
434 build_intrinsic(base
->gallivm
->builder
,
436 LLVMInt32TypeInContext(base
->gallivm
->context
),
438 LLVMReadNoneAttribute
);
439 args
[chan
+ 7] = args
[chan
+ 5];
445 for (chan
= 0; chan
< 4; chan
++ ) {
446 LLVMValueRef out_ptr
=
447 si_shader_ctx
->radeon_bld
.soa
.outputs
[index
][chan
];
448 /* +5 because the first output value will be
449 * the 6th argument to the intrinsic. */
450 args
[chan
+ 5] = LLVMBuildLoad(base
->gallivm
->builder
,
454 /* Clear COMPR flag */
455 args
[4] = uint
->zero
;
458 /* XXX: This controls which components of the output
459 * registers actually get exported. (e.g bit 0 means export
460 * X component, bit 1 means export Y component, etc.) I'm
461 * hard coding this to 0xf for now. In the future, we might
462 * want to do something else. */
463 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
465 /* Specify whether the EXEC mask represents the valid mask */
466 args
[1] = uint
->zero
;
468 /* Specify whether this is the last export */
469 args
[2] = uint
->zero
;
471 /* Specify the target we are exporting */
472 args
[3] = lp_build_const_int32(base
->gallivm
, target
);
474 /* XXX: We probably need to keep track of the output
475 * values, so we know what we are passing to the next
479 static void si_llvm_emit_prologue(struct lp_build_tgsi_context
*bld_base
)
481 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
482 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
483 lp_build_intrinsic_unary(gallivm
->builder
,
484 "llvm.AMDGPU.shader.type",
485 LLVMVoidTypeInContext(gallivm
->context
),
486 lp_build_const_int32(gallivm
, si_shader_ctx
->type
));
490 /* XXX: This is partially implemented for VS only at this point. It is not complete */
491 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context
* bld_base
)
493 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
494 struct si_shader
* shader
= &si_shader_ctx
->shader
->shader
;
495 struct lp_build_context
* base
= &bld_base
->base
;
496 struct lp_build_context
* uint
=
497 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
498 struct tgsi_parse_context
*parse
= &si_shader_ctx
->parse
;
499 LLVMValueRef last_args
[9] = { 0 };
500 unsigned color_count
= 0;
501 unsigned param_count
= 0;
503 while (!tgsi_parse_end_of_tokens(parse
)) {
504 struct tgsi_full_declaration
*d
=
505 &parse
->FullToken
.FullDeclaration
;
506 LLVMValueRef args
[9];
511 tgsi_parse_token(parse
);
512 if (parse
->FullToken
.Token
.Type
!= TGSI_TOKEN_TYPE_DECLARATION
)
515 switch (d
->Declaration
.File
) {
516 case TGSI_FILE_INPUT
:
517 i
= shader
->ninput
++;
518 shader
->input
[i
].name
= d
->Semantic
.Name
;
519 shader
->input
[i
].sid
= d
->Semantic
.Index
;
520 shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
521 shader
->input
[i
].centroid
= d
->Interp
.Centroid
;
524 case TGSI_FILE_OUTPUT
:
525 i
= shader
->noutput
++;
526 shader
->output
[i
].name
= d
->Semantic
.Name
;
527 shader
->output
[i
].sid
= d
->Semantic
.Index
;
528 shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
535 for (index
= d
->Range
.First
; index
<= d
->Range
.Last
; index
++) {
536 /* Select the correct target */
537 switch(d
->Semantic
.Name
) {
538 case TGSI_SEMANTIC_PSIZE
:
539 case TGSI_SEMANTIC_POSITION
:
540 target
= V_008DFC_SQ_EXP_POS
;
542 case TGSI_SEMANTIC_COLOR
:
543 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
544 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
545 shader
->output
[i
].param_offset
= param_count
;
548 target
= V_008DFC_SQ_EXP_MRT
+ color_count
;
552 case TGSI_SEMANTIC_FOG
:
553 case TGSI_SEMANTIC_GENERIC
:
554 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
555 shader
->output
[i
].param_offset
= param_count
;
561 "Warning: SI unhandled output type:%d\n",
565 si_llvm_init_export_args(bld_base
, d
, index
, target
, args
);
567 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
?
568 (d
->Semantic
.Name
== TGSI_SEMANTIC_POSITION
) :
569 (d
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
)) {
571 lp_build_intrinsic(base
->gallivm
->builder
,
573 LLVMVoidTypeInContext(base
->gallivm
->context
),
577 memcpy(last_args
, args
, sizeof(args
));
579 lp_build_intrinsic(base
->gallivm
->builder
,
581 LLVMVoidTypeInContext(base
->gallivm
->context
),
589 assert(si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
);
591 /* Specify which components to enable */
592 last_args
[0] = lp_build_const_int32(base
->gallivm
, 0x0);
594 /* Specify the target we are exporting */
595 last_args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRT
);
597 /* Set COMPR flag to zero to export data as 32-bit */
598 last_args
[4] = uint
->zero
;
601 last_args
[5]= uint
->zero
;
602 last_args
[6]= uint
->zero
;
603 last_args
[7]= uint
->zero
;
604 last_args
[8]= uint
->zero
;
607 /* Specify whether the EXEC mask represents the valid mask */
608 last_args
[1] = lp_build_const_int32(base
->gallivm
,
609 si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
);
611 /* Specify that this is the last export */
612 last_args
[2] = lp_build_const_int32(base
->gallivm
, 1);
614 lp_build_intrinsic(base
->gallivm
->builder
,
616 LLVMVoidTypeInContext(base
->gallivm
->context
),
619 /* XXX: Look up what this function does */
620 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
623 static void tex_fetch_args(
624 struct lp_build_tgsi_context
* bld_base
,
625 struct lp_build_emit_data
* emit_data
)
627 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
632 /* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
633 emit_data
->args
[0] = lp_build_const_int32(bld_base
->base
.gallivm
, 0xf);
636 /* XXX: Not all sample instructions need 4 address arguments. */
637 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
640 LLVMValueRef coords
[4];
642 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
643 src_w
= lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
645 for (chan
= 0; chan
< 3; chan
++ ) {
646 LLVMValueRef arg
= lp_build_emit_fetch(bld_base
,
647 emit_data
->inst
, 0, chan
);
648 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
652 coords
[3] = bld_base
->base
.one
;
653 emit_data
->args
[1] = lp_build_gather_values(bld_base
->base
.gallivm
,
656 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
, emit_data
->inst
,
660 ptr
= use_sgpr(bld_base
->base
.gallivm
, SGPR_CONST_PTR_V8I32
, 4);
661 offset
= lp_build_const_int32(bld_base
->base
.gallivm
,
662 emit_data
->inst
->Src
[1].Register
.Index
);
663 emit_data
->args
[2] = build_indexed_load(bld_base
->base
.gallivm
,
667 ptr
= use_sgpr(bld_base
->base
.gallivm
, SGPR_CONST_PTR_V4I32
, 2);
668 offset
= lp_build_const_int32(bld_base
->base
.gallivm
,
669 emit_data
->inst
->Src
[1].Register
.Index
);
670 emit_data
->args
[3] = build_indexed_load(bld_base
->base
.gallivm
,
674 /* XXX: We might want to pass this information to the shader at some. */
675 /* emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm,
676 emit_data->inst->Texture.Texture);
679 emit_data
->arg_count
= 4;
680 /* XXX: To optimize, we could use a float or v2f32, if the last bits of
681 * the writemask are clear */
682 emit_data
->dst_type
= LLVMVectorType(
683 LLVMFloatTypeInContext(bld_base
->base
.gallivm
->context
),
687 static const struct lp_build_tgsi_action tex_action
= {
688 .fetch_args
= tex_fetch_args
,
689 .emit
= lp_build_tgsi_intrinsic
,
690 .intr_name
= "llvm.SI.sample"
694 int si_pipe_shader_create(
695 struct pipe_context
*ctx
,
696 struct si_pipe_shader
*shader
)
698 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
699 struct si_pipe_shader_selector
*sel
= shader
->selector
;
700 struct si_shader_context si_shader_ctx
;
701 struct tgsi_shader_info shader_info
;
702 struct lp_build_tgsi_context
* bld_base
;
704 unsigned char * inst_bytes
;
705 unsigned inst_byte_count
;
710 dump
= debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE
);
712 memset(&si_shader_ctx
, 0, sizeof(si_shader_ctx
));
713 radeon_llvm_context_init(&si_shader_ctx
.radeon_bld
);
714 bld_base
= &si_shader_ctx
.radeon_bld
.soa
.bld_base
;
716 tgsi_scan_shader(sel
->tokens
, &shader_info
);
717 bld_base
->info
= &shader_info
;
718 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
719 bld_base
->emit_prologue
= si_llvm_emit_prologue
;
720 bld_base
->emit_epilogue
= si_llvm_emit_epilogue
;
722 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
723 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
725 si_shader_ctx
.radeon_bld
.load_input
= declare_input
;
726 si_shader_ctx
.tokens
= sel
->tokens
;
727 tgsi_parse_init(&si_shader_ctx
.parse
, si_shader_ctx
.tokens
);
728 si_shader_ctx
.shader
= shader
;
729 si_shader_ctx
.type
= si_shader_ctx
.parse
.FullHeader
.Processor
.Processor
;
730 si_shader_ctx
.rctx
= rctx
;
732 shader
->shader
.nr_cbufs
= rctx
->framebuffer
.nr_cbufs
;
734 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
735 * conversion fails. */
737 tgsi_dump(sel
->tokens
, 0);
740 if (!lp_build_tgsi_llvm(bld_base
, sel
->tokens
)) {
741 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
745 radeon_llvm_finalize_module(&si_shader_ctx
.radeon_bld
);
747 mod
= bld_base
->base
.gallivm
->module
;
751 radeon_llvm_compile(mod
, &inst_bytes
, &inst_byte_count
, "SI", dump
);
753 fprintf(stderr
, "SI CODE:\n");
754 for (i
= 0; i
< inst_byte_count
; i
+=4 ) {
755 fprintf(stderr
, "%02x%02x%02x%02x\n", inst_bytes
[i
+ 3],
756 inst_bytes
[i
+ 2], inst_bytes
[i
+ 1],
761 shader
->num_sgprs
= util_le32_to_cpu(*(uint32_t*)inst_bytes
);
762 shader
->num_vgprs
= util_le32_to_cpu(*(uint32_t*)(inst_bytes
+ 4));
763 shader
->spi_ps_input_ena
= util_le32_to_cpu(*(uint32_t*)(inst_bytes
+ 8));
765 radeon_llvm_dispose(&si_shader_ctx
.radeon_bld
);
766 tgsi_parse_free(&si_shader_ctx
.parse
);
768 /* copy new shader */
769 si_resource_reference(&shader
->bo
, NULL
);
770 shader
->bo
= si_resource_create_custom(ctx
->screen
, PIPE_USAGE_IMMUTABLE
,
771 inst_byte_count
- 12);
772 if (shader
->bo
== NULL
) {
776 ptr
= (uint32_t*)rctx
->ws
->buffer_map(shader
->bo
->cs_buf
, rctx
->cs
, PIPE_TRANSFER_WRITE
);
777 if (0 /*R600_BIG_ENDIAN*/) {
778 for (i
= 0; i
< (inst_byte_count
-12)/4; ++i
) {
779 ptr
[i
] = util_bswap32(*(uint32_t*)(inst_bytes
+12 + i
*4));
782 memcpy(ptr
, inst_bytes
+ 12, inst_byte_count
- 12);
784 rctx
->ws
->buffer_unmap(shader
->bo
->cs_buf
);
791 void si_pipe_shader_destroy(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
793 si_resource_reference(&shader
->bo
, NULL
);