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radeonsi: Write htile state to hardware.
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "gallivm/lp_bld_arit.h"
37 #include "gallivm/lp_bld_flow.h"
38 #include "radeon_llvm.h"
39 #include "radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_scan.h"
44 #include "tgsi/tgsi_util.h"
45 #include "tgsi/tgsi_dump.h"
46
47 #include "radeonsi_pipe.h"
48 #include "radeonsi_shader.h"
49 #include "si_state.h"
50 #include "sid.h"
51
52 #include <assert.h>
53 #include <errno.h>
54 #include <stdio.h>
55
56 struct si_shader_context
57 {
58 struct radeon_llvm_context radeon_bld;
59 struct tgsi_parse_context parse;
60 struct tgsi_token * tokens;
61 struct si_pipe_shader *shader;
62 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
63 int param_streamout_config;
64 int param_streamout_write_index;
65 int param_streamout_offset[4];
66 int param_vertex_id;
67 int param_instance_id;
68 LLVMValueRef const_md;
69 LLVMValueRef const_resource[NUM_CONST_BUFFERS];
70 #if HAVE_LLVM >= 0x0304
71 LLVMValueRef ddxy_lds;
72 #endif
73 LLVMValueRef *constants[NUM_CONST_BUFFERS];
74 LLVMValueRef *resources;
75 LLVMValueRef *samplers;
76 LLVMValueRef so_buffers[4];
77 };
78
79 static struct si_shader_context * si_shader_context(
80 struct lp_build_tgsi_context * bld_base)
81 {
82 return (struct si_shader_context *)bld_base;
83 }
84
85
86 #define PERSPECTIVE_BASE 0
87 #define LINEAR_BASE 9
88
89 #define SAMPLE_OFFSET 0
90 #define CENTER_OFFSET 2
91 #define CENTROID_OFSET 4
92
93 #define USE_SGPR_MAX_SUFFIX_LEN 5
94 #define CONST_ADDR_SPACE 2
95 #define LOCAL_ADDR_SPACE 3
96 #define USER_SGPR_ADDR_SPACE 8
97
98 /**
99 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
100 *
101 * @param offset The offset parameter specifies the number of
102 * elements to offset, not the number of bytes or dwords. An element is the
103 * the type pointed to by the base_ptr parameter (e.g. int is the element of
104 * an int* pointer)
105 *
106 * When LLVM lowers the load instruction, it will convert the element offset
107 * into a dword offset automatically.
108 *
109 */
110 static LLVMValueRef build_indexed_load(
111 struct si_shader_context * si_shader_ctx,
112 LLVMValueRef base_ptr,
113 LLVMValueRef offset)
114 {
115 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
116
117 LLVMValueRef indices[2] = {
118 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
119 offset
120 };
121 LLVMValueRef computed_ptr = LLVMBuildGEP(
122 base->gallivm->builder, base_ptr, indices, 2, "");
123
124 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
125 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
126 return result;
127 }
128
129 static LLVMValueRef get_instance_index_for_fetch(
130 struct radeon_llvm_context * radeon_bld,
131 unsigned divisor)
132 {
133 struct si_shader_context *si_shader_ctx =
134 si_shader_context(&radeon_bld->soa.bld_base);
135 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
136
137 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
138 si_shader_ctx->param_instance_id);
139 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
140 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
141
142 if (divisor > 1)
143 result = LLVMBuildUDiv(gallivm->builder, result,
144 lp_build_const_int32(gallivm, divisor), "");
145
146 return result;
147 }
148
149 static void declare_input_vs(
150 struct si_shader_context * si_shader_ctx,
151 unsigned input_index,
152 const struct tgsi_full_declaration *decl)
153 {
154 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
155 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
156
157 unsigned chan;
158
159 LLVMValueRef t_list_ptr;
160 LLVMValueRef t_offset;
161 LLVMValueRef t_list;
162 LLVMValueRef attribute_offset;
163 LLVMValueRef buffer_index;
164 LLVMValueRef args[3];
165 LLVMTypeRef vec4_type;
166 LLVMValueRef input;
167
168 /* Load the T list */
169 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
170
171 t_offset = lp_build_const_int32(base->gallivm, input_index);
172
173 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
174
175 /* Build the attribute offset */
176 attribute_offset = lp_build_const_int32(base->gallivm, 0);
177
178 if (divisor) {
179 /* Build index from instance ID, start instance and divisor */
180 si_shader_ctx->shader->shader.uses_instanceid = true;
181 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
182 } else {
183 /* Load the buffer index, which is always stored in VGPR0
184 * for Vertex Shaders */
185 buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
186 si_shader_ctx->param_vertex_id);
187 }
188
189 vec4_type = LLVMVectorType(base->elem_type, 4);
190 args[0] = t_list;
191 args[1] = attribute_offset;
192 args[2] = buffer_index;
193 input = build_intrinsic(base->gallivm->builder,
194 "llvm.SI.vs.load.input", vec4_type, args, 3,
195 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
196
197 /* Break up the vec4 into individual components */
198 for (chan = 0; chan < 4; chan++) {
199 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
200 /* XXX: Use a helper function for this. There is one in
201 * tgsi_llvm.c. */
202 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
203 LLVMBuildExtractElement(base->gallivm->builder,
204 input, llvm_chan, "");
205 }
206 }
207
208 static void declare_input_fs(
209 struct si_shader_context * si_shader_ctx,
210 unsigned input_index,
211 const struct tgsi_full_declaration *decl)
212 {
213 struct si_shader *shader = &si_shader_ctx->shader->shader;
214 struct lp_build_context * base =
215 &si_shader_ctx->radeon_bld.soa.bld_base.base;
216 struct lp_build_context *uint =
217 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
218 struct gallivm_state * gallivm = base->gallivm;
219 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
220 LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
221
222 LLVMValueRef interp_param;
223 const char * intr_name;
224
225 /* This value is:
226 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
227 * quad begins a new primitive. Bit 0 always needs
228 * to be unset)
229 * [32:16] ParamOffset
230 *
231 */
232 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
233 LLVMValueRef attr_number;
234
235 unsigned chan;
236
237 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
238 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
239 unsigned soa_index =
240 radeon_llvm_reg_index_soa(input_index, chan);
241 si_shader_ctx->radeon_bld.inputs[soa_index] =
242 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
243
244 if (chan == 3)
245 /* RCP for fragcoord.w */
246 si_shader_ctx->radeon_bld.inputs[soa_index] =
247 LLVMBuildFDiv(gallivm->builder,
248 lp_build_const_float(gallivm, 1.0f),
249 si_shader_ctx->radeon_bld.inputs[soa_index],
250 "");
251 }
252 return;
253 }
254
255 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
256 LLVMValueRef face, is_face_positive;
257
258 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
259
260 is_face_positive = LLVMBuildFCmp(gallivm->builder,
261 LLVMRealUGT, face,
262 lp_build_const_float(gallivm, 0.0f),
263 "");
264
265 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
266 LLVMBuildSelect(gallivm->builder,
267 is_face_positive,
268 lp_build_const_float(gallivm, 1.0f),
269 lp_build_const_float(gallivm, 0.0f),
270 "");
271 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
272 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
273 lp_build_const_float(gallivm, 0.0f);
274 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
275 lp_build_const_float(gallivm, 1.0f);
276
277 return;
278 }
279
280 shader->input[input_index].param_offset = shader->ninterp++;
281 attr_number = lp_build_const_int32(gallivm,
282 shader->input[input_index].param_offset);
283
284 switch (decl->Interp.Interpolate) {
285 case TGSI_INTERPOLATE_COLOR:
286 if (si_shader_ctx->shader->key.ps.flatshade) {
287 interp_param = 0;
288 } else {
289 if (decl->Interp.Centroid)
290 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
291 else
292 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
293 }
294 break;
295 case TGSI_INTERPOLATE_CONSTANT:
296 interp_param = 0;
297 break;
298 case TGSI_INTERPOLATE_LINEAR:
299 if (decl->Interp.Centroid)
300 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
301 else
302 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
303 break;
304 case TGSI_INTERPOLATE_PERSPECTIVE:
305 if (decl->Interp.Centroid)
306 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
307 else
308 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
309 break;
310 default:
311 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
312 return;
313 }
314
315 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
316
317 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
318 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
319 si_shader_ctx->shader->key.ps.color_two_side) {
320 LLVMValueRef args[4];
321 LLVMValueRef face, is_face_positive;
322 LLVMValueRef back_attr_number =
323 lp_build_const_int32(gallivm,
324 shader->input[input_index].param_offset + 1);
325
326 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
327
328 is_face_positive = LLVMBuildFCmp(gallivm->builder,
329 LLVMRealUGT, face,
330 lp_build_const_float(gallivm, 0.0f),
331 "");
332
333 args[2] = params;
334 args[3] = interp_param;
335 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
336 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
337 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
338 LLVMValueRef front, back;
339
340 args[0] = llvm_chan;
341 args[1] = attr_number;
342 front = build_intrinsic(base->gallivm->builder, intr_name,
343 input_type, args, args[3] ? 4 : 3,
344 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
345
346 args[1] = back_attr_number;
347 back = build_intrinsic(base->gallivm->builder, intr_name,
348 input_type, args, args[3] ? 4 : 3,
349 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
350
351 si_shader_ctx->radeon_bld.inputs[soa_index] =
352 LLVMBuildSelect(gallivm->builder,
353 is_face_positive,
354 front,
355 back,
356 "");
357 }
358
359 shader->ninterp++;
360 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
361 LLVMValueRef args[4];
362
363 args[0] = uint->zero;
364 args[1] = attr_number;
365 args[2] = params;
366 args[3] = interp_param;
367 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
368 build_intrinsic(base->gallivm->builder, intr_name,
369 input_type, args, args[3] ? 4 : 3,
370 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
371 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
372 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
373 lp_build_const_float(gallivm, 0.0f);
374 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
375 lp_build_const_float(gallivm, 1.0f);
376 } else {
377 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
378 LLVMValueRef args[4];
379 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
380 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
381 args[0] = llvm_chan;
382 args[1] = attr_number;
383 args[2] = params;
384 args[3] = interp_param;
385 si_shader_ctx->radeon_bld.inputs[soa_index] =
386 build_intrinsic(base->gallivm->builder, intr_name,
387 input_type, args, args[3] ? 4 : 3,
388 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
389 }
390 }
391 }
392
393 static void declare_input(
394 struct radeon_llvm_context * radeon_bld,
395 unsigned input_index,
396 const struct tgsi_full_declaration *decl)
397 {
398 struct si_shader_context * si_shader_ctx =
399 si_shader_context(&radeon_bld->soa.bld_base);
400 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
401 declare_input_vs(si_shader_ctx, input_index, decl);
402 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
403 declare_input_fs(si_shader_ctx, input_index, decl);
404 } else {
405 fprintf(stderr, "Warning: Unsupported shader type,\n");
406 }
407 }
408
409 static void declare_system_value(
410 struct radeon_llvm_context * radeon_bld,
411 unsigned index,
412 const struct tgsi_full_declaration *decl)
413 {
414 struct si_shader_context *si_shader_ctx =
415 si_shader_context(&radeon_bld->soa.bld_base);
416 LLVMValueRef value = 0;
417
418 switch (decl->Semantic.Name) {
419 case TGSI_SEMANTIC_INSTANCEID:
420 value = LLVMGetParam(radeon_bld->main_fn,
421 si_shader_ctx->param_instance_id);
422 break;
423
424 case TGSI_SEMANTIC_VERTEXID:
425 value = LLVMGetParam(radeon_bld->main_fn,
426 si_shader_ctx->param_vertex_id);
427 break;
428
429 default:
430 assert(!"unknown system value");
431 return;
432 }
433
434 radeon_bld->system_values[index] = value;
435 }
436
437 static LLVMValueRef fetch_constant(
438 struct lp_build_tgsi_context * bld_base,
439 const struct tgsi_full_src_register *reg,
440 enum tgsi_opcode_type type,
441 unsigned swizzle)
442 {
443 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
444 struct lp_build_context * base = &bld_base->base;
445 const struct tgsi_ind_register *ireg = &reg->Indirect;
446 unsigned buf, idx;
447
448 LLVMValueRef args[2];
449 LLVMValueRef addr;
450 LLVMValueRef result;
451
452 if (swizzle == LP_CHAN_ALL) {
453 unsigned chan;
454 LLVMValueRef values[4];
455 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
456 values[chan] = fetch_constant(bld_base, reg, type, chan);
457
458 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
459 }
460
461 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
462 idx = reg->Register.Index * 4 + swizzle;
463
464 if (!reg->Register.Indirect)
465 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
466
467 args[0] = si_shader_ctx->const_resource[buf];
468 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
469 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
470 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
471 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
472 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
473
474 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
475 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
476
477 return bitcast(bld_base, type, result);
478 }
479
480 /* Initialize arguments for the shader export intrinsic */
481 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
482 struct tgsi_full_declaration *d,
483 unsigned index,
484 unsigned target,
485 LLVMValueRef *args)
486 {
487 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
488 struct lp_build_context *uint =
489 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
490 struct lp_build_context *base = &bld_base->base;
491 unsigned compressed = 0;
492 unsigned chan;
493
494 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
495 int cbuf = target - V_008DFC_SQ_EXP_MRT;
496
497 if (cbuf >= 0 && cbuf < 8) {
498 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
499
500 if (compressed)
501 si_shader_ctx->shader->spi_shader_col_format |=
502 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
503 else
504 si_shader_ctx->shader->spi_shader_col_format |=
505 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
506
507 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
508 }
509 }
510
511 if (compressed) {
512 /* Pixel shader needs to pack output values before export */
513 for (chan = 0; chan < 2; chan++ ) {
514 LLVMValueRef *out_ptr =
515 si_shader_ctx->radeon_bld.soa.outputs[index];
516 args[0] = LLVMBuildLoad(base->gallivm->builder,
517 out_ptr[2 * chan], "");
518 args[1] = LLVMBuildLoad(base->gallivm->builder,
519 out_ptr[2 * chan + 1], "");
520 args[chan + 5] =
521 build_intrinsic(base->gallivm->builder,
522 "llvm.SI.packf16",
523 LLVMInt32TypeInContext(base->gallivm->context),
524 args, 2,
525 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
526 args[chan + 7] = args[chan + 5] =
527 LLVMBuildBitCast(base->gallivm->builder,
528 args[chan + 5],
529 LLVMFloatTypeInContext(base->gallivm->context),
530 "");
531 }
532
533 /* Set COMPR flag */
534 args[4] = uint->one;
535 } else {
536 for (chan = 0; chan < 4; chan++ ) {
537 LLVMValueRef out_ptr =
538 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
539 /* +5 because the first output value will be
540 * the 6th argument to the intrinsic. */
541 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
542 out_ptr, "");
543 }
544
545 /* Clear COMPR flag */
546 args[4] = uint->zero;
547 }
548
549 /* XXX: This controls which components of the output
550 * registers actually get exported. (e.g bit 0 means export
551 * X component, bit 1 means export Y component, etc.) I'm
552 * hard coding this to 0xf for now. In the future, we might
553 * want to do something else. */
554 args[0] = lp_build_const_int32(base->gallivm, 0xf);
555
556 /* Specify whether the EXEC mask represents the valid mask */
557 args[1] = uint->zero;
558
559 /* Specify whether this is the last export */
560 args[2] = uint->zero;
561
562 /* Specify the target we are exporting */
563 args[3] = lp_build_const_int32(base->gallivm, target);
564
565 /* XXX: We probably need to keep track of the output
566 * values, so we know what we are passing to the next
567 * stage. */
568 }
569
570 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
571 unsigned index)
572 {
573 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
574 struct gallivm_state *gallivm = bld_base->base.gallivm;
575
576 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
577 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
578 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
579 SI_PARAM_ALPHA_REF);
580
581 LLVMValueRef alpha_pass =
582 lp_build_cmp(&bld_base->base,
583 si_shader_ctx->shader->key.ps.alpha_func,
584 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
585 alpha_ref);
586 LLVMValueRef arg =
587 lp_build_select(&bld_base->base,
588 alpha_pass,
589 lp_build_const_float(gallivm, 1.0f),
590 lp_build_const_float(gallivm, -1.0f));
591
592 build_intrinsic(gallivm->builder,
593 "llvm.AMDGPU.kill",
594 LLVMVoidTypeInContext(gallivm->context),
595 &arg, 1, 0);
596 } else {
597 build_intrinsic(gallivm->builder,
598 "llvm.AMDGPU.kilp",
599 LLVMVoidTypeInContext(gallivm->context),
600 NULL, 0, 0);
601 }
602 }
603
604 static void si_alpha_to_one(struct lp_build_tgsi_context *bld_base,
605 unsigned index)
606 {
607 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
608
609 /* set alpha to one */
610 LLVMBuildStore(bld_base->base.gallivm->builder,
611 bld_base->base.one,
612 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
613 }
614
615 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
616 LLVMValueRef (*pos)[9], unsigned index)
617 {
618 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
619 struct si_pipe_shader *shader = si_shader_ctx->shader;
620 struct lp_build_context *base = &bld_base->base;
621 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
622 unsigned reg_index;
623 unsigned chan;
624 unsigned const_chan;
625 LLVMValueRef out_elts[4];
626 LLVMValueRef base_elt;
627 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
628 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, NUM_PIPE_CONST_BUFFERS);
629 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
630
631 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
632 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][chan];
633 out_elts[chan] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
634 }
635
636 for (reg_index = 0; reg_index < 2; reg_index ++) {
637 LLVMValueRef *args = pos[2 + reg_index];
638
639 if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
640 continue;
641
642 shader->shader.clip_dist_write |= 0xf << (4 * reg_index);
643
644 args[5] =
645 args[6] =
646 args[7] =
647 args[8] = lp_build_const_float(base->gallivm, 0.0f);
648
649 /* Compute dot products of position and user clip plane vectors */
650 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
651 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
652 args[0] = const_resource;
653 args[1] = lp_build_const_int32(base->gallivm,
654 ((reg_index * 4 + chan) * 4 +
655 const_chan) * 4);
656 base_elt = build_intrinsic(base->gallivm->builder,
657 "llvm.SI.load.const",
658 base->elem_type,
659 args, 2,
660 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
661 args[5 + chan] =
662 lp_build_add(base, args[5 + chan],
663 lp_build_mul(base, base_elt,
664 out_elts[const_chan]));
665 }
666 }
667
668 args[0] = lp_build_const_int32(base->gallivm, 0xf);
669 args[1] = uint->zero;
670 args[2] = uint->zero;
671 args[3] = lp_build_const_int32(base->gallivm,
672 V_008DFC_SQ_EXP_POS + 2 + reg_index);
673 args[4] = uint->zero;
674 }
675 }
676
677 static void si_dump_streamout(struct pipe_stream_output_info *so)
678 {
679 unsigned i;
680
681 if (so->num_outputs)
682 fprintf(stderr, "STREAMOUT\n");
683
684 for (i = 0; i < so->num_outputs; i++) {
685 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
686 so->output[i].start_component;
687 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
688 i, so->output[i].output_buffer,
689 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
690 so->output[i].register_index,
691 mask & 1 ? "x" : "",
692 mask & 2 ? "y" : "",
693 mask & 4 ? "z" : "",
694 mask & 8 ? "w" : "");
695 }
696 }
697
698 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
699 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
700 * or v4i32 (num_channels=3,4). */
701 static void build_tbuffer_store(struct si_shader_context *shader,
702 LLVMValueRef rsrc,
703 LLVMValueRef vdata,
704 unsigned num_channels,
705 LLVMValueRef vaddr,
706 LLVMValueRef soffset,
707 unsigned inst_offset,
708 unsigned dfmt,
709 unsigned nfmt,
710 unsigned offen,
711 unsigned idxen,
712 unsigned glc,
713 unsigned slc,
714 unsigned tfe)
715 {
716 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
717 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
718 LLVMValueRef args[] = {
719 rsrc,
720 vdata,
721 LLVMConstInt(i32, num_channels, 0),
722 vaddr,
723 soffset,
724 LLVMConstInt(i32, inst_offset, 0),
725 LLVMConstInt(i32, dfmt, 0),
726 LLVMConstInt(i32, nfmt, 0),
727 LLVMConstInt(i32, offen, 0),
728 LLVMConstInt(i32, idxen, 0),
729 LLVMConstInt(i32, glc, 0),
730 LLVMConstInt(i32, slc, 0),
731 LLVMConstInt(i32, tfe, 0)
732 };
733
734 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
735 unsigned func = CLAMP(num_channels, 1, 3) - 1;
736 const char *types[] = {"i32", "v2i32", "v4i32"};
737 char name[256];
738 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
739
740 lp_build_intrinsic(gallivm->builder, name,
741 LLVMVoidTypeInContext(gallivm->context),
742 args, Elements(args));
743 }
744
745 static void build_streamout_store(struct si_shader_context *shader,
746 LLVMValueRef rsrc,
747 LLVMValueRef vdata,
748 unsigned num_channels,
749 LLVMValueRef vaddr,
750 LLVMValueRef soffset,
751 unsigned inst_offset)
752 {
753 static unsigned dfmt[] = {
754 V_008F0C_BUF_DATA_FORMAT_32,
755 V_008F0C_BUF_DATA_FORMAT_32_32,
756 V_008F0C_BUF_DATA_FORMAT_32_32_32,
757 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
758 };
759 assert(num_channels >= 1 && num_channels <= 4);
760
761 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
762 inst_offset, dfmt[num_channels-1],
763 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
764 }
765
766 /* On SI, the vertex shader is responsible for writing streamout data
767 * to buffers. */
768 static void si_llvm_emit_streamout(struct si_shader_context *shader)
769 {
770 struct pipe_stream_output_info *so = &shader->shader->selector->so;
771 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
772 LLVMBuilderRef builder = gallivm->builder;
773 int i, j;
774 struct lp_build_if_state if_ctx;
775
776 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
777
778 LLVMValueRef so_param =
779 LLVMGetParam(shader->radeon_bld.main_fn,
780 shader->param_streamout_config);
781
782 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
783 LLVMValueRef so_vtx_count =
784 LLVMBuildAnd(builder,
785 LLVMBuildLShr(builder, so_param,
786 LLVMConstInt(i32, 16, 0), ""),
787 LLVMConstInt(i32, 127, 0), "");
788
789 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
790 NULL, 0, LLVMReadNoneAttribute);
791
792 /* can_emit = tid < so_vtx_count; */
793 LLVMValueRef can_emit =
794 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
795
796 /* Emit the streamout code conditionally. This actually avoids
797 * out-of-bounds buffer access. The hw tells us via the SGPR
798 * (so_vtx_count) which threads are allowed to emit streamout data. */
799 lp_build_if(&if_ctx, gallivm, can_emit);
800 {
801 /* The buffer offset is computed as follows:
802 * ByteOffset = streamout_offset[buffer_id]*4 +
803 * (streamout_write_index + thread_id)*stride[buffer_id] +
804 * attrib_offset
805 */
806
807 LLVMValueRef so_write_index =
808 LLVMGetParam(shader->radeon_bld.main_fn,
809 shader->param_streamout_write_index);
810
811 /* Compute (streamout_write_index + thread_id). */
812 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
813
814 /* Compute the write offset for each enabled buffer. */
815 LLVMValueRef so_write_offset[4] = {};
816 for (i = 0; i < 4; i++) {
817 if (!so->stride[i])
818 continue;
819
820 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
821 shader->param_streamout_offset[i]);
822 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
823
824 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
825 LLVMConstInt(i32, so->stride[i]*4, 0), "");
826 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
827 }
828
829 LLVMValueRef (*outputs)[TGSI_NUM_CHANNELS] = shader->radeon_bld.soa.outputs;
830
831 /* Write streamout data. */
832 for (i = 0; i < so->num_outputs; i++) {
833 unsigned buf_idx = so->output[i].output_buffer;
834 unsigned reg = so->output[i].register_index;
835 unsigned start = so->output[i].start_component;
836 unsigned num_comps = so->output[i].num_components;
837 LLVMValueRef out[4];
838
839 assert(num_comps && num_comps <= 4);
840 if (!num_comps || num_comps > 4)
841 continue;
842
843 /* Load the output as int. */
844 for (j = 0; j < num_comps; j++) {
845 out[j] = LLVMBuildLoad(builder, outputs[reg][start+j], "");
846 out[j] = LLVMBuildBitCast(builder, out[j], i32, "");
847 }
848
849 /* Pack the output. */
850 LLVMValueRef vdata = NULL;
851
852 switch (num_comps) {
853 case 1: /* as i32 */
854 vdata = out[0];
855 break;
856 case 2: /* as v2i32 */
857 case 3: /* as v4i32 (aligned to 4) */
858 case 4: /* as v4i32 */
859 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
860 for (j = 0; j < num_comps; j++) {
861 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
862 LLVMConstInt(i32, j, 0), "");
863 }
864 break;
865 }
866
867 build_streamout_store(shader, shader->so_buffers[buf_idx],
868 vdata, num_comps,
869 so_write_offset[buf_idx],
870 LLVMConstInt(i32, 0, 0),
871 so->output[i].dst_offset*4);
872 }
873 }
874 lp_build_endif(&if_ctx);
875 }
876
877
878 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
879 {
880 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
881 struct si_shader * shader = &si_shader_ctx->shader->shader;
882 struct lp_build_context * base = &bld_base->base;
883 struct lp_build_context * uint =
884 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
885 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
886 LLVMValueRef args[9];
887 LLVMValueRef last_args[9] = { 0 };
888 LLVMValueRef pos_args[4][9] = { { 0 } };
889 unsigned semantic_name;
890 unsigned param_count = 0;
891 int depth_index = -1, stencil_index = -1, psize_index = -1, edgeflag_index = -1;
892 int layer_index = -1;
893 int i;
894
895 if (si_shader_ctx->shader->selector->so.num_outputs) {
896 si_llvm_emit_streamout(si_shader_ctx);
897 }
898
899 while (!tgsi_parse_end_of_tokens(parse)) {
900 struct tgsi_full_declaration *d =
901 &parse->FullToken.FullDeclaration;
902 unsigned target;
903 unsigned index;
904
905 tgsi_parse_token(parse);
906
907 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
908 parse->FullToken.FullProperty.Property.PropertyName ==
909 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
910 shader->fs_write_all = TRUE;
911
912 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
913 continue;
914
915 switch (d->Declaration.File) {
916 case TGSI_FILE_INPUT:
917 i = shader->ninput++;
918 assert(i < Elements(shader->input));
919 shader->input[i].name = d->Semantic.Name;
920 shader->input[i].sid = d->Semantic.Index;
921 shader->input[i].interpolate = d->Interp.Interpolate;
922 shader->input[i].centroid = d->Interp.Centroid;
923 continue;
924
925 case TGSI_FILE_OUTPUT:
926 i = shader->noutput++;
927 assert(i < Elements(shader->output));
928 shader->output[i].name = d->Semantic.Name;
929 shader->output[i].sid = d->Semantic.Index;
930 shader->output[i].interpolate = d->Interp.Interpolate;
931 break;
932
933 default:
934 continue;
935 }
936
937 semantic_name = d->Semantic.Name;
938 handle_semantic:
939 for (index = d->Range.First; index <= d->Range.Last; index++) {
940 /* Select the correct target */
941 switch(semantic_name) {
942 case TGSI_SEMANTIC_PSIZE:
943 shader->vs_out_misc_write = true;
944 shader->vs_out_point_size = true;
945 psize_index = index;
946 continue;
947 case TGSI_SEMANTIC_EDGEFLAG:
948 shader->vs_out_misc_write = true;
949 shader->vs_out_edgeflag = true;
950 edgeflag_index = index;
951 continue;
952 case TGSI_SEMANTIC_LAYER:
953 shader->vs_out_misc_write = true;
954 shader->vs_out_layer = true;
955 layer_index = index;
956 continue;
957 case TGSI_SEMANTIC_POSITION:
958 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
959 target = V_008DFC_SQ_EXP_POS;
960 break;
961 } else {
962 depth_index = index;
963 continue;
964 }
965 case TGSI_SEMANTIC_STENCIL:
966 stencil_index = index;
967 continue;
968 case TGSI_SEMANTIC_COLOR:
969 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
970 case TGSI_SEMANTIC_BCOLOR:
971 target = V_008DFC_SQ_EXP_PARAM + param_count;
972 shader->output[i].param_offset = param_count;
973 param_count++;
974 } else {
975 target = V_008DFC_SQ_EXP_MRT + shader->output[i].sid;
976 if (si_shader_ctx->shader->key.ps.alpha_to_one) {
977 si_alpha_to_one(bld_base, index);
978 }
979 if (shader->output[i].sid == 0 &&
980 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
981 si_alpha_test(bld_base, index);
982 }
983 break;
984 case TGSI_SEMANTIC_CLIPDIST:
985 if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
986 (1 << d->Semantic.Index)))
987 continue;
988 shader->clip_dist_write |=
989 d->Declaration.UsageMask << (d->Semantic.Index << 2);
990 target = V_008DFC_SQ_EXP_POS + 2 + d->Semantic.Index;
991 break;
992 case TGSI_SEMANTIC_CLIPVERTEX:
993 si_llvm_emit_clipvertex(bld_base, pos_args, index);
994 continue;
995 case TGSI_SEMANTIC_FOG:
996 case TGSI_SEMANTIC_GENERIC:
997 target = V_008DFC_SQ_EXP_PARAM + param_count;
998 shader->output[i].param_offset = param_count;
999 param_count++;
1000 break;
1001 default:
1002 target = 0;
1003 fprintf(stderr,
1004 "Warning: SI unhandled output type:%d\n",
1005 semantic_name);
1006 }
1007
1008 si_llvm_init_export_args(bld_base, d, index, target, args);
1009
1010 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
1011 target >= V_008DFC_SQ_EXP_POS &&
1012 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1013 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1014 args, sizeof(args));
1015 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT &&
1016 semantic_name == TGSI_SEMANTIC_COLOR) {
1017 if (last_args[0]) {
1018 lp_build_intrinsic(base->gallivm->builder,
1019 "llvm.SI.export",
1020 LLVMVoidTypeInContext(base->gallivm->context),
1021 last_args, 9);
1022 }
1023
1024 memcpy(last_args, args, sizeof(args));
1025 } else {
1026 lp_build_intrinsic(base->gallivm->builder,
1027 "llvm.SI.export",
1028 LLVMVoidTypeInContext(base->gallivm->context),
1029 args, 9);
1030 }
1031 }
1032
1033 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1034 semantic_name = TGSI_SEMANTIC_GENERIC;
1035 goto handle_semantic;
1036 }
1037 }
1038
1039 if (depth_index >= 0 || stencil_index >= 0) {
1040 LLVMValueRef out_ptr;
1041 unsigned mask = 0;
1042
1043 /* Specify the target we are exporting */
1044 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1045
1046 if (depth_index >= 0) {
1047 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1048 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1049 mask |= 0x1;
1050
1051 if (stencil_index < 0) {
1052 args[6] =
1053 args[7] =
1054 args[8] = args[5];
1055 }
1056 }
1057
1058 if (stencil_index >= 0) {
1059 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1060 args[7] =
1061 args[8] =
1062 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1063 /* Only setting the stencil component bit (0x2) here
1064 * breaks some stencil piglit tests
1065 */
1066 mask |= 0x3;
1067
1068 if (depth_index < 0)
1069 args[5] = args[6];
1070 }
1071
1072 /* Specify which components to enable */
1073 args[0] = lp_build_const_int32(base->gallivm, mask);
1074
1075 args[1] =
1076 args[2] =
1077 args[4] = uint->zero;
1078
1079 if (last_args[0])
1080 lp_build_intrinsic(base->gallivm->builder,
1081 "llvm.SI.export",
1082 LLVMVoidTypeInContext(base->gallivm->context),
1083 args, 9);
1084 else
1085 memcpy(last_args, args, sizeof(args));
1086 }
1087
1088 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
1089 unsigned pos_idx = 0;
1090
1091 /* We need to add the position output manually if it's missing. */
1092 if (!pos_args[0][0]) {
1093 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1094 pos_args[0][1] = uint->zero; /* EXEC mask */
1095 pos_args[0][2] = uint->zero; /* last export? */
1096 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1097 pos_args[0][4] = uint->zero; /* COMPR flag */
1098 pos_args[0][5] = base->zero; /* X */
1099 pos_args[0][6] = base->zero; /* Y */
1100 pos_args[0][7] = base->zero; /* Z */
1101 pos_args[0][8] = base->one; /* W */
1102 }
1103
1104 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1105 if (shader->vs_out_misc_write) {
1106 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1107 shader->vs_out_point_size |
1108 (shader->vs_out_edgeflag << 1) |
1109 (shader->vs_out_layer << 2));
1110 pos_args[1][1] = uint->zero; /* EXEC mask */
1111 pos_args[1][2] = uint->zero; /* last export? */
1112 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1113 pos_args[1][4] = uint->zero; /* COMPR flag */
1114 pos_args[1][5] = base->zero; /* X */
1115 pos_args[1][6] = base->zero; /* Y */
1116 pos_args[1][7] = base->zero; /* Z */
1117 pos_args[1][8] = base->zero; /* W */
1118
1119 if (shader->vs_out_point_size) {
1120 pos_args[1][5] = LLVMBuildLoad(base->gallivm->builder,
1121 si_shader_ctx->radeon_bld.soa.outputs[psize_index][0], "");
1122 }
1123
1124 if (shader->vs_out_edgeflag) {
1125 LLVMValueRef output = LLVMBuildLoad(base->gallivm->builder,
1126 si_shader_ctx->radeon_bld.soa.outputs[edgeflag_index][0], "");
1127
1128 /* The output is a float, but the hw expects an integer
1129 * with the first bit containing the edge flag. */
1130 output = LLVMBuildFPToUI(base->gallivm->builder, output,
1131 bld_base->uint_bld.elem_type, "");
1132
1133 output = lp_build_min(&bld_base->int_bld, output, bld_base->int_bld.one);
1134
1135 /* The LLVM intrinsic expects a float. */
1136 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder, output,
1137 base->elem_type, "");
1138 }
1139
1140 if (shader->vs_out_layer) {
1141 pos_args[1][7] = LLVMBuildLoad(base->gallivm->builder,
1142 si_shader_ctx->radeon_bld.soa.outputs[layer_index][0], "");
1143 }
1144 }
1145
1146 for (i = 0; i < 4; i++)
1147 if (pos_args[i][0])
1148 shader->nr_pos_exports++;
1149
1150 for (i = 0; i < 4; i++) {
1151 if (!pos_args[i][0])
1152 continue;
1153
1154 /* Specify the target we are exporting */
1155 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1156
1157 if (pos_idx == shader->nr_pos_exports)
1158 /* Specify that this is the last export */
1159 pos_args[i][2] = uint->one;
1160
1161 lp_build_intrinsic(base->gallivm->builder,
1162 "llvm.SI.export",
1163 LLVMVoidTypeInContext(base->gallivm->context),
1164 pos_args[i], 9);
1165 }
1166 } else {
1167 if (!last_args[0]) {
1168 /* Specify which components to enable */
1169 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1170
1171 /* Specify the target we are exporting */
1172 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1173
1174 /* Set COMPR flag to zero to export data as 32-bit */
1175 last_args[4] = uint->zero;
1176
1177 /* dummy bits */
1178 last_args[5]= uint->zero;
1179 last_args[6]= uint->zero;
1180 last_args[7]= uint->zero;
1181 last_args[8]= uint->zero;
1182
1183 si_shader_ctx->shader->spi_shader_col_format |=
1184 V_028714_SPI_SHADER_32_ABGR;
1185 si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
1186 }
1187
1188 /* Specify whether the EXEC mask represents the valid mask */
1189 last_args[1] = uint->one;
1190
1191 if (shader->fs_write_all && shader->nr_cbufs > 1) {
1192 int i;
1193
1194 /* Specify that this is not yet the last export */
1195 last_args[2] = lp_build_const_int32(base->gallivm, 0);
1196
1197 for (i = 1; i < shader->nr_cbufs; i++) {
1198 /* Specify the target we are exporting */
1199 last_args[3] = lp_build_const_int32(base->gallivm,
1200 V_008DFC_SQ_EXP_MRT + i);
1201
1202 lp_build_intrinsic(base->gallivm->builder,
1203 "llvm.SI.export",
1204 LLVMVoidTypeInContext(base->gallivm->context),
1205 last_args, 9);
1206
1207 si_shader_ctx->shader->spi_shader_col_format |=
1208 si_shader_ctx->shader->spi_shader_col_format << 4;
1209 si_shader_ctx->shader->cb_shader_mask |=
1210 si_shader_ctx->shader->cb_shader_mask << 4;
1211 }
1212
1213 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1214 }
1215
1216 /* Specify that this is the last export */
1217 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1218
1219 lp_build_intrinsic(base->gallivm->builder,
1220 "llvm.SI.export",
1221 LLVMVoidTypeInContext(base->gallivm->context),
1222 last_args, 9);
1223 }
1224 }
1225
1226 static const struct lp_build_tgsi_action txf_action;
1227
1228 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1229 struct lp_build_tgsi_context * bld_base,
1230 struct lp_build_emit_data * emit_data);
1231
1232 static void tex_fetch_args(
1233 struct lp_build_tgsi_context * bld_base,
1234 struct lp_build_emit_data * emit_data)
1235 {
1236 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1237 struct gallivm_state *gallivm = bld_base->base.gallivm;
1238 const struct tgsi_full_instruction * inst = emit_data->inst;
1239 unsigned opcode = inst->Instruction.Opcode;
1240 unsigned target = inst->Texture.Texture;
1241 LLVMValueRef coords[4];
1242 LLVMValueRef address[16];
1243 int ref_pos;
1244 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1245 unsigned count = 0;
1246 unsigned chan;
1247 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1248 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1249
1250 if (target == TGSI_TEXTURE_BUFFER) {
1251 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1252 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1253 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1254 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1255
1256 /* Truncate v32i8 to v16i8. */
1257 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1258 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1259 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1260 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1261
1262 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1263 emit_data->args[0] = res;
1264 emit_data->args[1] = bld_base->uint_bld.zero;
1265 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1266 emit_data->arg_count = 3;
1267 return;
1268 }
1269
1270 /* Fetch and project texture coordinates */
1271 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1272 for (chan = 0; chan < 3; chan++ ) {
1273 coords[chan] = lp_build_emit_fetch(bld_base,
1274 emit_data->inst, 0,
1275 chan);
1276 if (opcode == TGSI_OPCODE_TXP)
1277 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1278 TGSI_OPCODE_DIV,
1279 coords[chan],
1280 coords[3]);
1281 }
1282
1283 if (opcode == TGSI_OPCODE_TXP)
1284 coords[3] = bld_base->base.one;
1285
1286 /* Pack LOD bias value */
1287 if (opcode == TGSI_OPCODE_TXB)
1288 address[count++] = coords[3];
1289
1290 if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
1291 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1292
1293 /* Pack depth comparison value */
1294 switch (target) {
1295 case TGSI_TEXTURE_SHADOW1D:
1296 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1297 case TGSI_TEXTURE_SHADOW2D:
1298 case TGSI_TEXTURE_SHADOWRECT:
1299 case TGSI_TEXTURE_SHADOWCUBE:
1300 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1301 assert(ref_pos >= 0);
1302 address[count++] = coords[ref_pos];
1303 break;
1304 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1305 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1306 }
1307
1308 /* Pack user derivatives */
1309 if (opcode == TGSI_OPCODE_TXD) {
1310 for (chan = 0; chan < 2; chan++) {
1311 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, chan);
1312 if (num_coords > 1)
1313 address[count++] = lp_build_emit_fetch(bld_base, inst, 2, chan);
1314 }
1315 }
1316
1317 /* Pack texture coordinates */
1318 address[count++] = coords[0];
1319 if (num_coords > 1)
1320 address[count++] = coords[1];
1321 if (num_coords > 2)
1322 address[count++] = coords[2];
1323
1324 /* Pack LOD or sample index */
1325 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1326 address[count++] = coords[3];
1327
1328 if (count > 16) {
1329 assert(!"Cannot handle more than 16 texture address parameters");
1330 count = 16;
1331 }
1332
1333 for (chan = 0; chan < count; chan++ ) {
1334 address[chan] = LLVMBuildBitCast(gallivm->builder,
1335 address[chan],
1336 LLVMInt32TypeInContext(gallivm->context),
1337 "");
1338 }
1339
1340 /* Adjust the sample index according to FMASK.
1341 *
1342 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1343 * which is the identity mapping. Each nibble says which physical sample
1344 * should be fetched to get that sample.
1345 *
1346 * For example, 0x11111100 means there are only 2 samples stored and
1347 * the second sample covers 3/4 of the pixel. When reading samples 0
1348 * and 1, return physical sample 0 (determined by the first two 0s
1349 * in FMASK), otherwise return physical sample 1.
1350 *
1351 * The sample index should be adjusted as follows:
1352 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1353 */
1354 if (target == TGSI_TEXTURE_2D_MSAA ||
1355 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1356 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1357 struct lp_build_emit_data txf_emit_data = *emit_data;
1358 LLVMValueRef txf_address[4];
1359 unsigned txf_count = count;
1360
1361 memcpy(txf_address, address, sizeof(txf_address));
1362
1363 if (target == TGSI_TEXTURE_2D_MSAA) {
1364 txf_address[2] = bld_base->uint_bld.zero;
1365 }
1366 txf_address[3] = bld_base->uint_bld.zero;
1367
1368 /* Pad to a power-of-two size. */
1369 while (txf_count < util_next_power_of_two(txf_count))
1370 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1371
1372 /* Read FMASK using TXF. */
1373 txf_emit_data.chan = 0;
1374 txf_emit_data.dst_type = LLVMVectorType(
1375 LLVMInt32TypeInContext(bld_base->base.gallivm->context), 4);
1376 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1377 txf_emit_data.args[1] = si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index];
1378 txf_emit_data.args[2] = lp_build_const_int32(bld_base->base.gallivm,
1379 target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY);
1380 txf_emit_data.arg_count = 3;
1381
1382 build_tex_intrinsic(&txf_action, bld_base, &txf_emit_data);
1383
1384 /* Initialize some constants. */
1385 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1386 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1387
1388 /* Apply the formula. */
1389 LLVMValueRef fmask =
1390 LLVMBuildExtractElement(gallivm->builder,
1391 txf_emit_data.output[0],
1392 uint_bld->zero, "");
1393
1394 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1395
1396 LLVMValueRef sample_index4 =
1397 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1398
1399 LLVMValueRef shifted_fmask =
1400 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1401
1402 LLVMValueRef final_sample =
1403 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1404
1405 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1406 * resource descriptor is 0 (invalid),
1407 */
1408 LLVMValueRef fmask_desc =
1409 LLVMBuildBitCast(gallivm->builder,
1410 si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index],
1411 LLVMVectorType(uint_bld->elem_type, 8), "");
1412
1413 LLVMValueRef fmask_word1 =
1414 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1415 uint_bld->one, "");
1416
1417 LLVMValueRef word1_is_nonzero =
1418 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1419 fmask_word1, uint_bld->zero, "");
1420
1421 /* Replace the MSAA sample index. */
1422 address[sample_chan] =
1423 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1424 final_sample, address[sample_chan], "");
1425 }
1426
1427 /* Resource */
1428 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1429
1430 if (opcode == TGSI_OPCODE_TXF) {
1431 /* add tex offsets */
1432 if (inst->Texture.NumOffsets) {
1433 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1434 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1435 const struct tgsi_texture_offset * off = inst->TexOffsets;
1436
1437 assert(inst->Texture.NumOffsets == 1);
1438
1439 switch (target) {
1440 case TGSI_TEXTURE_3D:
1441 address[2] = lp_build_add(uint_bld, address[2],
1442 bld->immediates[off->Index][off->SwizzleZ]);
1443 /* fall through */
1444 case TGSI_TEXTURE_2D:
1445 case TGSI_TEXTURE_SHADOW2D:
1446 case TGSI_TEXTURE_RECT:
1447 case TGSI_TEXTURE_SHADOWRECT:
1448 case TGSI_TEXTURE_2D_ARRAY:
1449 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1450 address[1] =
1451 lp_build_add(uint_bld, address[1],
1452 bld->immediates[off->Index][off->SwizzleY]);
1453 /* fall through */
1454 case TGSI_TEXTURE_1D:
1455 case TGSI_TEXTURE_SHADOW1D:
1456 case TGSI_TEXTURE_1D_ARRAY:
1457 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1458 address[0] =
1459 lp_build_add(uint_bld, address[0],
1460 bld->immediates[off->Index][off->SwizzleX]);
1461 break;
1462 /* texture offsets do not apply to other texture targets */
1463 }
1464 }
1465
1466 emit_data->dst_type = LLVMVectorType(
1467 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1468 4);
1469
1470 emit_data->arg_count = 3;
1471 } else {
1472 /* Sampler */
1473 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1474
1475 emit_data->dst_type = LLVMVectorType(
1476 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
1477 4);
1478
1479 emit_data->arg_count = 4;
1480 }
1481
1482 /* Dimensions */
1483 emit_data->args[emit_data->arg_count - 1] =
1484 lp_build_const_int32(bld_base->base.gallivm, target);
1485
1486 /* Pad to power of two vector */
1487 while (count < util_next_power_of_two(count))
1488 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1489
1490 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1491 }
1492
1493 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1494 struct lp_build_tgsi_context * bld_base,
1495 struct lp_build_emit_data * emit_data)
1496 {
1497 struct lp_build_context * base = &bld_base->base;
1498 char intr_name[127];
1499
1500 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1501 emit_data->output[emit_data->chan] = build_intrinsic(
1502 base->gallivm->builder,
1503 "llvm.SI.vs.load.input", emit_data->dst_type,
1504 emit_data->args, emit_data->arg_count,
1505 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1506 return;
1507 }
1508
1509 sprintf(intr_name, "%sv%ui32", action->intr_name,
1510 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1511
1512 emit_data->output[emit_data->chan] = build_intrinsic(
1513 base->gallivm->builder, intr_name, emit_data->dst_type,
1514 emit_data->args, emit_data->arg_count,
1515 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1516 }
1517
1518 static void txq_fetch_args(
1519 struct lp_build_tgsi_context * bld_base,
1520 struct lp_build_emit_data * emit_data)
1521 {
1522 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1523 const struct tgsi_full_instruction *inst = emit_data->inst;
1524 struct gallivm_state *gallivm = bld_base->base.gallivm;
1525
1526 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1527 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1528 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
1529
1530 /* Read the size from the buffer descriptor directly. */
1531 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
1532 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
1533 size = LLVMBuildExtractElement(gallivm->builder, size,
1534 lp_build_const_int32(gallivm, 2), "");
1535 emit_data->args[0] = size;
1536 return;
1537 }
1538
1539 /* Mip level */
1540 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1541
1542 /* Resource */
1543 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
1544
1545 /* Dimensions */
1546 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
1547 inst->Texture.Texture);
1548
1549 emit_data->arg_count = 3;
1550
1551 emit_data->dst_type = LLVMVectorType(
1552 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1553 4);
1554 }
1555
1556 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
1557 struct lp_build_tgsi_context * bld_base,
1558 struct lp_build_emit_data * emit_data)
1559 {
1560 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1561 /* Just return the buffer size. */
1562 emit_data->output[emit_data->chan] = emit_data->args[0];
1563 return;
1564 }
1565
1566 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
1567 }
1568
1569 #if HAVE_LLVM >= 0x0304
1570
1571 static void si_llvm_emit_ddxy(
1572 const struct lp_build_tgsi_action * action,
1573 struct lp_build_tgsi_context * bld_base,
1574 struct lp_build_emit_data * emit_data)
1575 {
1576 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1577 struct gallivm_state *gallivm = bld_base->base.gallivm;
1578 struct lp_build_context * base = &bld_base->base;
1579 const struct tgsi_full_instruction *inst = emit_data->inst;
1580 unsigned opcode = inst->Instruction.Opcode;
1581 LLVMValueRef indices[2];
1582 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1583 LLVMValueRef tl, trbl, result[4];
1584 LLVMTypeRef i32;
1585 unsigned swizzle[4];
1586 unsigned c;
1587
1588 i32 = LLVMInt32TypeInContext(gallivm->context);
1589
1590 indices[0] = bld_base->uint_bld.zero;
1591 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
1592 NULL, 0, LLVMReadNoneAttribute);
1593 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1594 indices, 2, "");
1595
1596 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
1597 lp_build_const_int32(gallivm, 0xfffffffc), "");
1598 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1599 indices, 2, "");
1600
1601 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
1602 lp_build_const_int32(gallivm,
1603 opcode == TGSI_OPCODE_DDX ? 1 : 2),
1604 "");
1605 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1606 indices, 2, "");
1607
1608 for (c = 0; c < 4; ++c) {
1609 unsigned i;
1610
1611 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
1612 for (i = 0; i < c; ++i) {
1613 if (swizzle[i] == swizzle[c]) {
1614 result[c] = result[i];
1615 break;
1616 }
1617 }
1618 if (i != c)
1619 continue;
1620
1621 LLVMBuildStore(gallivm->builder,
1622 LLVMBuildBitCast(gallivm->builder,
1623 lp_build_emit_fetch(bld_base, inst, 0, c),
1624 i32, ""),
1625 store_ptr);
1626
1627 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
1628 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
1629
1630 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
1631 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
1632
1633 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
1634 }
1635
1636 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
1637 }
1638
1639 #endif /* HAVE_LLVM >= 0x0304 */
1640
1641 static const struct lp_build_tgsi_action tex_action = {
1642 .fetch_args = tex_fetch_args,
1643 .emit = build_tex_intrinsic,
1644 .intr_name = "llvm.SI.sample."
1645 };
1646
1647 static const struct lp_build_tgsi_action txb_action = {
1648 .fetch_args = tex_fetch_args,
1649 .emit = build_tex_intrinsic,
1650 .intr_name = "llvm.SI.sampleb."
1651 };
1652
1653 #if HAVE_LLVM >= 0x0304
1654 static const struct lp_build_tgsi_action txd_action = {
1655 .fetch_args = tex_fetch_args,
1656 .emit = build_tex_intrinsic,
1657 .intr_name = "llvm.SI.sampled."
1658 };
1659 #endif
1660
1661 static const struct lp_build_tgsi_action txf_action = {
1662 .fetch_args = tex_fetch_args,
1663 .emit = build_tex_intrinsic,
1664 .intr_name = "llvm.SI.imageload."
1665 };
1666
1667 static const struct lp_build_tgsi_action txl_action = {
1668 .fetch_args = tex_fetch_args,
1669 .emit = build_tex_intrinsic,
1670 .intr_name = "llvm.SI.samplel."
1671 };
1672
1673 static const struct lp_build_tgsi_action txq_action = {
1674 .fetch_args = txq_fetch_args,
1675 .emit = build_txq_intrinsic,
1676 .intr_name = "llvm.SI.resinfo"
1677 };
1678
1679 static void create_meta_data(struct si_shader_context *si_shader_ctx)
1680 {
1681 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
1682 LLVMValueRef args[3];
1683
1684 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
1685 args[1] = 0;
1686 args[2] = lp_build_const_int32(gallivm, 1);
1687
1688 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
1689 }
1690
1691 static void create_function(struct si_shader_context *si_shader_ctx)
1692 {
1693 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1694 struct gallivm_state *gallivm = bld_base->base.gallivm;
1695 LLVMTypeRef params[21], f32, i8, i32, v2i32, v3i32;
1696 unsigned i, last_sgpr, num_params;
1697
1698 i8 = LLVMInt8TypeInContext(gallivm->context);
1699 i32 = LLVMInt32TypeInContext(gallivm->context);
1700 f32 = LLVMFloatTypeInContext(gallivm->context);
1701 v2i32 = LLVMVectorType(i32, 2);
1702 v3i32 = LLVMVectorType(i32, 3);
1703
1704 params[SI_PARAM_CONST] = LLVMPointerType(
1705 LLVMArrayType(LLVMVectorType(i8, 16), NUM_CONST_BUFFERS), CONST_ADDR_SPACE);
1706 /* We assume at most 16 textures per program at the moment.
1707 * This need probably need to be changed to support bindless textures */
1708 params[SI_PARAM_SAMPLER] = LLVMPointerType(
1709 LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS), CONST_ADDR_SPACE);
1710 params[SI_PARAM_RESOURCE] = LLVMPointerType(
1711 LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES), CONST_ADDR_SPACE);
1712
1713 switch (si_shader_ctx->type) {
1714 case TGSI_PROCESSOR_VERTEX:
1715 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_CONST];
1716 params[SI_PARAM_SO_BUFFER] = params[SI_PARAM_CONST];
1717 params[SI_PARAM_START_INSTANCE] = i32;
1718 num_params = SI_PARAM_START_INSTANCE+1;
1719
1720 /* The locations of the other parameters are assigned dynamically. */
1721
1722 /* Streamout SGPRs. */
1723 if (si_shader_ctx->shader->selector->so.num_outputs) {
1724 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
1725 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
1726 }
1727 /* A streamout buffer offset is loaded if the stride is non-zero. */
1728 for (i = 0; i < 4; i++) {
1729 if (!si_shader_ctx->shader->selector->so.stride[i])
1730 continue;
1731
1732 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
1733 }
1734
1735 last_sgpr = num_params-1;
1736
1737 /* VGPRs */
1738 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
1739 params[num_params++] = i32; /* unused*/
1740 params[num_params++] = i32; /* unused */
1741 params[si_shader_ctx->param_instance_id = num_params++] = i32;
1742 break;
1743
1744 case TGSI_PROCESSOR_FRAGMENT:
1745 params[SI_PARAM_ALPHA_REF] = f32;
1746 params[SI_PARAM_PRIM_MASK] = i32;
1747 last_sgpr = SI_PARAM_PRIM_MASK;
1748 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
1749 params[SI_PARAM_PERSP_CENTER] = v2i32;
1750 params[SI_PARAM_PERSP_CENTROID] = v2i32;
1751 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
1752 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
1753 params[SI_PARAM_LINEAR_CENTER] = v2i32;
1754 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
1755 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
1756 params[SI_PARAM_POS_X_FLOAT] = f32;
1757 params[SI_PARAM_POS_Y_FLOAT] = f32;
1758 params[SI_PARAM_POS_Z_FLOAT] = f32;
1759 params[SI_PARAM_POS_W_FLOAT] = f32;
1760 params[SI_PARAM_FRONT_FACE] = f32;
1761 params[SI_PARAM_ANCILLARY] = f32;
1762 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
1763 params[SI_PARAM_POS_FIXED_PT] = f32;
1764 num_params = SI_PARAM_POS_FIXED_PT+1;
1765 break;
1766
1767 default:
1768 assert(0 && "unimplemented shader");
1769 return;
1770 }
1771
1772 assert(num_params <= Elements(params));
1773 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
1774 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
1775
1776 for (i = 0; i <= last_sgpr; ++i) {
1777 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
1778 switch (i) {
1779 default:
1780 LLVMAddAttribute(P, LLVMInRegAttribute);
1781 break;
1782 #if HAVE_LLVM >= 0x0304
1783 /* We tell llvm that array inputs are passed by value to allow Sinking pass
1784 * to move load. Inputs are constant so this is fine. */
1785 case SI_PARAM_CONST:
1786 case SI_PARAM_SAMPLER:
1787 case SI_PARAM_RESOURCE:
1788 LLVMAddAttribute(P, LLVMByValAttribute);
1789 break;
1790 #endif
1791 }
1792 }
1793
1794 #if HAVE_LLVM >= 0x0304
1795 if (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
1796 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0)
1797 si_shader_ctx->ddxy_lds =
1798 LLVMAddGlobalInAddressSpace(gallivm->module,
1799 LLVMArrayType(i32, 64),
1800 "ddxy_lds",
1801 LOCAL_ADDR_SPACE);
1802 #endif
1803 }
1804
1805 static void preload_constants(struct si_shader_context *si_shader_ctx)
1806 {
1807 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1808 struct gallivm_state * gallivm = bld_base->base.gallivm;
1809 const struct tgsi_shader_info * info = bld_base->info;
1810 unsigned buf;
1811 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1812
1813 for (buf = 0; buf < NUM_CONST_BUFFERS; buf++) {
1814 unsigned i, num_const = info->const_file_max[buf] + 1;
1815
1816 if (num_const == 0)
1817 continue;
1818
1819 /* Allocate space for the constant values */
1820 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
1821
1822 /* Load the resource descriptor */
1823 si_shader_ctx->const_resource[buf] =
1824 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
1825
1826 /* Load the constants, we rely on the code sinking to do the rest */
1827 for (i = 0; i < num_const * 4; ++i) {
1828 LLVMValueRef args[2] = {
1829 si_shader_ctx->const_resource[buf],
1830 lp_build_const_int32(gallivm, i * 4)
1831 };
1832 si_shader_ctx->constants[buf][i] =
1833 build_intrinsic(gallivm->builder, "llvm.SI.load.const",
1834 bld_base->base.elem_type, args, 2,
1835 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1836 }
1837 }
1838 }
1839
1840 static void preload_samplers(struct si_shader_context *si_shader_ctx)
1841 {
1842 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1843 struct gallivm_state * gallivm = bld_base->base.gallivm;
1844 const struct tgsi_shader_info * info = bld_base->info;
1845
1846 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
1847
1848 LLVMValueRef res_ptr, samp_ptr;
1849 LLVMValueRef offset;
1850
1851 if (num_samplers == 0)
1852 return;
1853
1854 /* Allocate space for the values */
1855 si_shader_ctx->resources = CALLOC(NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
1856 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
1857
1858 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
1859 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
1860
1861 /* Load the resources and samplers, we rely on the code sinking to do the rest */
1862 for (i = 0; i < num_samplers; ++i) {
1863 /* Resource */
1864 offset = lp_build_const_int32(gallivm, i);
1865 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
1866
1867 /* Sampler */
1868 offset = lp_build_const_int32(gallivm, i);
1869 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
1870
1871 /* FMASK resource */
1872 if (info->is_msaa_sampler[i]) {
1873 offset = lp_build_const_int32(gallivm, FMASK_TEX_OFFSET + i);
1874 si_shader_ctx->resources[FMASK_TEX_OFFSET + i] =
1875 build_indexed_load(si_shader_ctx, res_ptr, offset);
1876 }
1877 }
1878 }
1879
1880 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
1881 {
1882 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1883 struct gallivm_state * gallivm = bld_base->base.gallivm;
1884 unsigned i;
1885
1886 if (!si_shader_ctx->shader->selector->so.num_outputs)
1887 return;
1888
1889 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1890 SI_PARAM_SO_BUFFER);
1891
1892 /* Load the resources, we rely on the code sinking to do the rest */
1893 for (i = 0; i < 4; ++i) {
1894 if (si_shader_ctx->shader->selector->so.stride[i]) {
1895 LLVMValueRef offset = lp_build_const_int32(gallivm, i);
1896
1897 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
1898 }
1899 }
1900 }
1901
1902 int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader,
1903 LLVMModuleRef mod)
1904 {
1905 unsigned i;
1906 uint32_t *ptr;
1907 struct radeon_llvm_binary binary;
1908 bool dump = r600_can_dump_shader(&rctx->screen->b,
1909 shader->selector ? shader->selector->tokens : NULL);
1910 memset(&binary, 0, sizeof(binary));
1911 radeon_llvm_compile(mod, &binary,
1912 r600_get_llvm_processor_name(rctx->screen->b.family), dump);
1913 if (dump && ! binary.disassembled) {
1914 fprintf(stderr, "SI CODE:\n");
1915 for (i = 0; i < binary.code_size; i+=4 ) {
1916 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
1917 binary.code[i + 2], binary.code[i + 1],
1918 binary.code[i]);
1919 }
1920 }
1921
1922 /* XXX: We may be able to emit some of these values directly rather than
1923 * extracting fields to be emitted later.
1924 */
1925 for (i = 0; i < binary.config_size; i+= 8) {
1926 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
1927 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
1928 switch (reg) {
1929 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
1930 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
1931 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
1932 case R_00B848_COMPUTE_PGM_RSRC1:
1933 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
1934 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
1935 break;
1936 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
1937 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
1938 break;
1939 case R_00B84C_COMPUTE_PGM_RSRC2:
1940 shader->lds_size = G_00B84C_LDS_SIZE(value);
1941 break;
1942 case R_0286CC_SPI_PS_INPUT_ENA:
1943 shader->spi_ps_input_ena = value;
1944 break;
1945 default:
1946 fprintf(stderr, "Warning: Compiler emitted unknown "
1947 "config register: 0x%x\n", reg);
1948 break;
1949 }
1950 }
1951
1952 /* copy new shader */
1953 r600_resource_reference(&shader->bo, NULL);
1954 shader->bo = r600_resource_create_custom(rctx->b.b.screen, PIPE_USAGE_IMMUTABLE,
1955 binary.code_size);
1956 if (shader->bo == NULL) {
1957 return -ENOMEM;
1958 }
1959
1960 ptr = (uint32_t*)rctx->b.ws->buffer_map(shader->bo->cs_buf, rctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
1961 if (0 /*R600_BIG_ENDIAN*/) {
1962 for (i = 0; i < binary.code_size / 4; ++i) {
1963 ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
1964 }
1965 } else {
1966 memcpy(ptr, binary.code, binary.code_size);
1967 }
1968 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
1969
1970 free(binary.code);
1971 free(binary.config);
1972
1973 return 0;
1974 }
1975
1976 int si_pipe_shader_create(
1977 struct pipe_context *ctx,
1978 struct si_pipe_shader *shader)
1979 {
1980 struct r600_context *rctx = (struct r600_context*)ctx;
1981 struct si_pipe_shader_selector *sel = shader->selector;
1982 struct si_shader_context si_shader_ctx;
1983 struct tgsi_shader_info shader_info;
1984 struct lp_build_tgsi_context * bld_base;
1985 LLVMModuleRef mod;
1986 int r = 0;
1987 bool dump = r600_can_dump_shader(&rctx->screen->b, shader->selector->tokens);
1988
1989 assert(shader->shader.noutput == 0);
1990 assert(shader->shader.ninterp == 0);
1991 assert(shader->shader.ninput == 0);
1992
1993 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
1994 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
1995 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
1996
1997 tgsi_scan_shader(sel->tokens, &shader_info);
1998
1999 shader->shader.uses_kill = shader_info.uses_kill;
2000 shader->shader.uses_instanceid = shader_info.uses_instanceid;
2001 bld_base->info = &shader_info;
2002 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2003 bld_base->emit_epilogue = si_llvm_emit_epilogue;
2004
2005 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2006 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
2007 #if HAVE_LLVM >= 0x0304
2008 bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
2009 #endif
2010 bld_base->op_actions[TGSI_OPCODE_TXF] = txf_action;
2011 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
2012 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2013 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2014
2015 #if HAVE_LLVM >= 0x0304
2016 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2017 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2018 #endif
2019
2020 si_shader_ctx.radeon_bld.load_input = declare_input;
2021 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2022 si_shader_ctx.tokens = sel->tokens;
2023 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2024 si_shader_ctx.shader = shader;
2025 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2026
2027 create_meta_data(&si_shader_ctx);
2028 create_function(&si_shader_ctx);
2029 preload_constants(&si_shader_ctx);
2030 preload_samplers(&si_shader_ctx);
2031 preload_streamout_buffers(&si_shader_ctx);
2032
2033 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
2034
2035 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2036 * conversion fails. */
2037 if (dump) {
2038 tgsi_dump(sel->tokens, 0);
2039 si_dump_streamout(&sel->so);
2040 }
2041
2042 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2043 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2044 for (int i = 0; i < NUM_CONST_BUFFERS; i++)
2045 FREE(si_shader_ctx.constants[i]);
2046 FREE(si_shader_ctx.resources);
2047 FREE(si_shader_ctx.samplers);
2048 return -EINVAL;
2049 }
2050
2051 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2052
2053 mod = bld_base->base.gallivm->module;
2054 r = si_compile_llvm(rctx, shader, mod);
2055
2056 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2057 tgsi_parse_free(&si_shader_ctx.parse);
2058
2059 for (int i = 0; i < NUM_CONST_BUFFERS; i++)
2060 FREE(si_shader_ctx.constants[i]);
2061 FREE(si_shader_ctx.resources);
2062 FREE(si_shader_ctx.samplers);
2063
2064 return r;
2065 }
2066
2067 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
2068 {
2069 r600_resource_reference(&shader->bo, NULL);
2070 }