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radeonsi: implement OpenGL edge flags
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "gallivm/lp_bld_arit.h"
37 #include "gallivm/lp_bld_flow.h"
38 #include "radeon_llvm.h"
39 #include "radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_scan.h"
44 #include "tgsi/tgsi_util.h"
45 #include "tgsi/tgsi_dump.h"
46
47 #include "radeonsi_pipe.h"
48 #include "radeonsi_shader.h"
49 #include "si_state.h"
50 #include "sid.h"
51
52 #include <assert.h>
53 #include <errno.h>
54 #include <stdio.h>
55
56 struct si_shader_context
57 {
58 struct radeon_llvm_context radeon_bld;
59 struct tgsi_parse_context parse;
60 struct tgsi_token * tokens;
61 struct si_pipe_shader *shader;
62 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
63 int param_streamout_config;
64 int param_streamout_write_index;
65 int param_streamout_offset[4];
66 int param_vertex_id;
67 int param_instance_id;
68 LLVMValueRef const_md;
69 LLVMValueRef const_resource[NUM_CONST_BUFFERS];
70 #if HAVE_LLVM >= 0x0304
71 LLVMValueRef ddxy_lds;
72 #endif
73 LLVMValueRef *constants[NUM_CONST_BUFFERS];
74 LLVMValueRef *resources;
75 LLVMValueRef *samplers;
76 LLVMValueRef so_buffers[4];
77 };
78
79 static struct si_shader_context * si_shader_context(
80 struct lp_build_tgsi_context * bld_base)
81 {
82 return (struct si_shader_context *)bld_base;
83 }
84
85
86 #define PERSPECTIVE_BASE 0
87 #define LINEAR_BASE 9
88
89 #define SAMPLE_OFFSET 0
90 #define CENTER_OFFSET 2
91 #define CENTROID_OFSET 4
92
93 #define USE_SGPR_MAX_SUFFIX_LEN 5
94 #define CONST_ADDR_SPACE 2
95 #define LOCAL_ADDR_SPACE 3
96 #define USER_SGPR_ADDR_SPACE 8
97
98 /**
99 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
100 *
101 * @param offset The offset parameter specifies the number of
102 * elements to offset, not the number of bytes or dwords. An element is the
103 * the type pointed to by the base_ptr parameter (e.g. int is the element of
104 * an int* pointer)
105 *
106 * When LLVM lowers the load instruction, it will convert the element offset
107 * into a dword offset automatically.
108 *
109 */
110 static LLVMValueRef build_indexed_load(
111 struct si_shader_context * si_shader_ctx,
112 LLVMValueRef base_ptr,
113 LLVMValueRef offset)
114 {
115 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
116
117 LLVMValueRef indices[2] = {
118 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
119 offset
120 };
121 LLVMValueRef computed_ptr = LLVMBuildGEP(
122 base->gallivm->builder, base_ptr, indices, 2, "");
123
124 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
125 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
126 return result;
127 }
128
129 static LLVMValueRef get_instance_index_for_fetch(
130 struct radeon_llvm_context * radeon_bld,
131 unsigned divisor)
132 {
133 struct si_shader_context *si_shader_ctx =
134 si_shader_context(&radeon_bld->soa.bld_base);
135 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
136
137 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
138 si_shader_ctx->param_instance_id);
139 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
140 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
141
142 if (divisor > 1)
143 result = LLVMBuildUDiv(gallivm->builder, result,
144 lp_build_const_int32(gallivm, divisor), "");
145
146 return result;
147 }
148
149 static void declare_input_vs(
150 struct si_shader_context * si_shader_ctx,
151 unsigned input_index,
152 const struct tgsi_full_declaration *decl)
153 {
154 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
155 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
156
157 unsigned chan;
158
159 LLVMValueRef t_list_ptr;
160 LLVMValueRef t_offset;
161 LLVMValueRef t_list;
162 LLVMValueRef attribute_offset;
163 LLVMValueRef buffer_index;
164 LLVMValueRef args[3];
165 LLVMTypeRef vec4_type;
166 LLVMValueRef input;
167
168 /* Load the T list */
169 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
170
171 t_offset = lp_build_const_int32(base->gallivm, input_index);
172
173 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
174
175 /* Build the attribute offset */
176 attribute_offset = lp_build_const_int32(base->gallivm, 0);
177
178 if (divisor) {
179 /* Build index from instance ID, start instance and divisor */
180 si_shader_ctx->shader->shader.uses_instanceid = true;
181 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
182 } else {
183 /* Load the buffer index, which is always stored in VGPR0
184 * for Vertex Shaders */
185 buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
186 si_shader_ctx->param_vertex_id);
187 }
188
189 vec4_type = LLVMVectorType(base->elem_type, 4);
190 args[0] = t_list;
191 args[1] = attribute_offset;
192 args[2] = buffer_index;
193 input = build_intrinsic(base->gallivm->builder,
194 "llvm.SI.vs.load.input", vec4_type, args, 3,
195 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
196
197 /* Break up the vec4 into individual components */
198 for (chan = 0; chan < 4; chan++) {
199 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
200 /* XXX: Use a helper function for this. There is one in
201 * tgsi_llvm.c. */
202 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
203 LLVMBuildExtractElement(base->gallivm->builder,
204 input, llvm_chan, "");
205 }
206 }
207
208 static void declare_input_fs(
209 struct si_shader_context * si_shader_ctx,
210 unsigned input_index,
211 const struct tgsi_full_declaration *decl)
212 {
213 struct si_shader *shader = &si_shader_ctx->shader->shader;
214 struct lp_build_context * base =
215 &si_shader_ctx->radeon_bld.soa.bld_base.base;
216 struct lp_build_context *uint =
217 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
218 struct gallivm_state * gallivm = base->gallivm;
219 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
220 LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
221
222 LLVMValueRef interp_param;
223 const char * intr_name;
224
225 /* This value is:
226 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
227 * quad begins a new primitive. Bit 0 always needs
228 * to be unset)
229 * [32:16] ParamOffset
230 *
231 */
232 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
233 LLVMValueRef attr_number;
234
235 unsigned chan;
236
237 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
238 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
239 unsigned soa_index =
240 radeon_llvm_reg_index_soa(input_index, chan);
241 si_shader_ctx->radeon_bld.inputs[soa_index] =
242 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
243
244 if (chan == 3)
245 /* RCP for fragcoord.w */
246 si_shader_ctx->radeon_bld.inputs[soa_index] =
247 LLVMBuildFDiv(gallivm->builder,
248 lp_build_const_float(gallivm, 1.0f),
249 si_shader_ctx->radeon_bld.inputs[soa_index],
250 "");
251 }
252 return;
253 }
254
255 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
256 LLVMValueRef face, is_face_positive;
257
258 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
259
260 is_face_positive = LLVMBuildFCmp(gallivm->builder,
261 LLVMRealUGT, face,
262 lp_build_const_float(gallivm, 0.0f),
263 "");
264
265 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
266 LLVMBuildSelect(gallivm->builder,
267 is_face_positive,
268 lp_build_const_float(gallivm, 1.0f),
269 lp_build_const_float(gallivm, 0.0f),
270 "");
271 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
272 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
273 lp_build_const_float(gallivm, 0.0f);
274 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
275 lp_build_const_float(gallivm, 1.0f);
276
277 return;
278 }
279
280 shader->input[input_index].param_offset = shader->ninterp++;
281 attr_number = lp_build_const_int32(gallivm,
282 shader->input[input_index].param_offset);
283
284 /* XXX: Handle all possible interpolation modes */
285 switch (decl->Interp.Interpolate) {
286 case TGSI_INTERPOLATE_COLOR:
287 if (si_shader_ctx->shader->key.ps.flatshade) {
288 interp_param = 0;
289 } else {
290 if (decl->Interp.Centroid)
291 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
292 else
293 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
294 }
295 break;
296 case TGSI_INTERPOLATE_CONSTANT:
297 interp_param = 0;
298 break;
299 case TGSI_INTERPOLATE_LINEAR:
300 if (decl->Interp.Centroid)
301 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
302 else
303 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
304 break;
305 case TGSI_INTERPOLATE_PERSPECTIVE:
306 if (decl->Interp.Centroid)
307 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
308 else
309 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
310 break;
311 default:
312 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
313 return;
314 }
315
316 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
317
318 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
319 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
320 si_shader_ctx->shader->key.ps.color_two_side) {
321 LLVMValueRef args[4];
322 LLVMValueRef face, is_face_positive;
323 LLVMValueRef back_attr_number =
324 lp_build_const_int32(gallivm,
325 shader->input[input_index].param_offset + 1);
326
327 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
328
329 is_face_positive = LLVMBuildFCmp(gallivm->builder,
330 LLVMRealUGT, face,
331 lp_build_const_float(gallivm, 0.0f),
332 "");
333
334 args[2] = params;
335 args[3] = interp_param;
336 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
337 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
338 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
339 LLVMValueRef front, back;
340
341 args[0] = llvm_chan;
342 args[1] = attr_number;
343 front = build_intrinsic(base->gallivm->builder, intr_name,
344 input_type, args, args[3] ? 4 : 3,
345 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
346
347 args[1] = back_attr_number;
348 back = build_intrinsic(base->gallivm->builder, intr_name,
349 input_type, args, args[3] ? 4 : 3,
350 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
351
352 si_shader_ctx->radeon_bld.inputs[soa_index] =
353 LLVMBuildSelect(gallivm->builder,
354 is_face_positive,
355 front,
356 back,
357 "");
358 }
359
360 shader->ninterp++;
361 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
362 LLVMValueRef args[4];
363
364 args[0] = uint->zero;
365 args[1] = attr_number;
366 args[2] = params;
367 args[3] = interp_param;
368 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
369 build_intrinsic(base->gallivm->builder, intr_name,
370 input_type, args, args[3] ? 4 : 3,
371 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
372 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
373 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
374 lp_build_const_float(gallivm, 0.0f);
375 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
376 lp_build_const_float(gallivm, 1.0f);
377 } else {
378 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
379 LLVMValueRef args[4];
380 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
381 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
382 args[0] = llvm_chan;
383 args[1] = attr_number;
384 args[2] = params;
385 args[3] = interp_param;
386 si_shader_ctx->radeon_bld.inputs[soa_index] =
387 build_intrinsic(base->gallivm->builder, intr_name,
388 input_type, args, args[3] ? 4 : 3,
389 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
390 }
391 }
392 }
393
394 static void declare_input(
395 struct radeon_llvm_context * radeon_bld,
396 unsigned input_index,
397 const struct tgsi_full_declaration *decl)
398 {
399 struct si_shader_context * si_shader_ctx =
400 si_shader_context(&radeon_bld->soa.bld_base);
401 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
402 declare_input_vs(si_shader_ctx, input_index, decl);
403 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
404 declare_input_fs(si_shader_ctx, input_index, decl);
405 } else {
406 fprintf(stderr, "Warning: Unsupported shader type,\n");
407 }
408 }
409
410 static void declare_system_value(
411 struct radeon_llvm_context * radeon_bld,
412 unsigned index,
413 const struct tgsi_full_declaration *decl)
414 {
415 struct si_shader_context *si_shader_ctx =
416 si_shader_context(&radeon_bld->soa.bld_base);
417 LLVMValueRef value = 0;
418
419 switch (decl->Semantic.Name) {
420 case TGSI_SEMANTIC_INSTANCEID:
421 value = LLVMGetParam(radeon_bld->main_fn,
422 si_shader_ctx->param_instance_id);
423 break;
424
425 case TGSI_SEMANTIC_VERTEXID:
426 value = LLVMGetParam(radeon_bld->main_fn,
427 si_shader_ctx->param_vertex_id);
428 break;
429
430 default:
431 assert(!"unknown system value");
432 return;
433 }
434
435 radeon_bld->system_values[index] = value;
436 }
437
438 static LLVMValueRef fetch_constant(
439 struct lp_build_tgsi_context * bld_base,
440 const struct tgsi_full_src_register *reg,
441 enum tgsi_opcode_type type,
442 unsigned swizzle)
443 {
444 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
445 struct lp_build_context * base = &bld_base->base;
446 const struct tgsi_ind_register *ireg = &reg->Indirect;
447 unsigned buf, idx;
448
449 LLVMValueRef args[2];
450 LLVMValueRef addr;
451 LLVMValueRef result;
452
453 if (swizzle == LP_CHAN_ALL) {
454 unsigned chan;
455 LLVMValueRef values[4];
456 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
457 values[chan] = fetch_constant(bld_base, reg, type, chan);
458
459 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
460 }
461
462 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
463 idx = reg->Register.Index * 4 + swizzle;
464
465 if (!reg->Register.Indirect)
466 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
467
468 args[0] = si_shader_ctx->const_resource[buf];
469 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
470 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
471 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
472 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
473 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
474
475 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
476 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
477
478 return bitcast(bld_base, type, result);
479 }
480
481 /* Initialize arguments for the shader export intrinsic */
482 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
483 struct tgsi_full_declaration *d,
484 unsigned index,
485 unsigned target,
486 LLVMValueRef *args)
487 {
488 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
489 struct lp_build_context *uint =
490 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
491 struct lp_build_context *base = &bld_base->base;
492 unsigned compressed = 0;
493 unsigned chan;
494
495 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
496 int cbuf = target - V_008DFC_SQ_EXP_MRT;
497
498 if (cbuf >= 0 && cbuf < 8) {
499 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
500
501 if (compressed)
502 si_shader_ctx->shader->spi_shader_col_format |=
503 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
504 else
505 si_shader_ctx->shader->spi_shader_col_format |=
506 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
507
508 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
509 }
510 }
511
512 if (compressed) {
513 /* Pixel shader needs to pack output values before export */
514 for (chan = 0; chan < 2; chan++ ) {
515 LLVMValueRef *out_ptr =
516 si_shader_ctx->radeon_bld.soa.outputs[index];
517 args[0] = LLVMBuildLoad(base->gallivm->builder,
518 out_ptr[2 * chan], "");
519 args[1] = LLVMBuildLoad(base->gallivm->builder,
520 out_ptr[2 * chan + 1], "");
521 args[chan + 5] =
522 build_intrinsic(base->gallivm->builder,
523 "llvm.SI.packf16",
524 LLVMInt32TypeInContext(base->gallivm->context),
525 args, 2,
526 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
527 args[chan + 7] = args[chan + 5] =
528 LLVMBuildBitCast(base->gallivm->builder,
529 args[chan + 5],
530 LLVMFloatTypeInContext(base->gallivm->context),
531 "");
532 }
533
534 /* Set COMPR flag */
535 args[4] = uint->one;
536 } else {
537 for (chan = 0; chan < 4; chan++ ) {
538 LLVMValueRef out_ptr =
539 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
540 /* +5 because the first output value will be
541 * the 6th argument to the intrinsic. */
542 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
543 out_ptr, "");
544 }
545
546 /* Clear COMPR flag */
547 args[4] = uint->zero;
548 }
549
550 /* XXX: This controls which components of the output
551 * registers actually get exported. (e.g bit 0 means export
552 * X component, bit 1 means export Y component, etc.) I'm
553 * hard coding this to 0xf for now. In the future, we might
554 * want to do something else. */
555 args[0] = lp_build_const_int32(base->gallivm, 0xf);
556
557 /* Specify whether the EXEC mask represents the valid mask */
558 args[1] = uint->zero;
559
560 /* Specify whether this is the last export */
561 args[2] = uint->zero;
562
563 /* Specify the target we are exporting */
564 args[3] = lp_build_const_int32(base->gallivm, target);
565
566 /* XXX: We probably need to keep track of the output
567 * values, so we know what we are passing to the next
568 * stage. */
569 }
570
571 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
572 unsigned index)
573 {
574 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
575 struct gallivm_state *gallivm = bld_base->base.gallivm;
576
577 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
578 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
579 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
580 SI_PARAM_ALPHA_REF);
581
582 LLVMValueRef alpha_pass =
583 lp_build_cmp(&bld_base->base,
584 si_shader_ctx->shader->key.ps.alpha_func,
585 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
586 alpha_ref);
587 LLVMValueRef arg =
588 lp_build_select(&bld_base->base,
589 alpha_pass,
590 lp_build_const_float(gallivm, 1.0f),
591 lp_build_const_float(gallivm, -1.0f));
592
593 build_intrinsic(gallivm->builder,
594 "llvm.AMDGPU.kill",
595 LLVMVoidTypeInContext(gallivm->context),
596 &arg, 1, 0);
597 } else {
598 build_intrinsic(gallivm->builder,
599 "llvm.AMDGPU.kilp",
600 LLVMVoidTypeInContext(gallivm->context),
601 NULL, 0, 0);
602 }
603 }
604
605 static void si_alpha_to_one(struct lp_build_tgsi_context *bld_base,
606 unsigned index)
607 {
608 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
609
610 /* set alpha to one */
611 LLVMBuildStore(bld_base->base.gallivm->builder,
612 bld_base->base.one,
613 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
614 }
615
616 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
617 LLVMValueRef (*pos)[9], unsigned index)
618 {
619 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
620 struct si_pipe_shader *shader = si_shader_ctx->shader;
621 struct lp_build_context *base = &bld_base->base;
622 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
623 unsigned reg_index;
624 unsigned chan;
625 unsigned const_chan;
626 LLVMValueRef out_elts[4];
627 LLVMValueRef base_elt;
628 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
629 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, NUM_PIPE_CONST_BUFFERS);
630 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
631
632 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
633 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][chan];
634 out_elts[chan] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
635 }
636
637 for (reg_index = 0; reg_index < 2; reg_index ++) {
638 LLVMValueRef *args = pos[2 + reg_index];
639
640 if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
641 continue;
642
643 shader->shader.clip_dist_write |= 0xf << (4 * reg_index);
644
645 args[5] =
646 args[6] =
647 args[7] =
648 args[8] = lp_build_const_float(base->gallivm, 0.0f);
649
650 /* Compute dot products of position and user clip plane vectors */
651 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
652 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
653 args[0] = const_resource;
654 args[1] = lp_build_const_int32(base->gallivm,
655 ((reg_index * 4 + chan) * 4 +
656 const_chan) * 4);
657 base_elt = build_intrinsic(base->gallivm->builder,
658 "llvm.SI.load.const",
659 base->elem_type,
660 args, 2,
661 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
662 args[5 + chan] =
663 lp_build_add(base, args[5 + chan],
664 lp_build_mul(base, base_elt,
665 out_elts[const_chan]));
666 }
667 }
668
669 args[0] = lp_build_const_int32(base->gallivm, 0xf);
670 args[1] = uint->zero;
671 args[2] = uint->zero;
672 args[3] = lp_build_const_int32(base->gallivm,
673 V_008DFC_SQ_EXP_POS + 2 + reg_index);
674 args[4] = uint->zero;
675 }
676 }
677
678 static void si_dump_streamout(struct pipe_stream_output_info *so)
679 {
680 unsigned i;
681
682 if (so->num_outputs)
683 fprintf(stderr, "STREAMOUT\n");
684
685 for (i = 0; i < so->num_outputs; i++) {
686 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
687 so->output[i].start_component;
688 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
689 i, so->output[i].output_buffer,
690 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
691 so->output[i].register_index,
692 mask & 1 ? "x" : "",
693 mask & 2 ? "y" : "",
694 mask & 4 ? "z" : "",
695 mask & 8 ? "w" : "");
696 }
697 }
698
699 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
700 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
701 * or v4i32 (num_channels=3,4). */
702 static void build_tbuffer_store(struct si_shader_context *shader,
703 LLVMValueRef rsrc,
704 LLVMValueRef vdata,
705 unsigned num_channels,
706 LLVMValueRef vaddr,
707 LLVMValueRef soffset,
708 unsigned inst_offset,
709 unsigned dfmt,
710 unsigned nfmt,
711 unsigned offen,
712 unsigned idxen,
713 unsigned glc,
714 unsigned slc,
715 unsigned tfe)
716 {
717 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
718 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
719 LLVMValueRef args[] = {
720 rsrc,
721 vdata,
722 LLVMConstInt(i32, num_channels, 0),
723 vaddr,
724 soffset,
725 LLVMConstInt(i32, inst_offset, 0),
726 LLVMConstInt(i32, dfmt, 0),
727 LLVMConstInt(i32, nfmt, 0),
728 LLVMConstInt(i32, offen, 0),
729 LLVMConstInt(i32, idxen, 0),
730 LLVMConstInt(i32, glc, 0),
731 LLVMConstInt(i32, slc, 0),
732 LLVMConstInt(i32, tfe, 0)
733 };
734
735 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
736 unsigned func = CLAMP(num_channels, 1, 3) - 1;
737 const char *types[] = {"i32", "v2i32", "v4i32"};
738 char name[256];
739 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
740
741 lp_build_intrinsic(gallivm->builder, name,
742 LLVMVoidTypeInContext(gallivm->context),
743 args, Elements(args));
744 }
745
746 static void build_streamout_store(struct si_shader_context *shader,
747 LLVMValueRef rsrc,
748 LLVMValueRef vdata,
749 unsigned num_channels,
750 LLVMValueRef vaddr,
751 LLVMValueRef soffset,
752 unsigned inst_offset)
753 {
754 static unsigned dfmt[] = {
755 V_008F0C_BUF_DATA_FORMAT_32,
756 V_008F0C_BUF_DATA_FORMAT_32_32,
757 V_008F0C_BUF_DATA_FORMAT_32_32_32,
758 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
759 };
760 assert(num_channels >= 1 && num_channels <= 4);
761
762 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
763 inst_offset, dfmt[num_channels-1],
764 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
765 }
766
767 /* On SI, the vertex shader is responsible for writing streamout data
768 * to buffers. */
769 static void si_llvm_emit_streamout(struct si_shader_context *shader)
770 {
771 struct pipe_stream_output_info *so = &shader->shader->selector->so;
772 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
773 LLVMBuilderRef builder = gallivm->builder;
774 int i, j;
775 struct lp_build_if_state if_ctx;
776
777 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
778
779 LLVMValueRef so_param =
780 LLVMGetParam(shader->radeon_bld.main_fn,
781 shader->param_streamout_config);
782
783 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
784 LLVMValueRef so_vtx_count =
785 LLVMBuildAnd(builder,
786 LLVMBuildLShr(builder, so_param,
787 LLVMConstInt(i32, 16, 0), ""),
788 LLVMConstInt(i32, 127, 0), "");
789
790 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
791 NULL, 0, LLVMReadNoneAttribute);
792
793 /* can_emit = tid < so_vtx_count; */
794 LLVMValueRef can_emit =
795 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
796
797 /* Emit the streamout code conditionally. This actually avoids
798 * out-of-bounds buffer access. The hw tells us via the SGPR
799 * (so_vtx_count) which threads are allowed to emit streamout data. */
800 lp_build_if(&if_ctx, gallivm, can_emit);
801 {
802 /* The buffer offset is computed as follows:
803 * ByteOffset = streamout_offset[buffer_id]*4 +
804 * (streamout_write_index + thread_id)*stride[buffer_id] +
805 * attrib_offset
806 */
807
808 LLVMValueRef so_write_index =
809 LLVMGetParam(shader->radeon_bld.main_fn,
810 shader->param_streamout_write_index);
811
812 /* Compute (streamout_write_index + thread_id). */
813 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
814
815 /* Compute the write offset for each enabled buffer. */
816 LLVMValueRef so_write_offset[4] = {};
817 for (i = 0; i < 4; i++) {
818 if (!so->stride[i])
819 continue;
820
821 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
822 shader->param_streamout_offset[i]);
823 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
824
825 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
826 LLVMConstInt(i32, so->stride[i]*4, 0), "");
827 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
828 }
829
830 LLVMValueRef (*outputs)[TGSI_NUM_CHANNELS] = shader->radeon_bld.soa.outputs;
831
832 /* Write streamout data. */
833 for (i = 0; i < so->num_outputs; i++) {
834 unsigned buf_idx = so->output[i].output_buffer;
835 unsigned reg = so->output[i].register_index;
836 unsigned start = so->output[i].start_component;
837 unsigned num_comps = so->output[i].num_components;
838 LLVMValueRef out[4];
839
840 assert(num_comps && num_comps <= 4);
841 if (!num_comps || num_comps > 4)
842 continue;
843
844 /* Load the output as int. */
845 for (j = 0; j < num_comps; j++) {
846 out[j] = LLVMBuildLoad(builder, outputs[reg][start+j], "");
847 out[j] = LLVMBuildBitCast(builder, out[j], i32, "");
848 }
849
850 /* Pack the output. */
851 LLVMValueRef vdata = NULL;
852
853 switch (num_comps) {
854 case 1: /* as i32 */
855 vdata = out[0];
856 break;
857 case 2: /* as v2i32 */
858 case 3: /* as v4i32 (aligned to 4) */
859 case 4: /* as v4i32 */
860 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
861 for (j = 0; j < num_comps; j++) {
862 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
863 LLVMConstInt(i32, j, 0), "");
864 }
865 break;
866 }
867
868 build_streamout_store(shader, shader->so_buffers[buf_idx],
869 vdata, num_comps,
870 so_write_offset[buf_idx],
871 LLVMConstInt(i32, 0, 0),
872 so->output[i].dst_offset*4);
873 }
874 }
875 lp_build_endif(&if_ctx);
876 }
877
878 /* XXX: This is partially implemented for VS only at this point. It is not complete */
879 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
880 {
881 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
882 struct si_shader * shader = &si_shader_ctx->shader->shader;
883 struct lp_build_context * base = &bld_base->base;
884 struct lp_build_context * uint =
885 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
886 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
887 LLVMValueRef args[9];
888 LLVMValueRef last_args[9] = { 0 };
889 LLVMValueRef pos_args[4][9] = { { 0 } };
890 unsigned semantic_name;
891 unsigned param_count = 0;
892 int depth_index = -1, stencil_index = -1, psize_index = -1, edgeflag_index = -1;
893 int i;
894
895 if (si_shader_ctx->shader->selector->so.num_outputs) {
896 si_llvm_emit_streamout(si_shader_ctx);
897 }
898
899 while (!tgsi_parse_end_of_tokens(parse)) {
900 struct tgsi_full_declaration *d =
901 &parse->FullToken.FullDeclaration;
902 unsigned target;
903 unsigned index;
904
905 tgsi_parse_token(parse);
906
907 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
908 parse->FullToken.FullProperty.Property.PropertyName ==
909 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
910 shader->fs_write_all = TRUE;
911
912 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
913 continue;
914
915 switch (d->Declaration.File) {
916 case TGSI_FILE_INPUT:
917 i = shader->ninput++;
918 assert(i < Elements(shader->input));
919 shader->input[i].name = d->Semantic.Name;
920 shader->input[i].sid = d->Semantic.Index;
921 shader->input[i].interpolate = d->Interp.Interpolate;
922 shader->input[i].centroid = d->Interp.Centroid;
923 continue;
924
925 case TGSI_FILE_OUTPUT:
926 i = shader->noutput++;
927 assert(i < Elements(shader->output));
928 shader->output[i].name = d->Semantic.Name;
929 shader->output[i].sid = d->Semantic.Index;
930 shader->output[i].interpolate = d->Interp.Interpolate;
931 break;
932
933 default:
934 continue;
935 }
936
937 semantic_name = d->Semantic.Name;
938 handle_semantic:
939 for (index = d->Range.First; index <= d->Range.Last; index++) {
940 /* Select the correct target */
941 switch(semantic_name) {
942 case TGSI_SEMANTIC_PSIZE:
943 shader->vs_out_misc_write = true;
944 shader->vs_out_point_size = true;
945 psize_index = index;
946 continue;
947 case TGSI_SEMANTIC_EDGEFLAG:
948 shader->vs_out_misc_write = true;
949 shader->vs_out_edgeflag = true;
950 edgeflag_index = index;
951 continue;
952 case TGSI_SEMANTIC_POSITION:
953 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
954 target = V_008DFC_SQ_EXP_POS;
955 break;
956 } else {
957 depth_index = index;
958 continue;
959 }
960 case TGSI_SEMANTIC_STENCIL:
961 stencil_index = index;
962 continue;
963 case TGSI_SEMANTIC_COLOR:
964 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
965 case TGSI_SEMANTIC_BCOLOR:
966 target = V_008DFC_SQ_EXP_PARAM + param_count;
967 shader->output[i].param_offset = param_count;
968 param_count++;
969 } else {
970 target = V_008DFC_SQ_EXP_MRT + shader->output[i].sid;
971 if (si_shader_ctx->shader->key.ps.alpha_to_one) {
972 si_alpha_to_one(bld_base, index);
973 }
974 if (shader->output[i].sid == 0 &&
975 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
976 si_alpha_test(bld_base, index);
977 }
978 break;
979 case TGSI_SEMANTIC_CLIPDIST:
980 if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
981 (1 << d->Semantic.Index)))
982 continue;
983 shader->clip_dist_write |=
984 d->Declaration.UsageMask << (d->Semantic.Index << 2);
985 target = V_008DFC_SQ_EXP_POS + 2 + d->Semantic.Index;
986 break;
987 case TGSI_SEMANTIC_CLIPVERTEX:
988 si_llvm_emit_clipvertex(bld_base, pos_args, index);
989 continue;
990 case TGSI_SEMANTIC_FOG:
991 case TGSI_SEMANTIC_GENERIC:
992 target = V_008DFC_SQ_EXP_PARAM + param_count;
993 shader->output[i].param_offset = param_count;
994 param_count++;
995 break;
996 default:
997 target = 0;
998 fprintf(stderr,
999 "Warning: SI unhandled output type:%d\n",
1000 semantic_name);
1001 }
1002
1003 si_llvm_init_export_args(bld_base, d, index, target, args);
1004
1005 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
1006 target >= V_008DFC_SQ_EXP_POS &&
1007 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1008 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1009 args, sizeof(args));
1010 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT &&
1011 semantic_name == TGSI_SEMANTIC_COLOR) {
1012 if (last_args[0]) {
1013 lp_build_intrinsic(base->gallivm->builder,
1014 "llvm.SI.export",
1015 LLVMVoidTypeInContext(base->gallivm->context),
1016 last_args, 9);
1017 }
1018
1019 memcpy(last_args, args, sizeof(args));
1020 } else {
1021 lp_build_intrinsic(base->gallivm->builder,
1022 "llvm.SI.export",
1023 LLVMVoidTypeInContext(base->gallivm->context),
1024 args, 9);
1025 }
1026 }
1027
1028 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1029 semantic_name = TGSI_SEMANTIC_GENERIC;
1030 goto handle_semantic;
1031 }
1032 }
1033
1034 if (depth_index >= 0 || stencil_index >= 0) {
1035 LLVMValueRef out_ptr;
1036 unsigned mask = 0;
1037
1038 /* Specify the target we are exporting */
1039 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1040
1041 if (depth_index >= 0) {
1042 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1043 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1044 mask |= 0x1;
1045
1046 if (stencil_index < 0) {
1047 args[6] =
1048 args[7] =
1049 args[8] = args[5];
1050 }
1051 }
1052
1053 if (stencil_index >= 0) {
1054 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1055 args[7] =
1056 args[8] =
1057 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1058 /* Only setting the stencil component bit (0x2) here
1059 * breaks some stencil piglit tests
1060 */
1061 mask |= 0x3;
1062
1063 if (depth_index < 0)
1064 args[5] = args[6];
1065 }
1066
1067 /* Specify which components to enable */
1068 args[0] = lp_build_const_int32(base->gallivm, mask);
1069
1070 args[1] =
1071 args[2] =
1072 args[4] = uint->zero;
1073
1074 if (last_args[0])
1075 lp_build_intrinsic(base->gallivm->builder,
1076 "llvm.SI.export",
1077 LLVMVoidTypeInContext(base->gallivm->context),
1078 args, 9);
1079 else
1080 memcpy(last_args, args, sizeof(args));
1081 }
1082
1083 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
1084 unsigned pos_idx = 0;
1085
1086 /* We need to add the position output manually if it's missing. */
1087 if (!pos_args[0][0]) {
1088 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1089 pos_args[0][1] = uint->zero; /* EXEC mask */
1090 pos_args[0][2] = uint->zero; /* last export? */
1091 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1092 pos_args[0][4] = uint->zero; /* COMPR flag */
1093 pos_args[0][5] = base->zero; /* X */
1094 pos_args[0][6] = base->zero; /* Y */
1095 pos_args[0][7] = base->zero; /* Z */
1096 pos_args[0][8] = base->one; /* W */
1097 }
1098
1099 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1100 if (shader->vs_out_misc_write) {
1101 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1102 shader->vs_out_point_size |
1103 (shader->vs_out_edgeflag << 1));
1104 pos_args[1][1] = uint->zero; /* EXEC mask */
1105 pos_args[1][2] = uint->zero; /* last export? */
1106 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1107 pos_args[1][4] = uint->zero; /* COMPR flag */
1108 pos_args[1][5] = base->zero; /* X */
1109 pos_args[1][6] = base->zero; /* Y */
1110 pos_args[1][7] = base->zero; /* Z */
1111 pos_args[1][8] = base->zero; /* W */
1112
1113 if (shader->vs_out_point_size) {
1114 pos_args[1][5] = LLVMBuildLoad(base->gallivm->builder,
1115 si_shader_ctx->radeon_bld.soa.outputs[psize_index][0], "");
1116 }
1117
1118 if (shader->vs_out_edgeflag) {
1119 LLVMValueRef output = LLVMBuildLoad(base->gallivm->builder,
1120 si_shader_ctx->radeon_bld.soa.outputs[edgeflag_index][0], "");
1121
1122 /* The output is a float, but the hw expects an integer
1123 * with the first bit containing the edge flag. */
1124 output = LLVMBuildFPToUI(base->gallivm->builder, output,
1125 bld_base->uint_bld.elem_type, "");
1126
1127 output = lp_build_min(&bld_base->int_bld, output, bld_base->int_bld.one);
1128
1129 /* The LLVM intrinsic expects a float. */
1130 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder, output,
1131 base->elem_type, "");
1132 }
1133 }
1134
1135 for (i = 0; i < 4; i++)
1136 if (pos_args[i][0])
1137 shader->nr_pos_exports++;
1138
1139 for (i = 0; i < 4; i++) {
1140 if (!pos_args[i][0])
1141 continue;
1142
1143 /* Specify the target we are exporting */
1144 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1145
1146 if (pos_idx == shader->nr_pos_exports)
1147 /* Specify that this is the last export */
1148 pos_args[i][2] = uint->one;
1149
1150 lp_build_intrinsic(base->gallivm->builder,
1151 "llvm.SI.export",
1152 LLVMVoidTypeInContext(base->gallivm->context),
1153 pos_args[i], 9);
1154 }
1155 } else {
1156 if (!last_args[0]) {
1157 /* Specify which components to enable */
1158 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1159
1160 /* Specify the target we are exporting */
1161 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1162
1163 /* Set COMPR flag to zero to export data as 32-bit */
1164 last_args[4] = uint->zero;
1165
1166 /* dummy bits */
1167 last_args[5]= uint->zero;
1168 last_args[6]= uint->zero;
1169 last_args[7]= uint->zero;
1170 last_args[8]= uint->zero;
1171
1172 si_shader_ctx->shader->spi_shader_col_format |=
1173 V_028714_SPI_SHADER_32_ABGR;
1174 si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
1175 }
1176
1177 /* Specify whether the EXEC mask represents the valid mask */
1178 last_args[1] = uint->one;
1179
1180 if (shader->fs_write_all && shader->nr_cbufs > 1) {
1181 int i;
1182
1183 /* Specify that this is not yet the last export */
1184 last_args[2] = lp_build_const_int32(base->gallivm, 0);
1185
1186 for (i = 1; i < shader->nr_cbufs; i++) {
1187 /* Specify the target we are exporting */
1188 last_args[3] = lp_build_const_int32(base->gallivm,
1189 V_008DFC_SQ_EXP_MRT + i);
1190
1191 lp_build_intrinsic(base->gallivm->builder,
1192 "llvm.SI.export",
1193 LLVMVoidTypeInContext(base->gallivm->context),
1194 last_args, 9);
1195
1196 si_shader_ctx->shader->spi_shader_col_format |=
1197 si_shader_ctx->shader->spi_shader_col_format << 4;
1198 si_shader_ctx->shader->cb_shader_mask |=
1199 si_shader_ctx->shader->cb_shader_mask << 4;
1200 }
1201
1202 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1203 }
1204
1205 /* Specify that this is the last export */
1206 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1207
1208 lp_build_intrinsic(base->gallivm->builder,
1209 "llvm.SI.export",
1210 LLVMVoidTypeInContext(base->gallivm->context),
1211 last_args, 9);
1212 }
1213 /* XXX: Look up what this function does */
1214 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
1215 }
1216
1217 static const struct lp_build_tgsi_action txf_action;
1218
1219 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1220 struct lp_build_tgsi_context * bld_base,
1221 struct lp_build_emit_data * emit_data);
1222
1223 static void tex_fetch_args(
1224 struct lp_build_tgsi_context * bld_base,
1225 struct lp_build_emit_data * emit_data)
1226 {
1227 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1228 struct gallivm_state *gallivm = bld_base->base.gallivm;
1229 const struct tgsi_full_instruction * inst = emit_data->inst;
1230 unsigned opcode = inst->Instruction.Opcode;
1231 unsigned target = inst->Texture.Texture;
1232 LLVMValueRef coords[4];
1233 LLVMValueRef address[16];
1234 int ref_pos;
1235 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1236 unsigned count = 0;
1237 unsigned chan;
1238 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1239 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1240
1241 if (target == TGSI_TEXTURE_BUFFER) {
1242 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1243 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1244 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1245 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1246
1247 /* Truncate v32i8 to v16i8. */
1248 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1249 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1250 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1251 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1252
1253 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1254 emit_data->args[0] = res;
1255 emit_data->args[1] = bld_base->uint_bld.zero;
1256 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1257 emit_data->arg_count = 3;
1258 return;
1259 }
1260
1261 /* Fetch and project texture coordinates */
1262 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1263 for (chan = 0; chan < 3; chan++ ) {
1264 coords[chan] = lp_build_emit_fetch(bld_base,
1265 emit_data->inst, 0,
1266 chan);
1267 if (opcode == TGSI_OPCODE_TXP)
1268 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1269 TGSI_OPCODE_DIV,
1270 coords[chan],
1271 coords[3]);
1272 }
1273
1274 if (opcode == TGSI_OPCODE_TXP)
1275 coords[3] = bld_base->base.one;
1276
1277 /* Pack LOD bias value */
1278 if (opcode == TGSI_OPCODE_TXB)
1279 address[count++] = coords[3];
1280
1281 if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
1282 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1283
1284 /* Pack depth comparison value */
1285 switch (target) {
1286 case TGSI_TEXTURE_SHADOW1D:
1287 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1288 case TGSI_TEXTURE_SHADOW2D:
1289 case TGSI_TEXTURE_SHADOWRECT:
1290 case TGSI_TEXTURE_SHADOWCUBE:
1291 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1292 assert(ref_pos >= 0);
1293 address[count++] = coords[ref_pos];
1294 break;
1295 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1296 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1297 }
1298
1299 /* Pack user derivatives */
1300 if (opcode == TGSI_OPCODE_TXD) {
1301 for (chan = 0; chan < 2; chan++) {
1302 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, chan);
1303 if (num_coords > 1)
1304 address[count++] = lp_build_emit_fetch(bld_base, inst, 2, chan);
1305 }
1306 }
1307
1308 /* Pack texture coordinates */
1309 address[count++] = coords[0];
1310 if (num_coords > 1)
1311 address[count++] = coords[1];
1312 if (num_coords > 2)
1313 address[count++] = coords[2];
1314
1315 /* Pack LOD or sample index */
1316 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1317 address[count++] = coords[3];
1318
1319 if (count > 16) {
1320 assert(!"Cannot handle more than 16 texture address parameters");
1321 count = 16;
1322 }
1323
1324 for (chan = 0; chan < count; chan++ ) {
1325 address[chan] = LLVMBuildBitCast(gallivm->builder,
1326 address[chan],
1327 LLVMInt32TypeInContext(gallivm->context),
1328 "");
1329 }
1330
1331 /* Adjust the sample index according to FMASK.
1332 *
1333 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1334 * which is the identity mapping. Each nibble says which physical sample
1335 * should be fetched to get that sample.
1336 *
1337 * For example, 0x11111100 means there are only 2 samples stored and
1338 * the second sample covers 3/4 of the pixel. When reading samples 0
1339 * and 1, return physical sample 0 (determined by the first two 0s
1340 * in FMASK), otherwise return physical sample 1.
1341 *
1342 * The sample index should be adjusted as follows:
1343 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1344 */
1345 if (target == TGSI_TEXTURE_2D_MSAA ||
1346 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1347 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1348 struct lp_build_emit_data txf_emit_data = *emit_data;
1349 LLVMValueRef txf_address[4];
1350 unsigned txf_count = count;
1351
1352 memcpy(txf_address, address, sizeof(txf_address));
1353
1354 if (target == TGSI_TEXTURE_2D_MSAA) {
1355 txf_address[2] = bld_base->uint_bld.zero;
1356 }
1357 txf_address[3] = bld_base->uint_bld.zero;
1358
1359 /* Pad to a power-of-two size. */
1360 while (txf_count < util_next_power_of_two(txf_count))
1361 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1362
1363 /* Read FMASK using TXF. */
1364 txf_emit_data.chan = 0;
1365 txf_emit_data.dst_type = LLVMVectorType(
1366 LLVMInt32TypeInContext(bld_base->base.gallivm->context), 4);
1367 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1368 txf_emit_data.args[1] = si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index];
1369 txf_emit_data.args[2] = lp_build_const_int32(bld_base->base.gallivm,
1370 target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY);
1371 txf_emit_data.arg_count = 3;
1372
1373 build_tex_intrinsic(&txf_action, bld_base, &txf_emit_data);
1374
1375 /* Initialize some constants. */
1376 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1377 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1378
1379 /* Apply the formula. */
1380 LLVMValueRef fmask =
1381 LLVMBuildExtractElement(gallivm->builder,
1382 txf_emit_data.output[0],
1383 uint_bld->zero, "");
1384
1385 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1386
1387 LLVMValueRef sample_index4 =
1388 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1389
1390 LLVMValueRef shifted_fmask =
1391 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1392
1393 LLVMValueRef final_sample =
1394 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1395
1396 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1397 * resource descriptor is 0 (invalid),
1398 */
1399 LLVMValueRef fmask_desc =
1400 LLVMBuildBitCast(gallivm->builder,
1401 si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index],
1402 LLVMVectorType(uint_bld->elem_type, 8), "");
1403
1404 LLVMValueRef fmask_word1 =
1405 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1406 uint_bld->one, "");
1407
1408 LLVMValueRef word1_is_nonzero =
1409 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1410 fmask_word1, uint_bld->zero, "");
1411
1412 /* Replace the MSAA sample index. */
1413 address[sample_chan] =
1414 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1415 final_sample, address[sample_chan], "");
1416 }
1417
1418 /* Resource */
1419 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1420
1421 if (opcode == TGSI_OPCODE_TXF) {
1422 /* add tex offsets */
1423 if (inst->Texture.NumOffsets) {
1424 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1425 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1426 const struct tgsi_texture_offset * off = inst->TexOffsets;
1427
1428 assert(inst->Texture.NumOffsets == 1);
1429
1430 switch (target) {
1431 case TGSI_TEXTURE_3D:
1432 address[2] = lp_build_add(uint_bld, address[2],
1433 bld->immediates[off->Index][off->SwizzleZ]);
1434 /* fall through */
1435 case TGSI_TEXTURE_2D:
1436 case TGSI_TEXTURE_SHADOW2D:
1437 case TGSI_TEXTURE_RECT:
1438 case TGSI_TEXTURE_SHADOWRECT:
1439 case TGSI_TEXTURE_2D_ARRAY:
1440 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1441 address[1] =
1442 lp_build_add(uint_bld, address[1],
1443 bld->immediates[off->Index][off->SwizzleY]);
1444 /* fall through */
1445 case TGSI_TEXTURE_1D:
1446 case TGSI_TEXTURE_SHADOW1D:
1447 case TGSI_TEXTURE_1D_ARRAY:
1448 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1449 address[0] =
1450 lp_build_add(uint_bld, address[0],
1451 bld->immediates[off->Index][off->SwizzleX]);
1452 break;
1453 /* texture offsets do not apply to other texture targets */
1454 }
1455 }
1456
1457 emit_data->dst_type = LLVMVectorType(
1458 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1459 4);
1460
1461 emit_data->arg_count = 3;
1462 } else {
1463 /* Sampler */
1464 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1465
1466 emit_data->dst_type = LLVMVectorType(
1467 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
1468 4);
1469
1470 emit_data->arg_count = 4;
1471 }
1472
1473 /* Dimensions */
1474 emit_data->args[emit_data->arg_count - 1] =
1475 lp_build_const_int32(bld_base->base.gallivm, target);
1476
1477 /* Pad to power of two vector */
1478 while (count < util_next_power_of_two(count))
1479 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1480
1481 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1482 }
1483
1484 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1485 struct lp_build_tgsi_context * bld_base,
1486 struct lp_build_emit_data * emit_data)
1487 {
1488 struct lp_build_context * base = &bld_base->base;
1489 char intr_name[127];
1490
1491 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1492 emit_data->output[emit_data->chan] = build_intrinsic(
1493 base->gallivm->builder,
1494 "llvm.SI.vs.load.input", emit_data->dst_type,
1495 emit_data->args, emit_data->arg_count,
1496 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1497 return;
1498 }
1499
1500 sprintf(intr_name, "%sv%ui32", action->intr_name,
1501 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1502
1503 emit_data->output[emit_data->chan] = build_intrinsic(
1504 base->gallivm->builder, intr_name, emit_data->dst_type,
1505 emit_data->args, emit_data->arg_count,
1506 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1507 }
1508
1509 static void txq_fetch_args(
1510 struct lp_build_tgsi_context * bld_base,
1511 struct lp_build_emit_data * emit_data)
1512 {
1513 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1514 const struct tgsi_full_instruction *inst = emit_data->inst;
1515 struct gallivm_state *gallivm = bld_base->base.gallivm;
1516
1517 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1518 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1519 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
1520
1521 /* Read the size from the buffer descriptor directly. */
1522 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
1523 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
1524 size = LLVMBuildExtractElement(gallivm->builder, size,
1525 lp_build_const_int32(gallivm, 2), "");
1526 emit_data->args[0] = size;
1527 return;
1528 }
1529
1530 /* Mip level */
1531 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1532
1533 /* Resource */
1534 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
1535
1536 /* Dimensions */
1537 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
1538 inst->Texture.Texture);
1539
1540 emit_data->arg_count = 3;
1541
1542 emit_data->dst_type = LLVMVectorType(
1543 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1544 4);
1545 }
1546
1547 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
1548 struct lp_build_tgsi_context * bld_base,
1549 struct lp_build_emit_data * emit_data)
1550 {
1551 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1552 /* Just return the buffer size. */
1553 emit_data->output[emit_data->chan] = emit_data->args[0];
1554 return;
1555 }
1556
1557 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
1558 }
1559
1560 #if HAVE_LLVM >= 0x0304
1561
1562 static void si_llvm_emit_ddxy(
1563 const struct lp_build_tgsi_action * action,
1564 struct lp_build_tgsi_context * bld_base,
1565 struct lp_build_emit_data * emit_data)
1566 {
1567 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1568 struct gallivm_state *gallivm = bld_base->base.gallivm;
1569 struct lp_build_context * base = &bld_base->base;
1570 const struct tgsi_full_instruction *inst = emit_data->inst;
1571 unsigned opcode = inst->Instruction.Opcode;
1572 LLVMValueRef indices[2];
1573 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1574 LLVMValueRef tl, trbl, result[4];
1575 LLVMTypeRef i32;
1576 unsigned swizzle[4];
1577 unsigned c;
1578
1579 i32 = LLVMInt32TypeInContext(gallivm->context);
1580
1581 indices[0] = bld_base->uint_bld.zero;
1582 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
1583 NULL, 0, LLVMReadNoneAttribute);
1584 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1585 indices, 2, "");
1586
1587 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
1588 lp_build_const_int32(gallivm, 0xfffffffc), "");
1589 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1590 indices, 2, "");
1591
1592 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
1593 lp_build_const_int32(gallivm,
1594 opcode == TGSI_OPCODE_DDX ? 1 : 2),
1595 "");
1596 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1597 indices, 2, "");
1598
1599 for (c = 0; c < 4; ++c) {
1600 unsigned i;
1601
1602 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
1603 for (i = 0; i < c; ++i) {
1604 if (swizzle[i] == swizzle[c]) {
1605 result[c] = result[i];
1606 break;
1607 }
1608 }
1609 if (i != c)
1610 continue;
1611
1612 LLVMBuildStore(gallivm->builder,
1613 LLVMBuildBitCast(gallivm->builder,
1614 lp_build_emit_fetch(bld_base, inst, 0, c),
1615 i32, ""),
1616 store_ptr);
1617
1618 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
1619 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
1620
1621 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
1622 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
1623
1624 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
1625 }
1626
1627 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
1628 }
1629
1630 #endif /* HAVE_LLVM >= 0x0304 */
1631
1632 static const struct lp_build_tgsi_action tex_action = {
1633 .fetch_args = tex_fetch_args,
1634 .emit = build_tex_intrinsic,
1635 .intr_name = "llvm.SI.sample."
1636 };
1637
1638 static const struct lp_build_tgsi_action txb_action = {
1639 .fetch_args = tex_fetch_args,
1640 .emit = build_tex_intrinsic,
1641 .intr_name = "llvm.SI.sampleb."
1642 };
1643
1644 #if HAVE_LLVM >= 0x0304
1645 static const struct lp_build_tgsi_action txd_action = {
1646 .fetch_args = tex_fetch_args,
1647 .emit = build_tex_intrinsic,
1648 .intr_name = "llvm.SI.sampled."
1649 };
1650 #endif
1651
1652 static const struct lp_build_tgsi_action txf_action = {
1653 .fetch_args = tex_fetch_args,
1654 .emit = build_tex_intrinsic,
1655 .intr_name = "llvm.SI.imageload."
1656 };
1657
1658 static const struct lp_build_tgsi_action txl_action = {
1659 .fetch_args = tex_fetch_args,
1660 .emit = build_tex_intrinsic,
1661 .intr_name = "llvm.SI.samplel."
1662 };
1663
1664 static const struct lp_build_tgsi_action txq_action = {
1665 .fetch_args = txq_fetch_args,
1666 .emit = build_txq_intrinsic,
1667 .intr_name = "llvm.SI.resinfo"
1668 };
1669
1670 static void create_meta_data(struct si_shader_context *si_shader_ctx)
1671 {
1672 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
1673 LLVMValueRef args[3];
1674
1675 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
1676 args[1] = 0;
1677 args[2] = lp_build_const_int32(gallivm, 1);
1678
1679 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
1680 }
1681
1682 static void create_function(struct si_shader_context *si_shader_ctx)
1683 {
1684 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1685 struct gallivm_state *gallivm = bld_base->base.gallivm;
1686 LLVMTypeRef params[21], f32, i8, i32, v2i32, v3i32;
1687 unsigned i, last_sgpr, num_params;
1688
1689 i8 = LLVMInt8TypeInContext(gallivm->context);
1690 i32 = LLVMInt32TypeInContext(gallivm->context);
1691 f32 = LLVMFloatTypeInContext(gallivm->context);
1692 v2i32 = LLVMVectorType(i32, 2);
1693 v3i32 = LLVMVectorType(i32, 3);
1694
1695 params[SI_PARAM_CONST] = LLVMPointerType(
1696 LLVMArrayType(LLVMVectorType(i8, 16), NUM_CONST_BUFFERS), CONST_ADDR_SPACE);
1697 /* We assume at most 16 textures per program at the moment.
1698 * This need probably need to be changed to support bindless textures */
1699 params[SI_PARAM_SAMPLER] = LLVMPointerType(
1700 LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS), CONST_ADDR_SPACE);
1701 params[SI_PARAM_RESOURCE] = LLVMPointerType(
1702 LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES), CONST_ADDR_SPACE);
1703
1704 switch (si_shader_ctx->type) {
1705 case TGSI_PROCESSOR_VERTEX:
1706 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_CONST];
1707 params[SI_PARAM_SO_BUFFER] = params[SI_PARAM_CONST];
1708 params[SI_PARAM_START_INSTANCE] = i32;
1709 num_params = SI_PARAM_START_INSTANCE+1;
1710
1711 /* The locations of the other parameters are assigned dynamically. */
1712
1713 /* Streamout SGPRs. */
1714 if (si_shader_ctx->shader->selector->so.num_outputs) {
1715 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
1716 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
1717 }
1718 /* A streamout buffer offset is loaded if the stride is non-zero. */
1719 for (i = 0; i < 4; i++) {
1720 if (!si_shader_ctx->shader->selector->so.stride[i])
1721 continue;
1722
1723 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
1724 }
1725
1726 last_sgpr = num_params-1;
1727
1728 /* VGPRs */
1729 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
1730 params[num_params++] = i32; /* unused*/
1731 params[num_params++] = i32; /* unused */
1732 params[si_shader_ctx->param_instance_id = num_params++] = i32;
1733 break;
1734
1735 case TGSI_PROCESSOR_FRAGMENT:
1736 params[SI_PARAM_ALPHA_REF] = f32;
1737 params[SI_PARAM_PRIM_MASK] = i32;
1738 last_sgpr = SI_PARAM_PRIM_MASK;
1739 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
1740 params[SI_PARAM_PERSP_CENTER] = v2i32;
1741 params[SI_PARAM_PERSP_CENTROID] = v2i32;
1742 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
1743 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
1744 params[SI_PARAM_LINEAR_CENTER] = v2i32;
1745 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
1746 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
1747 params[SI_PARAM_POS_X_FLOAT] = f32;
1748 params[SI_PARAM_POS_Y_FLOAT] = f32;
1749 params[SI_PARAM_POS_Z_FLOAT] = f32;
1750 params[SI_PARAM_POS_W_FLOAT] = f32;
1751 params[SI_PARAM_FRONT_FACE] = f32;
1752 params[SI_PARAM_ANCILLARY] = f32;
1753 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
1754 params[SI_PARAM_POS_FIXED_PT] = f32;
1755 num_params = SI_PARAM_POS_FIXED_PT+1;
1756 break;
1757
1758 default:
1759 assert(0 && "unimplemented shader");
1760 return;
1761 }
1762
1763 assert(num_params <= Elements(params));
1764 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
1765 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
1766
1767 for (i = 0; i <= last_sgpr; ++i) {
1768 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
1769 switch (i) {
1770 default:
1771 LLVMAddAttribute(P, LLVMInRegAttribute);
1772 break;
1773 #if HAVE_LLVM >= 0x0304
1774 /* We tell llvm that array inputs are passed by value to allow Sinking pass
1775 * to move load. Inputs are constant so this is fine. */
1776 case SI_PARAM_CONST:
1777 case SI_PARAM_SAMPLER:
1778 case SI_PARAM_RESOURCE:
1779 LLVMAddAttribute(P, LLVMByValAttribute);
1780 break;
1781 #endif
1782 }
1783 }
1784
1785 #if HAVE_LLVM >= 0x0304
1786 if (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
1787 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0)
1788 si_shader_ctx->ddxy_lds =
1789 LLVMAddGlobalInAddressSpace(gallivm->module,
1790 LLVMArrayType(i32, 64),
1791 "ddxy_lds",
1792 LOCAL_ADDR_SPACE);
1793 #endif
1794 }
1795
1796 static void preload_constants(struct si_shader_context *si_shader_ctx)
1797 {
1798 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1799 struct gallivm_state * gallivm = bld_base->base.gallivm;
1800 const struct tgsi_shader_info * info = bld_base->info;
1801 unsigned buf;
1802 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1803
1804 for (buf = 0; buf < NUM_CONST_BUFFERS; buf++) {
1805 unsigned i, num_const = info->const_file_max[buf] + 1;
1806
1807 if (num_const == 0)
1808 continue;
1809
1810 /* Allocate space for the constant values */
1811 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
1812
1813 /* Load the resource descriptor */
1814 si_shader_ctx->const_resource[buf] =
1815 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
1816
1817 /* Load the constants, we rely on the code sinking to do the rest */
1818 for (i = 0; i < num_const * 4; ++i) {
1819 LLVMValueRef args[2] = {
1820 si_shader_ctx->const_resource[buf],
1821 lp_build_const_int32(gallivm, i * 4)
1822 };
1823 si_shader_ctx->constants[buf][i] =
1824 build_intrinsic(gallivm->builder, "llvm.SI.load.const",
1825 bld_base->base.elem_type, args, 2,
1826 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1827 }
1828 }
1829 }
1830
1831 static void preload_samplers(struct si_shader_context *si_shader_ctx)
1832 {
1833 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1834 struct gallivm_state * gallivm = bld_base->base.gallivm;
1835 const struct tgsi_shader_info * info = bld_base->info;
1836
1837 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
1838
1839 LLVMValueRef res_ptr, samp_ptr;
1840 LLVMValueRef offset;
1841
1842 if (num_samplers == 0)
1843 return;
1844
1845 /* Allocate space for the values */
1846 si_shader_ctx->resources = CALLOC(NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
1847 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
1848
1849 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
1850 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
1851
1852 /* Load the resources and samplers, we rely on the code sinking to do the rest */
1853 for (i = 0; i < num_samplers; ++i) {
1854 /* Resource */
1855 offset = lp_build_const_int32(gallivm, i);
1856 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
1857
1858 /* Sampler */
1859 offset = lp_build_const_int32(gallivm, i);
1860 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
1861
1862 /* FMASK resource */
1863 if (info->is_msaa_sampler[i]) {
1864 offset = lp_build_const_int32(gallivm, FMASK_TEX_OFFSET + i);
1865 si_shader_ctx->resources[FMASK_TEX_OFFSET + i] =
1866 build_indexed_load(si_shader_ctx, res_ptr, offset);
1867 }
1868 }
1869 }
1870
1871 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
1872 {
1873 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1874 struct gallivm_state * gallivm = bld_base->base.gallivm;
1875 unsigned i;
1876
1877 if (!si_shader_ctx->shader->selector->so.num_outputs)
1878 return;
1879
1880 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1881 SI_PARAM_SO_BUFFER);
1882
1883 /* Load the resources, we rely on the code sinking to do the rest */
1884 for (i = 0; i < 4; ++i) {
1885 if (si_shader_ctx->shader->selector->so.stride[i]) {
1886 LLVMValueRef offset = lp_build_const_int32(gallivm, i);
1887
1888 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
1889 }
1890 }
1891 }
1892
1893 int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader,
1894 LLVMModuleRef mod)
1895 {
1896 unsigned i;
1897 uint32_t *ptr;
1898 struct radeon_llvm_binary binary;
1899 bool dump = r600_can_dump_shader(&rctx->screen->b,
1900 shader->selector ? shader->selector->tokens : NULL);
1901 memset(&binary, 0, sizeof(binary));
1902 radeon_llvm_compile(mod, &binary,
1903 r600_get_llvm_processor_name(rctx->screen->b.family), dump);
1904 if (dump && ! binary.disassembled) {
1905 fprintf(stderr, "SI CODE:\n");
1906 for (i = 0; i < binary.code_size; i+=4 ) {
1907 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
1908 binary.code[i + 2], binary.code[i + 1],
1909 binary.code[i]);
1910 }
1911 }
1912
1913 /* XXX: We may be able to emit some of these values directly rather than
1914 * extracting fields to be emitted later.
1915 */
1916 for (i = 0; i < binary.config_size; i+= 8) {
1917 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
1918 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
1919 switch (reg) {
1920 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
1921 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
1922 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
1923 case R_00B848_COMPUTE_PGM_RSRC1:
1924 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
1925 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
1926 break;
1927 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
1928 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
1929 break;
1930 case R_00B84C_COMPUTE_PGM_RSRC2:
1931 shader->lds_size = G_00B84C_LDS_SIZE(value);
1932 break;
1933 case R_0286CC_SPI_PS_INPUT_ENA:
1934 shader->spi_ps_input_ena = value;
1935 break;
1936 default:
1937 fprintf(stderr, "Warning: Compiler emitted unknown "
1938 "config register: 0x%x\n", reg);
1939 break;
1940 }
1941 }
1942
1943 /* copy new shader */
1944 r600_resource_reference(&shader->bo, NULL);
1945 shader->bo = r600_resource_create_custom(rctx->b.b.screen, PIPE_USAGE_IMMUTABLE,
1946 binary.code_size);
1947 if (shader->bo == NULL) {
1948 return -ENOMEM;
1949 }
1950
1951 ptr = (uint32_t*)rctx->b.ws->buffer_map(shader->bo->cs_buf, rctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
1952 if (0 /*R600_BIG_ENDIAN*/) {
1953 for (i = 0; i < binary.code_size / 4; ++i) {
1954 ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
1955 }
1956 } else {
1957 memcpy(ptr, binary.code, binary.code_size);
1958 }
1959 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
1960
1961 free(binary.code);
1962 free(binary.config);
1963
1964 return 0;
1965 }
1966
1967 int si_pipe_shader_create(
1968 struct pipe_context *ctx,
1969 struct si_pipe_shader *shader)
1970 {
1971 struct r600_context *rctx = (struct r600_context*)ctx;
1972 struct si_pipe_shader_selector *sel = shader->selector;
1973 struct si_shader_context si_shader_ctx;
1974 struct tgsi_shader_info shader_info;
1975 struct lp_build_tgsi_context * bld_base;
1976 LLVMModuleRef mod;
1977 int r = 0;
1978 bool dump = r600_can_dump_shader(&rctx->screen->b, shader->selector->tokens);
1979
1980 assert(shader->shader.noutput == 0);
1981 assert(shader->shader.ninterp == 0);
1982 assert(shader->shader.ninput == 0);
1983
1984 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
1985 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
1986 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
1987
1988 tgsi_scan_shader(sel->tokens, &shader_info);
1989
1990 shader->shader.uses_kill = shader_info.uses_kill;
1991 shader->shader.uses_instanceid = shader_info.uses_instanceid;
1992 bld_base->info = &shader_info;
1993 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
1994 bld_base->emit_epilogue = si_llvm_emit_epilogue;
1995
1996 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1997 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
1998 #if HAVE_LLVM >= 0x0304
1999 bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
2000 #endif
2001 bld_base->op_actions[TGSI_OPCODE_TXF] = txf_action;
2002 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
2003 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2004 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2005
2006 #if HAVE_LLVM >= 0x0304
2007 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2008 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2009 #endif
2010
2011 si_shader_ctx.radeon_bld.load_input = declare_input;
2012 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2013 si_shader_ctx.tokens = sel->tokens;
2014 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2015 si_shader_ctx.shader = shader;
2016 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2017
2018 create_meta_data(&si_shader_ctx);
2019 create_function(&si_shader_ctx);
2020 preload_constants(&si_shader_ctx);
2021 preload_samplers(&si_shader_ctx);
2022 preload_streamout_buffers(&si_shader_ctx);
2023
2024 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
2025
2026 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2027 * conversion fails. */
2028 if (dump) {
2029 tgsi_dump(sel->tokens, 0);
2030 si_dump_streamout(&sel->so);
2031 }
2032
2033 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2034 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2035 for (int i = 0; i < NUM_CONST_BUFFERS; i++)
2036 FREE(si_shader_ctx.constants[i]);
2037 FREE(si_shader_ctx.resources);
2038 FREE(si_shader_ctx.samplers);
2039 return -EINVAL;
2040 }
2041
2042 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2043
2044 mod = bld_base->base.gallivm->module;
2045 r = si_compile_llvm(rctx, shader, mod);
2046
2047 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2048 tgsi_parse_free(&si_shader_ctx.parse);
2049
2050 for (int i = 0; i < NUM_CONST_BUFFERS; i++)
2051 FREE(si_shader_ctx.constants[i]);
2052 FREE(si_shader_ctx.resources);
2053 FREE(si_shader_ctx.samplers);
2054
2055 return r;
2056 }
2057
2058 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
2059 {
2060 r600_resource_reference(&shader->bo, NULL);
2061 }