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radeonsi: remove wqm intrinsic
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "gallivm/lp_bld_arit.h"
37 #include "radeon_llvm.h"
38 #include "radeon_llvm_emit.h"
39 #include "tgsi/tgsi_info.h"
40 #include "tgsi/tgsi_parse.h"
41 #include "tgsi/tgsi_scan.h"
42 #include "tgsi/tgsi_dump.h"
43
44 #include "radeonsi_pipe.h"
45 #include "radeonsi_shader.h"
46 #include "si_state.h"
47 #include "sid.h"
48
49 #include <assert.h>
50 #include <errno.h>
51 #include <stdio.h>
52
53 struct si_shader_context
54 {
55 struct radeon_llvm_context radeon_bld;
56 struct r600_context *rctx;
57 struct tgsi_parse_context parse;
58 struct tgsi_token * tokens;
59 struct si_pipe_shader *shader;
60 struct si_shader_key key;
61 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
62 /* struct list_head inputs; */
63 /* unsigned * input_mappings *//* From TGSI to SI hw */
64 /* struct tgsi_shader_info info;*/
65 };
66
67 static struct si_shader_context * si_shader_context(
68 struct lp_build_tgsi_context * bld_base)
69 {
70 return (struct si_shader_context *)bld_base;
71 }
72
73
74 #define PERSPECTIVE_BASE 0
75 #define LINEAR_BASE 9
76
77 #define SAMPLE_OFFSET 0
78 #define CENTER_OFFSET 2
79 #define CENTROID_OFSET 4
80
81 #define USE_SGPR_MAX_SUFFIX_LEN 5
82 #define CONST_ADDR_SPACE 2
83 #define USER_SGPR_ADDR_SPACE 8
84
85 /**
86 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
87 *
88 * @param offset The offset parameter specifies the number of
89 * elements to offset, not the number of bytes or dwords. An element is the
90 * the type pointed to by the base_ptr parameter (e.g. int is the element of
91 * an int* pointer)
92 *
93 * When LLVM lowers the load instruction, it will convert the element offset
94 * into a dword offset automatically.
95 *
96 */
97 static LLVMValueRef build_indexed_load(
98 struct gallivm_state * gallivm,
99 LLVMValueRef base_ptr,
100 LLVMValueRef offset)
101 {
102 LLVMValueRef computed_ptr = LLVMBuildGEP(
103 gallivm->builder, base_ptr, &offset, 1, "");
104
105 return LLVMBuildLoad(gallivm->builder, computed_ptr, "");
106 }
107
108 static void declare_input_vs(
109 struct si_shader_context * si_shader_ctx,
110 unsigned input_index,
111 const struct tgsi_full_declaration *decl)
112 {
113 LLVMValueRef t_list_ptr;
114 LLVMValueRef t_offset;
115 LLVMValueRef t_list;
116 LLVMValueRef attribute_offset;
117 LLVMValueRef buffer_index_reg;
118 LLVMValueRef args[3];
119 LLVMTypeRef vec4_type;
120 LLVMValueRef input;
121 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
122 //struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[input_index];
123 unsigned chan;
124
125 /* Load the T list */
126 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
127
128 t_offset = lp_build_const_int32(base->gallivm, input_index);
129
130 t_list = build_indexed_load(base->gallivm, t_list_ptr, t_offset);
131
132 /* Build the attribute offset */
133 attribute_offset = lp_build_const_int32(base->gallivm, 0);
134
135 /* Load the buffer index, which is always stored in VGPR0
136 * for Vertex Shaders */
137 buffer_index_reg = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_INDEX);
138
139 vec4_type = LLVMVectorType(base->elem_type, 4);
140 args[0] = t_list;
141 args[1] = attribute_offset;
142 args[2] = buffer_index_reg;
143 input = lp_build_intrinsic(base->gallivm->builder,
144 "llvm.SI.vs.load.input", vec4_type, args, 3);
145
146 /* Break up the vec4 into individual components */
147 for (chan = 0; chan < 4; chan++) {
148 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
149 /* XXX: Use a helper function for this. There is one in
150 * tgsi_llvm.c. */
151 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
152 LLVMBuildExtractElement(base->gallivm->builder,
153 input, llvm_chan, "");
154 }
155 }
156
157 static void declare_input_fs(
158 struct si_shader_context * si_shader_ctx,
159 unsigned input_index,
160 const struct tgsi_full_declaration *decl)
161 {
162 struct si_shader *shader = &si_shader_ctx->shader->shader;
163 struct lp_build_context * base =
164 &si_shader_ctx->radeon_bld.soa.bld_base.base;
165 struct gallivm_state * gallivm = base->gallivm;
166 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
167 LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
168
169 LLVMValueRef interp_param;
170 const char * intr_name;
171
172 /* This value is:
173 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
174 * quad begins a new primitive. Bit 0 always needs
175 * to be unset)
176 * [32:16] ParamOffset
177 *
178 */
179 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
180 LLVMValueRef attr_number;
181
182 unsigned chan;
183
184 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
185 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
186 unsigned soa_index =
187 radeon_llvm_reg_index_soa(input_index, chan);
188 si_shader_ctx->radeon_bld.inputs[soa_index] =
189 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
190
191 if (chan == 3)
192 /* RCP for fragcoord.w */
193 si_shader_ctx->radeon_bld.inputs[soa_index] =
194 LLVMBuildFDiv(gallivm->builder,
195 lp_build_const_float(gallivm, 1.0f),
196 si_shader_ctx->radeon_bld.inputs[soa_index],
197 "");
198 }
199 return;
200 }
201
202 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
203 LLVMValueRef face, is_face_positive;
204
205 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
206
207 is_face_positive = LLVMBuildFCmp(gallivm->builder,
208 LLVMRealUGT, face,
209 lp_build_const_float(gallivm, 0.0f),
210 "");
211
212 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
213 LLVMBuildSelect(gallivm->builder,
214 is_face_positive,
215 lp_build_const_float(gallivm, 1.0f),
216 lp_build_const_float(gallivm, 0.0f),
217 "");
218 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
219 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
220 lp_build_const_float(gallivm, 0.0f);
221 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
222 lp_build_const_float(gallivm, 1.0f);
223
224 return;
225 }
226
227 shader->input[input_index].param_offset = shader->ninterp++;
228 attr_number = lp_build_const_int32(gallivm,
229 shader->input[input_index].param_offset);
230
231 /* XXX: Handle all possible interpolation modes */
232 switch (decl->Interp.Interpolate) {
233 case TGSI_INTERPOLATE_COLOR:
234 if (si_shader_ctx->key.flatshade) {
235 interp_param = 0;
236 } else {
237 if (decl->Interp.Centroid)
238 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
239 else
240 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
241 }
242 break;
243 case TGSI_INTERPOLATE_CONSTANT:
244 interp_param = 0;
245 break;
246 case TGSI_INTERPOLATE_LINEAR:
247 if (decl->Interp.Centroid)
248 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
249 else
250 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
251 break;
252 case TGSI_INTERPOLATE_PERSPECTIVE:
253 if (decl->Interp.Centroid)
254 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
255 else
256 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
257 break;
258 default:
259 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
260 return;
261 }
262
263 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
264
265 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
266 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
267 si_shader_ctx->key.color_two_side) {
268 LLVMValueRef args[4];
269 LLVMValueRef face, is_face_positive;
270 LLVMValueRef back_attr_number =
271 lp_build_const_int32(gallivm,
272 shader->input[input_index].param_offset + 1);
273
274 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
275
276 is_face_positive = LLVMBuildFCmp(gallivm->builder,
277 LLVMRealUGT, face,
278 lp_build_const_float(gallivm, 0.0f),
279 "");
280
281 args[2] = params;
282 args[3] = interp_param;
283 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
284 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
285 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
286 LLVMValueRef front, back;
287
288 args[0] = llvm_chan;
289 args[1] = attr_number;
290 front = build_intrinsic(base->gallivm->builder, intr_name,
291 input_type, args, args[3] ? 4 : 3,
292 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
293
294 args[1] = back_attr_number;
295 back = build_intrinsic(base->gallivm->builder, intr_name,
296 input_type, args, args[3] ? 4 : 3,
297 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
298
299 si_shader_ctx->radeon_bld.inputs[soa_index] =
300 LLVMBuildSelect(gallivm->builder,
301 is_face_positive,
302 front,
303 back,
304 "");
305 }
306
307 shader->ninterp++;
308 } else {
309 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
310 LLVMValueRef args[4];
311 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
312 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
313 args[0] = llvm_chan;
314 args[1] = attr_number;
315 args[2] = params;
316 args[3] = interp_param;
317 si_shader_ctx->radeon_bld.inputs[soa_index] =
318 build_intrinsic(base->gallivm->builder, intr_name,
319 input_type, args, args[3] ? 4 : 3,
320 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
321 }
322 }
323 }
324
325 static void declare_input(
326 struct radeon_llvm_context * radeon_bld,
327 unsigned input_index,
328 const struct tgsi_full_declaration *decl)
329 {
330 struct si_shader_context * si_shader_ctx =
331 si_shader_context(&radeon_bld->soa.bld_base);
332 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
333 declare_input_vs(si_shader_ctx, input_index, decl);
334 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
335 declare_input_fs(si_shader_ctx, input_index, decl);
336 } else {
337 fprintf(stderr, "Warning: Unsupported shader type,\n");
338 }
339 }
340
341 static LLVMValueRef fetch_constant(
342 struct lp_build_tgsi_context * bld_base,
343 const struct tgsi_full_src_register *reg,
344 enum tgsi_opcode_type type,
345 unsigned swizzle)
346 {
347 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
348 struct lp_build_context * base = &bld_base->base;
349
350 LLVMValueRef ptr;
351 LLVMValueRef args[2];
352 LLVMValueRef result;
353
354 if (swizzle == LP_CHAN_ALL) {
355 unsigned chan;
356 LLVMValueRef values[4];
357 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
358 values[chan] = fetch_constant(bld_base, reg, type, chan);
359
360 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
361 }
362
363 /* Load the resource descriptor */
364 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
365 args[0] = build_indexed_load(base->gallivm, ptr, bld_base->uint_bld.zero);
366
367 args[1] = lp_build_const_int32(base->gallivm, (reg->Register.Index * 4 + swizzle) * 4);
368 if (reg->Register.Indirect) {
369 const struct tgsi_ind_register *ireg = &reg->Indirect;
370 LLVMValueRef addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
371 LLVMValueRef idx = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
372 idx = lp_build_mul_imm(&bld_base->uint_bld, idx, 16);
373 args[1] = lp_build_add(&bld_base->uint_bld, idx, args[1]);
374 }
375
376 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
377 args, 2, LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
378
379 return bitcast(bld_base, type, result);
380 }
381
382 /* Initialize arguments for the shader export intrinsic */
383 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
384 struct tgsi_full_declaration *d,
385 unsigned index,
386 unsigned target,
387 LLVMValueRef *args)
388 {
389 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
390 struct lp_build_context *uint =
391 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
392 struct lp_build_context *base = &bld_base->base;
393 unsigned compressed = 0;
394 unsigned chan;
395
396 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
397 int cbuf = target - V_008DFC_SQ_EXP_MRT;
398
399 if (cbuf >= 0 && cbuf < 8) {
400 compressed = (si_shader_ctx->key.export_16bpc >> cbuf) & 0x1;
401
402 if (compressed)
403 si_shader_ctx->shader->spi_shader_col_format |=
404 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
405 else
406 si_shader_ctx->shader->spi_shader_col_format |=
407 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
408 }
409 }
410
411 if (compressed) {
412 /* Pixel shader needs to pack output values before export */
413 for (chan = 0; chan < 2; chan++ ) {
414 LLVMValueRef *out_ptr =
415 si_shader_ctx->radeon_bld.soa.outputs[index];
416 args[0] = LLVMBuildLoad(base->gallivm->builder,
417 out_ptr[2 * chan], "");
418 args[1] = LLVMBuildLoad(base->gallivm->builder,
419 out_ptr[2 * chan + 1], "");
420 args[chan + 5] =
421 build_intrinsic(base->gallivm->builder,
422 "llvm.SI.packf16",
423 LLVMInt32TypeInContext(base->gallivm->context),
424 args, 2,
425 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
426 args[chan + 7] = args[chan + 5] =
427 LLVMBuildBitCast(base->gallivm->builder,
428 args[chan + 5],
429 LLVMFloatTypeInContext(base->gallivm->context),
430 "");
431 }
432
433 /* Set COMPR flag */
434 args[4] = uint->one;
435 } else {
436 for (chan = 0; chan < 4; chan++ ) {
437 LLVMValueRef out_ptr =
438 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
439 /* +5 because the first output value will be
440 * the 6th argument to the intrinsic. */
441 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
442 out_ptr, "");
443 }
444
445 /* Clear COMPR flag */
446 args[4] = uint->zero;
447 }
448
449 /* XXX: This controls which components of the output
450 * registers actually get exported. (e.g bit 0 means export
451 * X component, bit 1 means export Y component, etc.) I'm
452 * hard coding this to 0xf for now. In the future, we might
453 * want to do something else. */
454 args[0] = lp_build_const_int32(base->gallivm, 0xf);
455
456 /* Specify whether the EXEC mask represents the valid mask */
457 args[1] = uint->zero;
458
459 /* Specify whether this is the last export */
460 args[2] = uint->zero;
461
462 /* Specify the target we are exporting */
463 args[3] = lp_build_const_int32(base->gallivm, target);
464
465 /* XXX: We probably need to keep track of the output
466 * values, so we know what we are passing to the next
467 * stage. */
468 }
469
470 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
471 unsigned index)
472 {
473 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
474 struct gallivm_state *gallivm = bld_base->base.gallivm;
475
476 if (si_shader_ctx->key.alpha_func != PIPE_FUNC_NEVER) {
477 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
478 LLVMValueRef alpha_pass =
479 lp_build_cmp(&bld_base->base,
480 si_shader_ctx->key.alpha_func,
481 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
482 lp_build_const_float(gallivm, si_shader_ctx->key.alpha_ref));
483 LLVMValueRef arg =
484 lp_build_select(&bld_base->base,
485 alpha_pass,
486 lp_build_const_float(gallivm, 1.0f),
487 lp_build_const_float(gallivm, -1.0f));
488
489 build_intrinsic(gallivm->builder,
490 "llvm.AMDGPU.kill",
491 LLVMVoidTypeInContext(gallivm->context),
492 &arg, 1, 0);
493 } else {
494 build_intrinsic(gallivm->builder,
495 "llvm.AMDGPU.kilp",
496 LLVMVoidTypeInContext(gallivm->context),
497 NULL, 0, 0);
498 }
499 }
500
501 /* XXX: This is partially implemented for VS only at this point. It is not complete */
502 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
503 {
504 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
505 struct si_shader * shader = &si_shader_ctx->shader->shader;
506 struct lp_build_context * base = &bld_base->base;
507 struct lp_build_context * uint =
508 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
509 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
510 LLVMValueRef args[9];
511 LLVMValueRef last_args[9] = { 0 };
512 unsigned color_count = 0;
513 unsigned param_count = 0;
514 int depth_index = -1, stencil_index = -1;
515
516 while (!tgsi_parse_end_of_tokens(parse)) {
517 struct tgsi_full_declaration *d =
518 &parse->FullToken.FullDeclaration;
519 unsigned target;
520 unsigned index;
521 int i;
522
523 tgsi_parse_token(parse);
524
525 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
526 parse->FullToken.FullProperty.Property.PropertyName ==
527 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
528 shader->fs_write_all = TRUE;
529
530 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
531 continue;
532
533 switch (d->Declaration.File) {
534 case TGSI_FILE_INPUT:
535 i = shader->ninput++;
536 shader->input[i].name = d->Semantic.Name;
537 shader->input[i].sid = d->Semantic.Index;
538 shader->input[i].interpolate = d->Interp.Interpolate;
539 shader->input[i].centroid = d->Interp.Centroid;
540 continue;
541
542 case TGSI_FILE_OUTPUT:
543 i = shader->noutput++;
544 shader->output[i].name = d->Semantic.Name;
545 shader->output[i].sid = d->Semantic.Index;
546 shader->output[i].interpolate = d->Interp.Interpolate;
547 break;
548
549 default:
550 continue;
551 }
552
553 for (index = d->Range.First; index <= d->Range.Last; index++) {
554 /* Select the correct target */
555 switch(d->Semantic.Name) {
556 case TGSI_SEMANTIC_PSIZE:
557 target = V_008DFC_SQ_EXP_POS;
558 break;
559 case TGSI_SEMANTIC_POSITION:
560 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
561 target = V_008DFC_SQ_EXP_POS;
562 break;
563 } else {
564 depth_index = index;
565 continue;
566 }
567 case TGSI_SEMANTIC_STENCIL:
568 stencil_index = index;
569 continue;
570 case TGSI_SEMANTIC_COLOR:
571 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
572 case TGSI_SEMANTIC_BCOLOR:
573 target = V_008DFC_SQ_EXP_PARAM + param_count;
574 shader->output[i].param_offset = param_count;
575 param_count++;
576 } else {
577 target = V_008DFC_SQ_EXP_MRT + color_count;
578 if (color_count == 0 &&
579 si_shader_ctx->key.alpha_func != PIPE_FUNC_ALWAYS)
580 si_alpha_test(bld_base, index);
581
582 color_count++;
583 }
584 break;
585 case TGSI_SEMANTIC_FOG:
586 case TGSI_SEMANTIC_GENERIC:
587 target = V_008DFC_SQ_EXP_PARAM + param_count;
588 shader->output[i].param_offset = param_count;
589 param_count++;
590 break;
591 default:
592 target = 0;
593 fprintf(stderr,
594 "Warning: SI unhandled output type:%d\n",
595 d->Semantic.Name);
596 }
597
598 si_llvm_init_export_args(bld_base, d, index, target, args);
599
600 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
601 (d->Semantic.Name == TGSI_SEMANTIC_POSITION) :
602 (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) {
603 if (last_args[0]) {
604 lp_build_intrinsic(base->gallivm->builder,
605 "llvm.SI.export",
606 LLVMVoidTypeInContext(base->gallivm->context),
607 last_args, 9);
608 }
609
610 memcpy(last_args, args, sizeof(args));
611 } else {
612 lp_build_intrinsic(base->gallivm->builder,
613 "llvm.SI.export",
614 LLVMVoidTypeInContext(base->gallivm->context),
615 args, 9);
616 }
617
618 }
619 }
620
621 if (depth_index >= 0 || stencil_index >= 0) {
622 LLVMValueRef out_ptr;
623 unsigned mask = 0;
624
625 /* Specify the target we are exporting */
626 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
627
628 if (depth_index >= 0) {
629 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
630 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
631 mask |= 0x1;
632
633 if (stencil_index < 0) {
634 args[6] =
635 args[7] =
636 args[8] = args[5];
637 }
638 }
639
640 if (stencil_index >= 0) {
641 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
642 args[7] =
643 args[8] =
644 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
645 mask |= 0x2;
646
647 if (depth_index < 0)
648 args[5] = args[6];
649 }
650
651 /* Specify which components to enable */
652 args[0] = lp_build_const_int32(base->gallivm, mask);
653
654 args[1] =
655 args[2] =
656 args[4] = uint->zero;
657
658 if (last_args[0])
659 lp_build_intrinsic(base->gallivm->builder,
660 "llvm.SI.export",
661 LLVMVoidTypeInContext(base->gallivm->context),
662 args, 9);
663 else
664 memcpy(last_args, args, sizeof(args));
665 }
666
667 if (!last_args[0]) {
668 assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
669
670 /* Specify which components to enable */
671 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
672
673 /* Specify the target we are exporting */
674 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
675
676 /* Set COMPR flag to zero to export data as 32-bit */
677 last_args[4] = uint->zero;
678
679 /* dummy bits */
680 last_args[5]= uint->zero;
681 last_args[6]= uint->zero;
682 last_args[7]= uint->zero;
683 last_args[8]= uint->zero;
684
685 si_shader_ctx->shader->spi_shader_col_format |=
686 V_028714_SPI_SHADER_32_ABGR;
687 }
688
689 /* Specify whether the EXEC mask represents the valid mask */
690 last_args[1] = lp_build_const_int32(base->gallivm,
691 si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
692
693 if (shader->fs_write_all && shader->nr_cbufs > 1) {
694 int i;
695
696 /* Specify that this is not yet the last export */
697 last_args[2] = lp_build_const_int32(base->gallivm, 0);
698
699 for (i = 1; i < shader->nr_cbufs; i++) {
700 /* Specify the target we are exporting */
701 last_args[3] = lp_build_const_int32(base->gallivm,
702 V_008DFC_SQ_EXP_MRT + i);
703
704 lp_build_intrinsic(base->gallivm->builder,
705 "llvm.SI.export",
706 LLVMVoidTypeInContext(base->gallivm->context),
707 last_args, 9);
708
709 si_shader_ctx->shader->spi_shader_col_format |=
710 si_shader_ctx->shader->spi_shader_col_format << 4;
711 }
712
713 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
714 }
715
716 /* Specify that this is the last export */
717 last_args[2] = lp_build_const_int32(base->gallivm, 1);
718
719 lp_build_intrinsic(base->gallivm->builder,
720 "llvm.SI.export",
721 LLVMVoidTypeInContext(base->gallivm->context),
722 last_args, 9);
723
724 /* XXX: Look up what this function does */
725 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
726 }
727
728 static void tex_fetch_args(
729 struct lp_build_tgsi_context * bld_base,
730 struct lp_build_emit_data * emit_data)
731 {
732 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
733 struct gallivm_state *gallivm = bld_base->base.gallivm;
734 const struct tgsi_full_instruction * inst = emit_data->inst;
735 unsigned opcode = inst->Instruction.Opcode;
736 unsigned target = inst->Texture.Texture;
737 LLVMValueRef ptr;
738 LLVMValueRef offset;
739 LLVMValueRef coords[4];
740 LLVMValueRef address[16];
741 unsigned count = 0;
742 unsigned chan;
743
744 /* WriteMask */
745 /* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
746 emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm, 0xf);
747
748 /* Fetch and project texture coordinates */
749 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
750 for (chan = 0; chan < 3; chan++ ) {
751 coords[chan] = lp_build_emit_fetch(bld_base,
752 emit_data->inst, 0,
753 chan);
754 if (opcode == TGSI_OPCODE_TXP)
755 coords[chan] = lp_build_emit_llvm_binary(bld_base,
756 TGSI_OPCODE_DIV,
757 coords[chan],
758 coords[3]);
759 }
760
761 if (opcode == TGSI_OPCODE_TXP)
762 coords[3] = bld_base->base.one;
763
764 /* Pack LOD bias value */
765 if (opcode == TGSI_OPCODE_TXB)
766 address[count++] = coords[3];
767
768 if ((target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE) &&
769 opcode != TGSI_OPCODE_TXQ)
770 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
771
772 /* Pack depth comparison value */
773 switch (target) {
774 case TGSI_TEXTURE_SHADOW1D:
775 case TGSI_TEXTURE_SHADOW1D_ARRAY:
776 case TGSI_TEXTURE_SHADOW2D:
777 case TGSI_TEXTURE_SHADOWRECT:
778 address[count++] = coords[2];
779 break;
780 case TGSI_TEXTURE_SHADOWCUBE:
781 case TGSI_TEXTURE_SHADOW2D_ARRAY:
782 address[count++] = coords[3];
783 break;
784 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
785 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
786 }
787
788 /* Pack texture coordinates */
789 address[count++] = coords[0];
790 switch (target) {
791 case TGSI_TEXTURE_2D:
792 case TGSI_TEXTURE_2D_ARRAY:
793 case TGSI_TEXTURE_3D:
794 case TGSI_TEXTURE_CUBE:
795 case TGSI_TEXTURE_RECT:
796 case TGSI_TEXTURE_SHADOW2D:
797 case TGSI_TEXTURE_SHADOWRECT:
798 case TGSI_TEXTURE_SHADOW2D_ARRAY:
799 case TGSI_TEXTURE_SHADOWCUBE:
800 case TGSI_TEXTURE_2D_MSAA:
801 case TGSI_TEXTURE_2D_ARRAY_MSAA:
802 case TGSI_TEXTURE_CUBE_ARRAY:
803 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
804 address[count++] = coords[1];
805 }
806 switch (target) {
807 case TGSI_TEXTURE_3D:
808 case TGSI_TEXTURE_CUBE:
809 case TGSI_TEXTURE_SHADOWCUBE:
810 case TGSI_TEXTURE_CUBE_ARRAY:
811 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
812 address[count++] = coords[2];
813 }
814
815 /* Pack array slice */
816 switch (target) {
817 case TGSI_TEXTURE_1D_ARRAY:
818 address[count++] = coords[1];
819 }
820 switch (target) {
821 case TGSI_TEXTURE_2D_ARRAY:
822 case TGSI_TEXTURE_2D_ARRAY_MSAA:
823 case TGSI_TEXTURE_SHADOW2D_ARRAY:
824 address[count++] = coords[2];
825 }
826 switch (target) {
827 case TGSI_TEXTURE_CUBE_ARRAY:
828 case TGSI_TEXTURE_SHADOW1D_ARRAY:
829 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
830 address[count++] = coords[3];
831 }
832
833 /* Pack LOD */
834 if (opcode == TGSI_OPCODE_TXL)
835 address[count++] = coords[3];
836
837 if (count > 16) {
838 assert(!"Cannot handle more than 16 texture address parameters");
839 count = 16;
840 }
841
842 for (chan = 0; chan < count; chan++ ) {
843 address[chan] = LLVMBuildBitCast(gallivm->builder,
844 address[chan],
845 LLVMInt32TypeInContext(gallivm->context),
846 "");
847 }
848
849 /* Pad to power of two vector */
850 while (count < util_next_power_of_two(count))
851 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
852
853 emit_data->args[1] = lp_build_gather_values(gallivm, address, count);
854
855 /* Resource */
856 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
857 offset = lp_build_const_int32(bld_base->base.gallivm,
858 emit_data->inst->Src[1].Register.Index);
859 emit_data->args[2] = build_indexed_load(bld_base->base.gallivm,
860 ptr, offset);
861
862 /* Sampler */
863 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
864 offset = lp_build_const_int32(bld_base->base.gallivm,
865 emit_data->inst->Src[1].Register.Index);
866 emit_data->args[3] = build_indexed_load(bld_base->base.gallivm,
867 ptr, offset);
868
869 /* Dimensions */
870 emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm, target);
871
872 emit_data->arg_count = 5;
873 /* XXX: To optimize, we could use a float or v2f32, if the last bits of
874 * the writemask are clear */
875 emit_data->dst_type = LLVMVectorType(
876 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
877 4);
878 }
879
880 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
881 struct lp_build_tgsi_context * bld_base,
882 struct lp_build_emit_data * emit_data)
883 {
884 struct lp_build_context * base = &bld_base->base;
885 char intr_name[23];
886
887 sprintf(intr_name, "%sv%ui32", action->intr_name,
888 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[1])));
889
890 emit_data->output[emit_data->chan] = lp_build_intrinsic(
891 base->gallivm->builder, intr_name, emit_data->dst_type,
892 emit_data->args, emit_data->arg_count);
893 }
894
895 static const struct lp_build_tgsi_action tex_action = {
896 .fetch_args = tex_fetch_args,
897 .emit = build_tex_intrinsic,
898 .intr_name = "llvm.SI.sample."
899 };
900
901 static const struct lp_build_tgsi_action txb_action = {
902 .fetch_args = tex_fetch_args,
903 .emit = build_tex_intrinsic,
904 .intr_name = "llvm.SI.sampleb."
905 };
906
907 static const struct lp_build_tgsi_action txl_action = {
908 .fetch_args = tex_fetch_args,
909 .emit = build_tex_intrinsic,
910 .intr_name = "llvm.SI.samplel."
911 };
912
913 static void create_function(struct si_shader_context *si_shader_ctx)
914 {
915 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
916 LLVMTypeRef params[20], f32, i8, i32, v2i32, v3i32;
917 unsigned i;
918
919 i8 = LLVMInt8TypeInContext(gallivm->context);
920 i32 = LLVMInt32TypeInContext(gallivm->context);
921 f32 = LLVMFloatTypeInContext(gallivm->context);
922 v2i32 = LLVMVectorType(i32, 2);
923 v3i32 = LLVMVectorType(i32, 3);
924
925 params[SI_PARAM_CONST] = LLVMPointerType(LLVMVectorType(i8, 16), CONST_ADDR_SPACE);
926 params[SI_PARAM_SAMPLER] = params[SI_PARAM_CONST];
927 params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), CONST_ADDR_SPACE);
928
929 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
930 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
931 params[SI_PARAM_VERTEX_INDEX] = i32;
932 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 5);
933
934 } else {
935 params[SI_PARAM_PRIM_MASK] = i32;
936 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
937 params[SI_PARAM_PERSP_CENTER] = v2i32;
938 params[SI_PARAM_PERSP_CENTROID] = v2i32;
939 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
940 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
941 params[SI_PARAM_LINEAR_CENTER] = v2i32;
942 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
943 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
944 params[SI_PARAM_POS_X_FLOAT] = f32;
945 params[SI_PARAM_POS_Y_FLOAT] = f32;
946 params[SI_PARAM_POS_Z_FLOAT] = f32;
947 params[SI_PARAM_POS_W_FLOAT] = f32;
948 params[SI_PARAM_FRONT_FACE] = f32;
949 params[SI_PARAM_ANCILLARY] = f32;
950 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
951 params[SI_PARAM_POS_FIXED_PT] = f32;
952 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 20);
953 }
954
955 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
956 for (i = SI_PARAM_CONST; i <= SI_PARAM_VERTEX_BUFFER; ++i) {
957 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
958 LLVMAddAttribute(P, LLVMInRegAttribute);
959 }
960 }
961
962 int si_pipe_shader_create(
963 struct pipe_context *ctx,
964 struct si_pipe_shader *shader,
965 struct si_shader_key key)
966 {
967 struct r600_context *rctx = (struct r600_context*)ctx;
968 struct si_pipe_shader_selector *sel = shader->selector;
969 struct si_shader_context si_shader_ctx;
970 struct tgsi_shader_info shader_info;
971 struct lp_build_tgsi_context * bld_base;
972 LLVMModuleRef mod;
973 unsigned char * inst_bytes;
974 unsigned inst_byte_count;
975 unsigned i;
976 uint32_t *ptr;
977 bool dump;
978
979 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
980
981 assert(shader->shader.noutput == 0);
982 assert(shader->shader.ninterp == 0);
983 assert(shader->shader.ninput == 0);
984
985 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
986 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
987 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
988
989 tgsi_scan_shader(sel->tokens, &shader_info);
990 shader->shader.uses_kill = shader_info.uses_kill;
991 bld_base->info = &shader_info;
992 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
993 bld_base->emit_epilogue = si_llvm_emit_epilogue;
994
995 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
996 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
997 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
998 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
999
1000 si_shader_ctx.radeon_bld.load_input = declare_input;
1001 si_shader_ctx.tokens = sel->tokens;
1002 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
1003 si_shader_ctx.shader = shader;
1004 si_shader_ctx.key = key;
1005 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
1006 si_shader_ctx.rctx = rctx;
1007
1008 create_function(&si_shader_ctx);
1009
1010 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
1011
1012 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
1013 * conversion fails. */
1014 if (dump) {
1015 tgsi_dump(sel->tokens, 0);
1016 }
1017
1018 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
1019 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
1020 return -EINVAL;
1021 }
1022
1023 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
1024
1025 mod = bld_base->base.gallivm->module;
1026 if (dump) {
1027 LLVMDumpModule(mod);
1028 }
1029 radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count, "SI", dump);
1030 if (dump) {
1031 fprintf(stderr, "SI CODE:\n");
1032 for (i = 0; i < inst_byte_count; i+=4 ) {
1033 fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3],
1034 inst_bytes[i + 2], inst_bytes[i + 1],
1035 inst_bytes[i]);
1036 }
1037 }
1038
1039 shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes);
1040 shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4));
1041 shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8));
1042
1043 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
1044 tgsi_parse_free(&si_shader_ctx.parse);
1045
1046 /* copy new shader */
1047 si_resource_reference(&shader->bo, NULL);
1048 shader->bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
1049 inst_byte_count - 12);
1050 if (shader->bo == NULL) {
1051 return -ENOMEM;
1052 }
1053
1054 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1055 if (0 /*R600_BIG_ENDIAN*/) {
1056 for (i = 0; i < (inst_byte_count-12)/4; ++i) {
1057 ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4));
1058 }
1059 } else {
1060 memcpy(ptr, inst_bytes + 12, inst_byte_count - 12);
1061 }
1062 rctx->ws->buffer_unmap(shader->bo->cs_buf);
1063
1064 free(inst_bytes);
1065
1066 return 0;
1067 }
1068
1069 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
1070 {
1071 si_resource_reference(&shader->bo, NULL);
1072 }