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radeonsi: add preloading for all samplers
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "gallivm/lp_bld_arit.h"
37 #include "radeon_llvm.h"
38 #include "radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "tgsi/tgsi_info.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "radeonsi_pipe.h"
46 #include "radeonsi_shader.h"
47 #include "si_state.h"
48 #include "sid.h"
49
50 #include <assert.h>
51 #include <errno.h>
52 #include <stdio.h>
53
54 struct si_shader_context
55 {
56 struct radeon_llvm_context radeon_bld;
57 struct r600_context *rctx;
58 struct tgsi_parse_context parse;
59 struct tgsi_token * tokens;
60 struct si_pipe_shader *shader;
61 struct si_shader_key key;
62 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
63 LLVMValueRef const_md;
64 LLVMValueRef const_resource;
65 LLVMValueRef *constants;
66 LLVMValueRef *resources;
67 LLVMValueRef *samplers;
68 };
69
70 static struct si_shader_context * si_shader_context(
71 struct lp_build_tgsi_context * bld_base)
72 {
73 return (struct si_shader_context *)bld_base;
74 }
75
76
77 #define PERSPECTIVE_BASE 0
78 #define LINEAR_BASE 9
79
80 #define SAMPLE_OFFSET 0
81 #define CENTER_OFFSET 2
82 #define CENTROID_OFSET 4
83
84 #define USE_SGPR_MAX_SUFFIX_LEN 5
85 #define CONST_ADDR_SPACE 2
86 #define USER_SGPR_ADDR_SPACE 8
87
88 /**
89 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
90 *
91 * @param offset The offset parameter specifies the number of
92 * elements to offset, not the number of bytes or dwords. An element is the
93 * the type pointed to by the base_ptr parameter (e.g. int is the element of
94 * an int* pointer)
95 *
96 * When LLVM lowers the load instruction, it will convert the element offset
97 * into a dword offset automatically.
98 *
99 */
100 static LLVMValueRef build_indexed_load(
101 struct si_shader_context * si_shader_ctx,
102 LLVMValueRef base_ptr,
103 LLVMValueRef offset)
104 {
105 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
106
107 LLVMValueRef computed_ptr = LLVMBuildGEP(
108 base->gallivm->builder, base_ptr, &offset, 1, "");
109
110 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
111 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
112 return result;
113 }
114
115 static void declare_input_vs(
116 struct si_shader_context * si_shader_ctx,
117 unsigned input_index,
118 const struct tgsi_full_declaration *decl)
119 {
120 LLVMValueRef t_list_ptr;
121 LLVMValueRef t_offset;
122 LLVMValueRef t_list;
123 LLVMValueRef attribute_offset;
124 LLVMValueRef buffer_index_reg;
125 LLVMValueRef args[3];
126 LLVMTypeRef vec4_type;
127 LLVMValueRef input;
128 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
129 //struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[input_index];
130 unsigned chan;
131
132 /* Load the T list */
133 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
134
135 t_offset = lp_build_const_int32(base->gallivm, input_index);
136
137 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
138
139 /* Build the attribute offset */
140 attribute_offset = lp_build_const_int32(base->gallivm, 0);
141
142 /* Load the buffer index, which is always stored in VGPR0
143 * for Vertex Shaders */
144 buffer_index_reg = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_INDEX);
145
146 vec4_type = LLVMVectorType(base->elem_type, 4);
147 args[0] = t_list;
148 args[1] = attribute_offset;
149 args[2] = buffer_index_reg;
150 input = build_intrinsic(base->gallivm->builder,
151 "llvm.SI.vs.load.input", vec4_type, args, 3,
152 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
153
154 /* Break up the vec4 into individual components */
155 for (chan = 0; chan < 4; chan++) {
156 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
157 /* XXX: Use a helper function for this. There is one in
158 * tgsi_llvm.c. */
159 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
160 LLVMBuildExtractElement(base->gallivm->builder,
161 input, llvm_chan, "");
162 }
163 }
164
165 static void declare_input_fs(
166 struct si_shader_context * si_shader_ctx,
167 unsigned input_index,
168 const struct tgsi_full_declaration *decl)
169 {
170 struct si_shader *shader = &si_shader_ctx->shader->shader;
171 struct lp_build_context * base =
172 &si_shader_ctx->radeon_bld.soa.bld_base.base;
173 struct gallivm_state * gallivm = base->gallivm;
174 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
175 LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
176
177 LLVMValueRef interp_param;
178 const char * intr_name;
179
180 /* This value is:
181 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
182 * quad begins a new primitive. Bit 0 always needs
183 * to be unset)
184 * [32:16] ParamOffset
185 *
186 */
187 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
188 LLVMValueRef attr_number;
189
190 unsigned chan;
191
192 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
193 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
194 unsigned soa_index =
195 radeon_llvm_reg_index_soa(input_index, chan);
196 si_shader_ctx->radeon_bld.inputs[soa_index] =
197 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
198
199 if (chan == 3)
200 /* RCP for fragcoord.w */
201 si_shader_ctx->radeon_bld.inputs[soa_index] =
202 LLVMBuildFDiv(gallivm->builder,
203 lp_build_const_float(gallivm, 1.0f),
204 si_shader_ctx->radeon_bld.inputs[soa_index],
205 "");
206 }
207 return;
208 }
209
210 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
211 LLVMValueRef face, is_face_positive;
212
213 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
214
215 is_face_positive = LLVMBuildFCmp(gallivm->builder,
216 LLVMRealUGT, face,
217 lp_build_const_float(gallivm, 0.0f),
218 "");
219
220 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
221 LLVMBuildSelect(gallivm->builder,
222 is_face_positive,
223 lp_build_const_float(gallivm, 1.0f),
224 lp_build_const_float(gallivm, 0.0f),
225 "");
226 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
227 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
228 lp_build_const_float(gallivm, 0.0f);
229 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
230 lp_build_const_float(gallivm, 1.0f);
231
232 return;
233 }
234
235 shader->input[input_index].param_offset = shader->ninterp++;
236 attr_number = lp_build_const_int32(gallivm,
237 shader->input[input_index].param_offset);
238
239 /* XXX: Handle all possible interpolation modes */
240 switch (decl->Interp.Interpolate) {
241 case TGSI_INTERPOLATE_COLOR:
242 if (si_shader_ctx->key.flatshade) {
243 interp_param = 0;
244 } else {
245 if (decl->Interp.Centroid)
246 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
247 else
248 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
249 }
250 break;
251 case TGSI_INTERPOLATE_CONSTANT:
252 interp_param = 0;
253 break;
254 case TGSI_INTERPOLATE_LINEAR:
255 if (decl->Interp.Centroid)
256 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
257 else
258 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
259 break;
260 case TGSI_INTERPOLATE_PERSPECTIVE:
261 if (decl->Interp.Centroid)
262 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
263 else
264 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
265 break;
266 default:
267 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
268 return;
269 }
270
271 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
272
273 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
274 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
275 si_shader_ctx->key.color_two_side) {
276 LLVMValueRef args[4];
277 LLVMValueRef face, is_face_positive;
278 LLVMValueRef back_attr_number =
279 lp_build_const_int32(gallivm,
280 shader->input[input_index].param_offset + 1);
281
282 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
283
284 is_face_positive = LLVMBuildFCmp(gallivm->builder,
285 LLVMRealUGT, face,
286 lp_build_const_float(gallivm, 0.0f),
287 "");
288
289 args[2] = params;
290 args[3] = interp_param;
291 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
292 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
293 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
294 LLVMValueRef front, back;
295
296 args[0] = llvm_chan;
297 args[1] = attr_number;
298 front = build_intrinsic(base->gallivm->builder, intr_name,
299 input_type, args, args[3] ? 4 : 3,
300 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
301
302 args[1] = back_attr_number;
303 back = build_intrinsic(base->gallivm->builder, intr_name,
304 input_type, args, args[3] ? 4 : 3,
305 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
306
307 si_shader_ctx->radeon_bld.inputs[soa_index] =
308 LLVMBuildSelect(gallivm->builder,
309 is_face_positive,
310 front,
311 back,
312 "");
313 }
314
315 shader->ninterp++;
316 } else {
317 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
318 LLVMValueRef args[4];
319 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
320 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
321 args[0] = llvm_chan;
322 args[1] = attr_number;
323 args[2] = params;
324 args[3] = interp_param;
325 si_shader_ctx->radeon_bld.inputs[soa_index] =
326 build_intrinsic(base->gallivm->builder, intr_name,
327 input_type, args, args[3] ? 4 : 3,
328 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
329 }
330 }
331 }
332
333 static void declare_input(
334 struct radeon_llvm_context * radeon_bld,
335 unsigned input_index,
336 const struct tgsi_full_declaration *decl)
337 {
338 struct si_shader_context * si_shader_ctx =
339 si_shader_context(&radeon_bld->soa.bld_base);
340 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
341 declare_input_vs(si_shader_ctx, input_index, decl);
342 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
343 declare_input_fs(si_shader_ctx, input_index, decl);
344 } else {
345 fprintf(stderr, "Warning: Unsupported shader type,\n");
346 }
347 }
348
349 static LLVMValueRef fetch_constant(
350 struct lp_build_tgsi_context * bld_base,
351 const struct tgsi_full_src_register *reg,
352 enum tgsi_opcode_type type,
353 unsigned swizzle)
354 {
355 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
356 struct lp_build_context * base = &bld_base->base;
357 const struct tgsi_ind_register *ireg = &reg->Indirect;
358 unsigned idx;
359
360 LLVMValueRef args[2];
361 LLVMValueRef addr;
362 LLVMValueRef result;
363
364 if (swizzle == LP_CHAN_ALL) {
365 unsigned chan;
366 LLVMValueRef values[4];
367 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
368 values[chan] = fetch_constant(bld_base, reg, type, chan);
369
370 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
371 }
372
373 idx = reg->Register.Index * 4 + swizzle;
374 if (!reg->Register.Indirect)
375 return bitcast(bld_base, type, si_shader_ctx->constants[idx]);
376
377 args[0] = si_shader_ctx->const_resource;
378 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
379 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
380 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
381 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
382 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
383
384 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
385 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
386
387 return bitcast(bld_base, type, result);
388 }
389
390 /* Initialize arguments for the shader export intrinsic */
391 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
392 struct tgsi_full_declaration *d,
393 unsigned index,
394 unsigned target,
395 LLVMValueRef *args)
396 {
397 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
398 struct lp_build_context *uint =
399 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
400 struct lp_build_context *base = &bld_base->base;
401 unsigned compressed = 0;
402 unsigned chan;
403
404 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
405 int cbuf = target - V_008DFC_SQ_EXP_MRT;
406
407 if (cbuf >= 0 && cbuf < 8) {
408 compressed = (si_shader_ctx->key.export_16bpc >> cbuf) & 0x1;
409
410 if (compressed)
411 si_shader_ctx->shader->spi_shader_col_format |=
412 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
413 else
414 si_shader_ctx->shader->spi_shader_col_format |=
415 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
416 }
417 }
418
419 if (compressed) {
420 /* Pixel shader needs to pack output values before export */
421 for (chan = 0; chan < 2; chan++ ) {
422 LLVMValueRef *out_ptr =
423 si_shader_ctx->radeon_bld.soa.outputs[index];
424 args[0] = LLVMBuildLoad(base->gallivm->builder,
425 out_ptr[2 * chan], "");
426 args[1] = LLVMBuildLoad(base->gallivm->builder,
427 out_ptr[2 * chan + 1], "");
428 args[chan + 5] =
429 build_intrinsic(base->gallivm->builder,
430 "llvm.SI.packf16",
431 LLVMInt32TypeInContext(base->gallivm->context),
432 args, 2,
433 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
434 args[chan + 7] = args[chan + 5] =
435 LLVMBuildBitCast(base->gallivm->builder,
436 args[chan + 5],
437 LLVMFloatTypeInContext(base->gallivm->context),
438 "");
439 }
440
441 /* Set COMPR flag */
442 args[4] = uint->one;
443 } else {
444 for (chan = 0; chan < 4; chan++ ) {
445 LLVMValueRef out_ptr =
446 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
447 /* +5 because the first output value will be
448 * the 6th argument to the intrinsic. */
449 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
450 out_ptr, "");
451 }
452
453 /* Clear COMPR flag */
454 args[4] = uint->zero;
455 }
456
457 /* XXX: This controls which components of the output
458 * registers actually get exported. (e.g bit 0 means export
459 * X component, bit 1 means export Y component, etc.) I'm
460 * hard coding this to 0xf for now. In the future, we might
461 * want to do something else. */
462 args[0] = lp_build_const_int32(base->gallivm, 0xf);
463
464 /* Specify whether the EXEC mask represents the valid mask */
465 args[1] = uint->zero;
466
467 /* Specify whether this is the last export */
468 args[2] = uint->zero;
469
470 /* Specify the target we are exporting */
471 args[3] = lp_build_const_int32(base->gallivm, target);
472
473 /* XXX: We probably need to keep track of the output
474 * values, so we know what we are passing to the next
475 * stage. */
476 }
477
478 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
479 unsigned index)
480 {
481 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
482 struct gallivm_state *gallivm = bld_base->base.gallivm;
483
484 if (si_shader_ctx->key.alpha_func != PIPE_FUNC_NEVER) {
485 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
486 LLVMValueRef alpha_pass =
487 lp_build_cmp(&bld_base->base,
488 si_shader_ctx->key.alpha_func,
489 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
490 lp_build_const_float(gallivm, si_shader_ctx->key.alpha_ref));
491 LLVMValueRef arg =
492 lp_build_select(&bld_base->base,
493 alpha_pass,
494 lp_build_const_float(gallivm, 1.0f),
495 lp_build_const_float(gallivm, -1.0f));
496
497 build_intrinsic(gallivm->builder,
498 "llvm.AMDGPU.kill",
499 LLVMVoidTypeInContext(gallivm->context),
500 &arg, 1, 0);
501 } else {
502 build_intrinsic(gallivm->builder,
503 "llvm.AMDGPU.kilp",
504 LLVMVoidTypeInContext(gallivm->context),
505 NULL, 0, 0);
506 }
507 }
508
509 /* XXX: This is partially implemented for VS only at this point. It is not complete */
510 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
511 {
512 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
513 struct si_shader * shader = &si_shader_ctx->shader->shader;
514 struct lp_build_context * base = &bld_base->base;
515 struct lp_build_context * uint =
516 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
517 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
518 LLVMValueRef args[9];
519 LLVMValueRef last_args[9] = { 0 };
520 unsigned color_count = 0;
521 unsigned param_count = 0;
522 int depth_index = -1, stencil_index = -1;
523
524 while (!tgsi_parse_end_of_tokens(parse)) {
525 struct tgsi_full_declaration *d =
526 &parse->FullToken.FullDeclaration;
527 unsigned target;
528 unsigned index;
529 int i;
530
531 tgsi_parse_token(parse);
532
533 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
534 parse->FullToken.FullProperty.Property.PropertyName ==
535 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
536 shader->fs_write_all = TRUE;
537
538 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
539 continue;
540
541 switch (d->Declaration.File) {
542 case TGSI_FILE_INPUT:
543 i = shader->ninput++;
544 shader->input[i].name = d->Semantic.Name;
545 shader->input[i].sid = d->Semantic.Index;
546 shader->input[i].interpolate = d->Interp.Interpolate;
547 shader->input[i].centroid = d->Interp.Centroid;
548 continue;
549
550 case TGSI_FILE_OUTPUT:
551 i = shader->noutput++;
552 shader->output[i].name = d->Semantic.Name;
553 shader->output[i].sid = d->Semantic.Index;
554 shader->output[i].interpolate = d->Interp.Interpolate;
555 break;
556
557 default:
558 continue;
559 }
560
561 for (index = d->Range.First; index <= d->Range.Last; index++) {
562 /* Select the correct target */
563 switch(d->Semantic.Name) {
564 case TGSI_SEMANTIC_PSIZE:
565 target = V_008DFC_SQ_EXP_POS;
566 break;
567 case TGSI_SEMANTIC_POSITION:
568 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
569 target = V_008DFC_SQ_EXP_POS;
570 break;
571 } else {
572 depth_index = index;
573 continue;
574 }
575 case TGSI_SEMANTIC_STENCIL:
576 stencil_index = index;
577 continue;
578 case TGSI_SEMANTIC_COLOR:
579 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
580 case TGSI_SEMANTIC_BCOLOR:
581 target = V_008DFC_SQ_EXP_PARAM + param_count;
582 shader->output[i].param_offset = param_count;
583 param_count++;
584 } else {
585 target = V_008DFC_SQ_EXP_MRT + color_count;
586 if (color_count == 0 &&
587 si_shader_ctx->key.alpha_func != PIPE_FUNC_ALWAYS)
588 si_alpha_test(bld_base, index);
589
590 color_count++;
591 }
592 break;
593 case TGSI_SEMANTIC_FOG:
594 case TGSI_SEMANTIC_GENERIC:
595 target = V_008DFC_SQ_EXP_PARAM + param_count;
596 shader->output[i].param_offset = param_count;
597 param_count++;
598 break;
599 default:
600 target = 0;
601 fprintf(stderr,
602 "Warning: SI unhandled output type:%d\n",
603 d->Semantic.Name);
604 }
605
606 si_llvm_init_export_args(bld_base, d, index, target, args);
607
608 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
609 (d->Semantic.Name == TGSI_SEMANTIC_POSITION) :
610 (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) {
611 if (last_args[0]) {
612 lp_build_intrinsic(base->gallivm->builder,
613 "llvm.SI.export",
614 LLVMVoidTypeInContext(base->gallivm->context),
615 last_args, 9);
616 }
617
618 memcpy(last_args, args, sizeof(args));
619 } else {
620 lp_build_intrinsic(base->gallivm->builder,
621 "llvm.SI.export",
622 LLVMVoidTypeInContext(base->gallivm->context),
623 args, 9);
624 }
625
626 }
627 }
628
629 if (depth_index >= 0 || stencil_index >= 0) {
630 LLVMValueRef out_ptr;
631 unsigned mask = 0;
632
633 /* Specify the target we are exporting */
634 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
635
636 if (depth_index >= 0) {
637 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
638 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
639 mask |= 0x1;
640
641 if (stencil_index < 0) {
642 args[6] =
643 args[7] =
644 args[8] = args[5];
645 }
646 }
647
648 if (stencil_index >= 0) {
649 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
650 args[7] =
651 args[8] =
652 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
653 mask |= 0x2;
654
655 if (depth_index < 0)
656 args[5] = args[6];
657 }
658
659 /* Specify which components to enable */
660 args[0] = lp_build_const_int32(base->gallivm, mask);
661
662 args[1] =
663 args[2] =
664 args[4] = uint->zero;
665
666 if (last_args[0])
667 lp_build_intrinsic(base->gallivm->builder,
668 "llvm.SI.export",
669 LLVMVoidTypeInContext(base->gallivm->context),
670 args, 9);
671 else
672 memcpy(last_args, args, sizeof(args));
673 }
674
675 if (!last_args[0]) {
676 assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
677
678 /* Specify which components to enable */
679 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
680
681 /* Specify the target we are exporting */
682 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
683
684 /* Set COMPR flag to zero to export data as 32-bit */
685 last_args[4] = uint->zero;
686
687 /* dummy bits */
688 last_args[5]= uint->zero;
689 last_args[6]= uint->zero;
690 last_args[7]= uint->zero;
691 last_args[8]= uint->zero;
692
693 si_shader_ctx->shader->spi_shader_col_format |=
694 V_028714_SPI_SHADER_32_ABGR;
695 }
696
697 /* Specify whether the EXEC mask represents the valid mask */
698 last_args[1] = lp_build_const_int32(base->gallivm,
699 si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
700
701 if (shader->fs_write_all && shader->nr_cbufs > 1) {
702 int i;
703
704 /* Specify that this is not yet the last export */
705 last_args[2] = lp_build_const_int32(base->gallivm, 0);
706
707 for (i = 1; i < shader->nr_cbufs; i++) {
708 /* Specify the target we are exporting */
709 last_args[3] = lp_build_const_int32(base->gallivm,
710 V_008DFC_SQ_EXP_MRT + i);
711
712 lp_build_intrinsic(base->gallivm->builder,
713 "llvm.SI.export",
714 LLVMVoidTypeInContext(base->gallivm->context),
715 last_args, 9);
716
717 si_shader_ctx->shader->spi_shader_col_format |=
718 si_shader_ctx->shader->spi_shader_col_format << 4;
719 }
720
721 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
722 }
723
724 /* Specify that this is the last export */
725 last_args[2] = lp_build_const_int32(base->gallivm, 1);
726
727 lp_build_intrinsic(base->gallivm->builder,
728 "llvm.SI.export",
729 LLVMVoidTypeInContext(base->gallivm->context),
730 last_args, 9);
731
732 /* XXX: Look up what this function does */
733 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
734 }
735
736 static void tex_fetch_args(
737 struct lp_build_tgsi_context * bld_base,
738 struct lp_build_emit_data * emit_data)
739 {
740 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
741 struct gallivm_state *gallivm = bld_base->base.gallivm;
742 const struct tgsi_full_instruction * inst = emit_data->inst;
743 unsigned opcode = inst->Instruction.Opcode;
744 unsigned target = inst->Texture.Texture;
745 LLVMValueRef coords[4];
746 LLVMValueRef address[16];
747 unsigned count = 0;
748 unsigned chan;
749
750 /* WriteMask */
751 /* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
752 emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm, 0xf);
753
754 /* Fetch and project texture coordinates */
755 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
756 for (chan = 0; chan < 3; chan++ ) {
757 coords[chan] = lp_build_emit_fetch(bld_base,
758 emit_data->inst, 0,
759 chan);
760 if (opcode == TGSI_OPCODE_TXP)
761 coords[chan] = lp_build_emit_llvm_binary(bld_base,
762 TGSI_OPCODE_DIV,
763 coords[chan],
764 coords[3]);
765 }
766
767 if (opcode == TGSI_OPCODE_TXP)
768 coords[3] = bld_base->base.one;
769
770 /* Pack LOD bias value */
771 if (opcode == TGSI_OPCODE_TXB)
772 address[count++] = coords[3];
773
774 if ((target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE) &&
775 opcode != TGSI_OPCODE_TXQ)
776 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
777
778 /* Pack depth comparison value */
779 switch (target) {
780 case TGSI_TEXTURE_SHADOW1D:
781 case TGSI_TEXTURE_SHADOW1D_ARRAY:
782 case TGSI_TEXTURE_SHADOW2D:
783 case TGSI_TEXTURE_SHADOWRECT:
784 address[count++] = coords[2];
785 break;
786 case TGSI_TEXTURE_SHADOWCUBE:
787 case TGSI_TEXTURE_SHADOW2D_ARRAY:
788 address[count++] = coords[3];
789 break;
790 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
791 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
792 }
793
794 /* Pack texture coordinates */
795 address[count++] = coords[0];
796 switch (target) {
797 case TGSI_TEXTURE_2D:
798 case TGSI_TEXTURE_2D_ARRAY:
799 case TGSI_TEXTURE_3D:
800 case TGSI_TEXTURE_CUBE:
801 case TGSI_TEXTURE_RECT:
802 case TGSI_TEXTURE_SHADOW2D:
803 case TGSI_TEXTURE_SHADOWRECT:
804 case TGSI_TEXTURE_SHADOW2D_ARRAY:
805 case TGSI_TEXTURE_SHADOWCUBE:
806 case TGSI_TEXTURE_2D_MSAA:
807 case TGSI_TEXTURE_2D_ARRAY_MSAA:
808 case TGSI_TEXTURE_CUBE_ARRAY:
809 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
810 address[count++] = coords[1];
811 }
812 switch (target) {
813 case TGSI_TEXTURE_3D:
814 case TGSI_TEXTURE_CUBE:
815 case TGSI_TEXTURE_SHADOWCUBE:
816 case TGSI_TEXTURE_CUBE_ARRAY:
817 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
818 address[count++] = coords[2];
819 }
820
821 /* Pack array slice */
822 switch (target) {
823 case TGSI_TEXTURE_1D_ARRAY:
824 address[count++] = coords[1];
825 }
826 switch (target) {
827 case TGSI_TEXTURE_2D_ARRAY:
828 case TGSI_TEXTURE_2D_ARRAY_MSAA:
829 case TGSI_TEXTURE_SHADOW2D_ARRAY:
830 address[count++] = coords[2];
831 }
832 switch (target) {
833 case TGSI_TEXTURE_CUBE_ARRAY:
834 case TGSI_TEXTURE_SHADOW1D_ARRAY:
835 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
836 address[count++] = coords[3];
837 }
838
839 /* Pack LOD */
840 if (opcode == TGSI_OPCODE_TXL)
841 address[count++] = coords[3];
842
843 if (count > 16) {
844 assert(!"Cannot handle more than 16 texture address parameters");
845 count = 16;
846 }
847
848 for (chan = 0; chan < count; chan++ ) {
849 address[chan] = LLVMBuildBitCast(gallivm->builder,
850 address[chan],
851 LLVMInt32TypeInContext(gallivm->context),
852 "");
853 }
854
855 /* Pad to power of two vector */
856 while (count < util_next_power_of_two(count))
857 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
858
859 emit_data->args[1] = lp_build_gather_values(gallivm, address, count);
860
861 /* Resource */
862 emit_data->args[2] = si_shader_ctx->resources[emit_data->inst->Src[1].Register.Index];
863
864 /* Sampler */
865 emit_data->args[3] = si_shader_ctx->samplers[emit_data->inst->Src[1].Register.Index];
866
867 /* Dimensions */
868 emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm, target);
869
870 emit_data->arg_count = 5;
871 /* XXX: To optimize, we could use a float or v2f32, if the last bits of
872 * the writemask are clear */
873 emit_data->dst_type = LLVMVectorType(
874 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
875 4);
876 }
877
878 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
879 struct lp_build_tgsi_context * bld_base,
880 struct lp_build_emit_data * emit_data)
881 {
882 struct lp_build_context * base = &bld_base->base;
883 char intr_name[23];
884
885 sprintf(intr_name, "%sv%ui32", action->intr_name,
886 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[1])));
887
888 emit_data->output[emit_data->chan] = build_intrinsic(
889 base->gallivm->builder, intr_name, emit_data->dst_type,
890 emit_data->args, emit_data->arg_count,
891 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
892 }
893
894 static const struct lp_build_tgsi_action tex_action = {
895 .fetch_args = tex_fetch_args,
896 .emit = build_tex_intrinsic,
897 .intr_name = "llvm.SI.sample."
898 };
899
900 static const struct lp_build_tgsi_action txb_action = {
901 .fetch_args = tex_fetch_args,
902 .emit = build_tex_intrinsic,
903 .intr_name = "llvm.SI.sampleb."
904 };
905
906 static const struct lp_build_tgsi_action txl_action = {
907 .fetch_args = tex_fetch_args,
908 .emit = build_tex_intrinsic,
909 .intr_name = "llvm.SI.samplel."
910 };
911
912 static void create_meta_data(struct si_shader_context *si_shader_ctx)
913 {
914 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
915 LLVMValueRef args[3];
916
917 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
918 args[1] = 0;
919 args[2] = lp_build_const_int32(gallivm, 1);
920
921 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
922 }
923
924 static void create_function(struct si_shader_context *si_shader_ctx)
925 {
926 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
927 LLVMTypeRef params[20], f32, i8, i32, v2i32, v3i32;
928 unsigned i;
929
930 i8 = LLVMInt8TypeInContext(gallivm->context);
931 i32 = LLVMInt32TypeInContext(gallivm->context);
932 f32 = LLVMFloatTypeInContext(gallivm->context);
933 v2i32 = LLVMVectorType(i32, 2);
934 v3i32 = LLVMVectorType(i32, 3);
935
936 params[SI_PARAM_CONST] = LLVMPointerType(LLVMVectorType(i8, 16), CONST_ADDR_SPACE);
937 params[SI_PARAM_SAMPLER] = params[SI_PARAM_CONST];
938 params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), CONST_ADDR_SPACE);
939
940 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
941 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
942 params[SI_PARAM_VERTEX_INDEX] = i32;
943 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 5);
944
945 } else {
946 params[SI_PARAM_PRIM_MASK] = i32;
947 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
948 params[SI_PARAM_PERSP_CENTER] = v2i32;
949 params[SI_PARAM_PERSP_CENTROID] = v2i32;
950 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
951 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
952 params[SI_PARAM_LINEAR_CENTER] = v2i32;
953 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
954 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
955 params[SI_PARAM_POS_X_FLOAT] = f32;
956 params[SI_PARAM_POS_Y_FLOAT] = f32;
957 params[SI_PARAM_POS_Z_FLOAT] = f32;
958 params[SI_PARAM_POS_W_FLOAT] = f32;
959 params[SI_PARAM_FRONT_FACE] = f32;
960 params[SI_PARAM_ANCILLARY] = f32;
961 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
962 params[SI_PARAM_POS_FIXED_PT] = f32;
963 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 20);
964 }
965
966 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
967 for (i = SI_PARAM_CONST; i <= SI_PARAM_VERTEX_BUFFER; ++i) {
968 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
969 LLVMAddAttribute(P, LLVMInRegAttribute);
970 }
971 }
972
973 static void preload_constants(struct si_shader_context *si_shader_ctx)
974 {
975 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
976 struct gallivm_state * gallivm = bld_base->base.gallivm;
977 const struct tgsi_shader_info * info = bld_base->info;
978
979 unsigned i, num_const = info->file_max[TGSI_FILE_CONSTANT] + 1;
980
981 LLVMValueRef ptr;
982
983 if (num_const == 0)
984 return;
985
986 /* Allocate space for the constant values */
987 si_shader_ctx->constants = CALLOC(num_const * 4, sizeof(LLVMValueRef));
988
989 /* Load the resource descriptor */
990 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
991 si_shader_ctx->const_resource = build_indexed_load(si_shader_ctx, ptr, bld_base->uint_bld.zero);
992
993 /* Load the constants, we rely on the code sinking to do the rest */
994 for (i = 0; i < num_const * 4; ++i) {
995 LLVMValueRef args[2] = {
996 si_shader_ctx->const_resource,
997 lp_build_const_int32(gallivm, i * 4)
998 };
999 si_shader_ctx->constants[i] = build_intrinsic(gallivm->builder, "llvm.SI.load.const",
1000 bld_base->base.elem_type, args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1001 }
1002 }
1003
1004 static void preload_samplers(struct si_shader_context *si_shader_ctx)
1005 {
1006 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1007 struct gallivm_state * gallivm = bld_base->base.gallivm;
1008 const struct tgsi_shader_info * info = bld_base->info;
1009
1010 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
1011
1012 LLVMValueRef res_ptr, samp_ptr;
1013 LLVMValueRef offset;
1014
1015 if (num_samplers == 0)
1016 return;
1017
1018 /* Allocate space for the values */
1019 si_shader_ctx->resources = CALLOC(num_samplers, sizeof(LLVMValueRef));
1020 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
1021
1022 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
1023 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
1024
1025 /* Load the resources and samplers, we rely on the code sinking to do the rest */
1026 for (i = 0; i < num_samplers; ++i) {
1027
1028 /* Resource */
1029 offset = lp_build_const_int32(gallivm, i);
1030 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
1031
1032 /* Sampler */
1033 offset = lp_build_const_int32(gallivm, i);
1034 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
1035 }
1036 }
1037
1038 int si_pipe_shader_create(
1039 struct pipe_context *ctx,
1040 struct si_pipe_shader *shader,
1041 struct si_shader_key key)
1042 {
1043 struct r600_context *rctx = (struct r600_context*)ctx;
1044 struct si_pipe_shader_selector *sel = shader->selector;
1045 struct si_shader_context si_shader_ctx;
1046 struct tgsi_shader_info shader_info;
1047 struct lp_build_tgsi_context * bld_base;
1048 LLVMModuleRef mod;
1049 unsigned char * inst_bytes;
1050 unsigned inst_byte_count;
1051 unsigned i;
1052 uint32_t *ptr;
1053 bool dump;
1054
1055 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
1056
1057 assert(shader->shader.noutput == 0);
1058 assert(shader->shader.ninterp == 0);
1059 assert(shader->shader.ninput == 0);
1060
1061 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
1062 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
1063 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
1064
1065 tgsi_scan_shader(sel->tokens, &shader_info);
1066 shader->shader.uses_kill = shader_info.uses_kill;
1067 bld_base->info = &shader_info;
1068 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
1069 bld_base->emit_epilogue = si_llvm_emit_epilogue;
1070
1071 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1072 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
1073 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
1074 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
1075
1076 si_shader_ctx.radeon_bld.load_input = declare_input;
1077 si_shader_ctx.tokens = sel->tokens;
1078 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
1079 si_shader_ctx.shader = shader;
1080 si_shader_ctx.key = key;
1081 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
1082 si_shader_ctx.rctx = rctx;
1083
1084 create_meta_data(&si_shader_ctx);
1085 create_function(&si_shader_ctx);
1086 preload_constants(&si_shader_ctx);
1087 preload_samplers(&si_shader_ctx);
1088
1089 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
1090
1091 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
1092 * conversion fails. */
1093 if (dump) {
1094 tgsi_dump(sel->tokens, 0);
1095 }
1096
1097 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
1098 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
1099 FREE(si_shader_ctx.constants);
1100 FREE(si_shader_ctx.resources);
1101 FREE(si_shader_ctx.samplers);
1102 return -EINVAL;
1103 }
1104
1105 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
1106
1107 mod = bld_base->base.gallivm->module;
1108 if (dump) {
1109 LLVMDumpModule(mod);
1110 }
1111 radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count, "SI", dump);
1112 if (dump) {
1113 fprintf(stderr, "SI CODE:\n");
1114 for (i = 0; i < inst_byte_count; i+=4 ) {
1115 fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3],
1116 inst_bytes[i + 2], inst_bytes[i + 1],
1117 inst_bytes[i]);
1118 }
1119 }
1120
1121 shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes);
1122 shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4));
1123 shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8));
1124
1125 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
1126 tgsi_parse_free(&si_shader_ctx.parse);
1127
1128 /* copy new shader */
1129 si_resource_reference(&shader->bo, NULL);
1130 shader->bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
1131 inst_byte_count - 12);
1132 if (shader->bo == NULL) {
1133 FREE(si_shader_ctx.constants);
1134 FREE(si_shader_ctx.resources);
1135 FREE(si_shader_ctx.samplers);
1136 return -ENOMEM;
1137 }
1138
1139 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1140 if (0 /*R600_BIG_ENDIAN*/) {
1141 for (i = 0; i < (inst_byte_count-12)/4; ++i) {
1142 ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4));
1143 }
1144 } else {
1145 memcpy(ptr, inst_bytes + 12, inst_byte_count - 12);
1146 }
1147 rctx->ws->buffer_unmap(shader->bo->cs_buf);
1148
1149 FREE(si_shader_ctx.constants);
1150 FREE(si_shader_ctx.resources);
1151 FREE(si_shader_ctx.samplers);
1152 free(inst_bytes);
1153
1154 return 0;
1155 }
1156
1157 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
1158 {
1159 si_resource_reference(&shader->bo, NULL);
1160 }