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radeonsi: mark all loads as constant
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "gallivm/lp_bld_arit.h"
37 #include "radeon_llvm.h"
38 #include "radeon_llvm_emit.h"
39 #include "tgsi/tgsi_info.h"
40 #include "tgsi/tgsi_parse.h"
41 #include "tgsi/tgsi_scan.h"
42 #include "tgsi/tgsi_dump.h"
43
44 #include "radeonsi_pipe.h"
45 #include "radeonsi_shader.h"
46 #include "si_state.h"
47 #include "sid.h"
48
49 #include <assert.h>
50 #include <errno.h>
51 #include <stdio.h>
52
53 struct si_shader_context
54 {
55 struct radeon_llvm_context radeon_bld;
56 struct r600_context *rctx;
57 struct tgsi_parse_context parse;
58 struct tgsi_token * tokens;
59 struct si_pipe_shader *shader;
60 struct si_shader_key key;
61 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
62 LLVMValueRef const_md;
63 /* struct list_head inputs; */
64 /* unsigned * input_mappings *//* From TGSI to SI hw */
65 /* struct tgsi_shader_info info;*/
66 };
67
68 static struct si_shader_context * si_shader_context(
69 struct lp_build_tgsi_context * bld_base)
70 {
71 return (struct si_shader_context *)bld_base;
72 }
73
74
75 #define PERSPECTIVE_BASE 0
76 #define LINEAR_BASE 9
77
78 #define SAMPLE_OFFSET 0
79 #define CENTER_OFFSET 2
80 #define CENTROID_OFSET 4
81
82 #define USE_SGPR_MAX_SUFFIX_LEN 5
83 #define CONST_ADDR_SPACE 2
84 #define USER_SGPR_ADDR_SPACE 8
85
86 /**
87 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
88 *
89 * @param offset The offset parameter specifies the number of
90 * elements to offset, not the number of bytes or dwords. An element is the
91 * the type pointed to by the base_ptr parameter (e.g. int is the element of
92 * an int* pointer)
93 *
94 * When LLVM lowers the load instruction, it will convert the element offset
95 * into a dword offset automatically.
96 *
97 */
98 static LLVMValueRef build_indexed_load(
99 struct si_shader_context * si_shader_ctx,
100 LLVMValueRef base_ptr,
101 LLVMValueRef offset)
102 {
103 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
104
105 LLVMValueRef computed_ptr = LLVMBuildGEP(
106 base->gallivm->builder, base_ptr, &offset, 1, "");
107
108 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
109 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
110 return result;
111 }
112
113 static void declare_input_vs(
114 struct si_shader_context * si_shader_ctx,
115 unsigned input_index,
116 const struct tgsi_full_declaration *decl)
117 {
118 LLVMValueRef t_list_ptr;
119 LLVMValueRef t_offset;
120 LLVMValueRef t_list;
121 LLVMValueRef attribute_offset;
122 LLVMValueRef buffer_index_reg;
123 LLVMValueRef args[3];
124 LLVMTypeRef vec4_type;
125 LLVMValueRef input;
126 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
127 //struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[input_index];
128 unsigned chan;
129
130 /* Load the T list */
131 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
132
133 t_offset = lp_build_const_int32(base->gallivm, input_index);
134
135 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
136
137 /* Build the attribute offset */
138 attribute_offset = lp_build_const_int32(base->gallivm, 0);
139
140 /* Load the buffer index, which is always stored in VGPR0
141 * for Vertex Shaders */
142 buffer_index_reg = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_INDEX);
143
144 vec4_type = LLVMVectorType(base->elem_type, 4);
145 args[0] = t_list;
146 args[1] = attribute_offset;
147 args[2] = buffer_index_reg;
148 input = lp_build_intrinsic(base->gallivm->builder,
149 "llvm.SI.vs.load.input", vec4_type, args, 3);
150
151 /* Break up the vec4 into individual components */
152 for (chan = 0; chan < 4; chan++) {
153 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
154 /* XXX: Use a helper function for this. There is one in
155 * tgsi_llvm.c. */
156 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
157 LLVMBuildExtractElement(base->gallivm->builder,
158 input, llvm_chan, "");
159 }
160 }
161
162 static void declare_input_fs(
163 struct si_shader_context * si_shader_ctx,
164 unsigned input_index,
165 const struct tgsi_full_declaration *decl)
166 {
167 struct si_shader *shader = &si_shader_ctx->shader->shader;
168 struct lp_build_context * base =
169 &si_shader_ctx->radeon_bld.soa.bld_base.base;
170 struct gallivm_state * gallivm = base->gallivm;
171 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
172 LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
173
174 LLVMValueRef interp_param;
175 const char * intr_name;
176
177 /* This value is:
178 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
179 * quad begins a new primitive. Bit 0 always needs
180 * to be unset)
181 * [32:16] ParamOffset
182 *
183 */
184 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
185 LLVMValueRef attr_number;
186
187 unsigned chan;
188
189 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
190 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
191 unsigned soa_index =
192 radeon_llvm_reg_index_soa(input_index, chan);
193 si_shader_ctx->radeon_bld.inputs[soa_index] =
194 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
195
196 if (chan == 3)
197 /* RCP for fragcoord.w */
198 si_shader_ctx->radeon_bld.inputs[soa_index] =
199 LLVMBuildFDiv(gallivm->builder,
200 lp_build_const_float(gallivm, 1.0f),
201 si_shader_ctx->radeon_bld.inputs[soa_index],
202 "");
203 }
204 return;
205 }
206
207 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
208 LLVMValueRef face, is_face_positive;
209
210 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
211
212 is_face_positive = LLVMBuildFCmp(gallivm->builder,
213 LLVMRealUGT, face,
214 lp_build_const_float(gallivm, 0.0f),
215 "");
216
217 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
218 LLVMBuildSelect(gallivm->builder,
219 is_face_positive,
220 lp_build_const_float(gallivm, 1.0f),
221 lp_build_const_float(gallivm, 0.0f),
222 "");
223 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
224 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
225 lp_build_const_float(gallivm, 0.0f);
226 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
227 lp_build_const_float(gallivm, 1.0f);
228
229 return;
230 }
231
232 shader->input[input_index].param_offset = shader->ninterp++;
233 attr_number = lp_build_const_int32(gallivm,
234 shader->input[input_index].param_offset);
235
236 /* XXX: Handle all possible interpolation modes */
237 switch (decl->Interp.Interpolate) {
238 case TGSI_INTERPOLATE_COLOR:
239 if (si_shader_ctx->key.flatshade) {
240 interp_param = 0;
241 } else {
242 if (decl->Interp.Centroid)
243 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
244 else
245 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
246 }
247 break;
248 case TGSI_INTERPOLATE_CONSTANT:
249 interp_param = 0;
250 break;
251 case TGSI_INTERPOLATE_LINEAR:
252 if (decl->Interp.Centroid)
253 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
254 else
255 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
256 break;
257 case TGSI_INTERPOLATE_PERSPECTIVE:
258 if (decl->Interp.Centroid)
259 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
260 else
261 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
262 break;
263 default:
264 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
265 return;
266 }
267
268 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
269
270 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
271 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
272 si_shader_ctx->key.color_two_side) {
273 LLVMValueRef args[4];
274 LLVMValueRef face, is_face_positive;
275 LLVMValueRef back_attr_number =
276 lp_build_const_int32(gallivm,
277 shader->input[input_index].param_offset + 1);
278
279 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
280
281 is_face_positive = LLVMBuildFCmp(gallivm->builder,
282 LLVMRealUGT, face,
283 lp_build_const_float(gallivm, 0.0f),
284 "");
285
286 args[2] = params;
287 args[3] = interp_param;
288 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
289 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
290 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
291 LLVMValueRef front, back;
292
293 args[0] = llvm_chan;
294 args[1] = attr_number;
295 front = build_intrinsic(base->gallivm->builder, intr_name,
296 input_type, args, args[3] ? 4 : 3,
297 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
298
299 args[1] = back_attr_number;
300 back = build_intrinsic(base->gallivm->builder, intr_name,
301 input_type, args, args[3] ? 4 : 3,
302 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
303
304 si_shader_ctx->radeon_bld.inputs[soa_index] =
305 LLVMBuildSelect(gallivm->builder,
306 is_face_positive,
307 front,
308 back,
309 "");
310 }
311
312 shader->ninterp++;
313 } else {
314 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
315 LLVMValueRef args[4];
316 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
317 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
318 args[0] = llvm_chan;
319 args[1] = attr_number;
320 args[2] = params;
321 args[3] = interp_param;
322 si_shader_ctx->radeon_bld.inputs[soa_index] =
323 build_intrinsic(base->gallivm->builder, intr_name,
324 input_type, args, args[3] ? 4 : 3,
325 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
326 }
327 }
328 }
329
330 static void declare_input(
331 struct radeon_llvm_context * radeon_bld,
332 unsigned input_index,
333 const struct tgsi_full_declaration *decl)
334 {
335 struct si_shader_context * si_shader_ctx =
336 si_shader_context(&radeon_bld->soa.bld_base);
337 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
338 declare_input_vs(si_shader_ctx, input_index, decl);
339 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
340 declare_input_fs(si_shader_ctx, input_index, decl);
341 } else {
342 fprintf(stderr, "Warning: Unsupported shader type,\n");
343 }
344 }
345
346 static LLVMValueRef fetch_constant(
347 struct lp_build_tgsi_context * bld_base,
348 const struct tgsi_full_src_register *reg,
349 enum tgsi_opcode_type type,
350 unsigned swizzle)
351 {
352 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
353 struct lp_build_context * base = &bld_base->base;
354
355 LLVMValueRef ptr;
356 LLVMValueRef args[2];
357 LLVMValueRef result;
358
359 if (swizzle == LP_CHAN_ALL) {
360 unsigned chan;
361 LLVMValueRef values[4];
362 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
363 values[chan] = fetch_constant(bld_base, reg, type, chan);
364
365 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
366 }
367
368 /* Load the resource descriptor */
369 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
370 args[0] = build_indexed_load(si_shader_ctx, ptr, bld_base->uint_bld.zero);
371
372 args[1] = lp_build_const_int32(base->gallivm, (reg->Register.Index * 4 + swizzle) * 4);
373 if (reg->Register.Indirect) {
374 const struct tgsi_ind_register *ireg = &reg->Indirect;
375 LLVMValueRef addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
376 LLVMValueRef idx = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
377 idx = lp_build_mul_imm(&bld_base->uint_bld, idx, 16);
378 args[1] = lp_build_add(&bld_base->uint_bld, idx, args[1]);
379 }
380
381 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
382 args, 2, LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
383
384 return bitcast(bld_base, type, result);
385 }
386
387 /* Initialize arguments for the shader export intrinsic */
388 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
389 struct tgsi_full_declaration *d,
390 unsigned index,
391 unsigned target,
392 LLVMValueRef *args)
393 {
394 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
395 struct lp_build_context *uint =
396 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
397 struct lp_build_context *base = &bld_base->base;
398 unsigned compressed = 0;
399 unsigned chan;
400
401 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
402 int cbuf = target - V_008DFC_SQ_EXP_MRT;
403
404 if (cbuf >= 0 && cbuf < 8) {
405 compressed = (si_shader_ctx->key.export_16bpc >> cbuf) & 0x1;
406
407 if (compressed)
408 si_shader_ctx->shader->spi_shader_col_format |=
409 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
410 else
411 si_shader_ctx->shader->spi_shader_col_format |=
412 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
413 }
414 }
415
416 if (compressed) {
417 /* Pixel shader needs to pack output values before export */
418 for (chan = 0; chan < 2; chan++ ) {
419 LLVMValueRef *out_ptr =
420 si_shader_ctx->radeon_bld.soa.outputs[index];
421 args[0] = LLVMBuildLoad(base->gallivm->builder,
422 out_ptr[2 * chan], "");
423 args[1] = LLVMBuildLoad(base->gallivm->builder,
424 out_ptr[2 * chan + 1], "");
425 args[chan + 5] =
426 build_intrinsic(base->gallivm->builder,
427 "llvm.SI.packf16",
428 LLVMInt32TypeInContext(base->gallivm->context),
429 args, 2,
430 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
431 args[chan + 7] = args[chan + 5] =
432 LLVMBuildBitCast(base->gallivm->builder,
433 args[chan + 5],
434 LLVMFloatTypeInContext(base->gallivm->context),
435 "");
436 }
437
438 /* Set COMPR flag */
439 args[4] = uint->one;
440 } else {
441 for (chan = 0; chan < 4; chan++ ) {
442 LLVMValueRef out_ptr =
443 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
444 /* +5 because the first output value will be
445 * the 6th argument to the intrinsic. */
446 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
447 out_ptr, "");
448 }
449
450 /* Clear COMPR flag */
451 args[4] = uint->zero;
452 }
453
454 /* XXX: This controls which components of the output
455 * registers actually get exported. (e.g bit 0 means export
456 * X component, bit 1 means export Y component, etc.) I'm
457 * hard coding this to 0xf for now. In the future, we might
458 * want to do something else. */
459 args[0] = lp_build_const_int32(base->gallivm, 0xf);
460
461 /* Specify whether the EXEC mask represents the valid mask */
462 args[1] = uint->zero;
463
464 /* Specify whether this is the last export */
465 args[2] = uint->zero;
466
467 /* Specify the target we are exporting */
468 args[3] = lp_build_const_int32(base->gallivm, target);
469
470 /* XXX: We probably need to keep track of the output
471 * values, so we know what we are passing to the next
472 * stage. */
473 }
474
475 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
476 unsigned index)
477 {
478 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
479 struct gallivm_state *gallivm = bld_base->base.gallivm;
480
481 if (si_shader_ctx->key.alpha_func != PIPE_FUNC_NEVER) {
482 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
483 LLVMValueRef alpha_pass =
484 lp_build_cmp(&bld_base->base,
485 si_shader_ctx->key.alpha_func,
486 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
487 lp_build_const_float(gallivm, si_shader_ctx->key.alpha_ref));
488 LLVMValueRef arg =
489 lp_build_select(&bld_base->base,
490 alpha_pass,
491 lp_build_const_float(gallivm, 1.0f),
492 lp_build_const_float(gallivm, -1.0f));
493
494 build_intrinsic(gallivm->builder,
495 "llvm.AMDGPU.kill",
496 LLVMVoidTypeInContext(gallivm->context),
497 &arg, 1, 0);
498 } else {
499 build_intrinsic(gallivm->builder,
500 "llvm.AMDGPU.kilp",
501 LLVMVoidTypeInContext(gallivm->context),
502 NULL, 0, 0);
503 }
504 }
505
506 /* XXX: This is partially implemented for VS only at this point. It is not complete */
507 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
508 {
509 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
510 struct si_shader * shader = &si_shader_ctx->shader->shader;
511 struct lp_build_context * base = &bld_base->base;
512 struct lp_build_context * uint =
513 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
514 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
515 LLVMValueRef args[9];
516 LLVMValueRef last_args[9] = { 0 };
517 unsigned color_count = 0;
518 unsigned param_count = 0;
519 int depth_index = -1, stencil_index = -1;
520
521 while (!tgsi_parse_end_of_tokens(parse)) {
522 struct tgsi_full_declaration *d =
523 &parse->FullToken.FullDeclaration;
524 unsigned target;
525 unsigned index;
526 int i;
527
528 tgsi_parse_token(parse);
529
530 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
531 parse->FullToken.FullProperty.Property.PropertyName ==
532 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
533 shader->fs_write_all = TRUE;
534
535 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
536 continue;
537
538 switch (d->Declaration.File) {
539 case TGSI_FILE_INPUT:
540 i = shader->ninput++;
541 shader->input[i].name = d->Semantic.Name;
542 shader->input[i].sid = d->Semantic.Index;
543 shader->input[i].interpolate = d->Interp.Interpolate;
544 shader->input[i].centroid = d->Interp.Centroid;
545 continue;
546
547 case TGSI_FILE_OUTPUT:
548 i = shader->noutput++;
549 shader->output[i].name = d->Semantic.Name;
550 shader->output[i].sid = d->Semantic.Index;
551 shader->output[i].interpolate = d->Interp.Interpolate;
552 break;
553
554 default:
555 continue;
556 }
557
558 for (index = d->Range.First; index <= d->Range.Last; index++) {
559 /* Select the correct target */
560 switch(d->Semantic.Name) {
561 case TGSI_SEMANTIC_PSIZE:
562 target = V_008DFC_SQ_EXP_POS;
563 break;
564 case TGSI_SEMANTIC_POSITION:
565 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
566 target = V_008DFC_SQ_EXP_POS;
567 break;
568 } else {
569 depth_index = index;
570 continue;
571 }
572 case TGSI_SEMANTIC_STENCIL:
573 stencil_index = index;
574 continue;
575 case TGSI_SEMANTIC_COLOR:
576 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
577 case TGSI_SEMANTIC_BCOLOR:
578 target = V_008DFC_SQ_EXP_PARAM + param_count;
579 shader->output[i].param_offset = param_count;
580 param_count++;
581 } else {
582 target = V_008DFC_SQ_EXP_MRT + color_count;
583 if (color_count == 0 &&
584 si_shader_ctx->key.alpha_func != PIPE_FUNC_ALWAYS)
585 si_alpha_test(bld_base, index);
586
587 color_count++;
588 }
589 break;
590 case TGSI_SEMANTIC_FOG:
591 case TGSI_SEMANTIC_GENERIC:
592 target = V_008DFC_SQ_EXP_PARAM + param_count;
593 shader->output[i].param_offset = param_count;
594 param_count++;
595 break;
596 default:
597 target = 0;
598 fprintf(stderr,
599 "Warning: SI unhandled output type:%d\n",
600 d->Semantic.Name);
601 }
602
603 si_llvm_init_export_args(bld_base, d, index, target, args);
604
605 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
606 (d->Semantic.Name == TGSI_SEMANTIC_POSITION) :
607 (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) {
608 if (last_args[0]) {
609 lp_build_intrinsic(base->gallivm->builder,
610 "llvm.SI.export",
611 LLVMVoidTypeInContext(base->gallivm->context),
612 last_args, 9);
613 }
614
615 memcpy(last_args, args, sizeof(args));
616 } else {
617 lp_build_intrinsic(base->gallivm->builder,
618 "llvm.SI.export",
619 LLVMVoidTypeInContext(base->gallivm->context),
620 args, 9);
621 }
622
623 }
624 }
625
626 if (depth_index >= 0 || stencil_index >= 0) {
627 LLVMValueRef out_ptr;
628 unsigned mask = 0;
629
630 /* Specify the target we are exporting */
631 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
632
633 if (depth_index >= 0) {
634 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
635 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
636 mask |= 0x1;
637
638 if (stencil_index < 0) {
639 args[6] =
640 args[7] =
641 args[8] = args[5];
642 }
643 }
644
645 if (stencil_index >= 0) {
646 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
647 args[7] =
648 args[8] =
649 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
650 mask |= 0x2;
651
652 if (depth_index < 0)
653 args[5] = args[6];
654 }
655
656 /* Specify which components to enable */
657 args[0] = lp_build_const_int32(base->gallivm, mask);
658
659 args[1] =
660 args[2] =
661 args[4] = uint->zero;
662
663 if (last_args[0])
664 lp_build_intrinsic(base->gallivm->builder,
665 "llvm.SI.export",
666 LLVMVoidTypeInContext(base->gallivm->context),
667 args, 9);
668 else
669 memcpy(last_args, args, sizeof(args));
670 }
671
672 if (!last_args[0]) {
673 assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
674
675 /* Specify which components to enable */
676 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
677
678 /* Specify the target we are exporting */
679 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
680
681 /* Set COMPR flag to zero to export data as 32-bit */
682 last_args[4] = uint->zero;
683
684 /* dummy bits */
685 last_args[5]= uint->zero;
686 last_args[6]= uint->zero;
687 last_args[7]= uint->zero;
688 last_args[8]= uint->zero;
689
690 si_shader_ctx->shader->spi_shader_col_format |=
691 V_028714_SPI_SHADER_32_ABGR;
692 }
693
694 /* Specify whether the EXEC mask represents the valid mask */
695 last_args[1] = lp_build_const_int32(base->gallivm,
696 si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
697
698 if (shader->fs_write_all && shader->nr_cbufs > 1) {
699 int i;
700
701 /* Specify that this is not yet the last export */
702 last_args[2] = lp_build_const_int32(base->gallivm, 0);
703
704 for (i = 1; i < shader->nr_cbufs; i++) {
705 /* Specify the target we are exporting */
706 last_args[3] = lp_build_const_int32(base->gallivm,
707 V_008DFC_SQ_EXP_MRT + i);
708
709 lp_build_intrinsic(base->gallivm->builder,
710 "llvm.SI.export",
711 LLVMVoidTypeInContext(base->gallivm->context),
712 last_args, 9);
713
714 si_shader_ctx->shader->spi_shader_col_format |=
715 si_shader_ctx->shader->spi_shader_col_format << 4;
716 }
717
718 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
719 }
720
721 /* Specify that this is the last export */
722 last_args[2] = lp_build_const_int32(base->gallivm, 1);
723
724 lp_build_intrinsic(base->gallivm->builder,
725 "llvm.SI.export",
726 LLVMVoidTypeInContext(base->gallivm->context),
727 last_args, 9);
728
729 /* XXX: Look up what this function does */
730 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
731 }
732
733 static void tex_fetch_args(
734 struct lp_build_tgsi_context * bld_base,
735 struct lp_build_emit_data * emit_data)
736 {
737 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
738 struct gallivm_state *gallivm = bld_base->base.gallivm;
739 const struct tgsi_full_instruction * inst = emit_data->inst;
740 unsigned opcode = inst->Instruction.Opcode;
741 unsigned target = inst->Texture.Texture;
742 LLVMValueRef ptr;
743 LLVMValueRef offset;
744 LLVMValueRef coords[4];
745 LLVMValueRef address[16];
746 unsigned count = 0;
747 unsigned chan;
748
749 /* WriteMask */
750 /* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
751 emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm, 0xf);
752
753 /* Fetch and project texture coordinates */
754 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
755 for (chan = 0; chan < 3; chan++ ) {
756 coords[chan] = lp_build_emit_fetch(bld_base,
757 emit_data->inst, 0,
758 chan);
759 if (opcode == TGSI_OPCODE_TXP)
760 coords[chan] = lp_build_emit_llvm_binary(bld_base,
761 TGSI_OPCODE_DIV,
762 coords[chan],
763 coords[3]);
764 }
765
766 if (opcode == TGSI_OPCODE_TXP)
767 coords[3] = bld_base->base.one;
768
769 /* Pack LOD bias value */
770 if (opcode == TGSI_OPCODE_TXB)
771 address[count++] = coords[3];
772
773 if ((target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE) &&
774 opcode != TGSI_OPCODE_TXQ)
775 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
776
777 /* Pack depth comparison value */
778 switch (target) {
779 case TGSI_TEXTURE_SHADOW1D:
780 case TGSI_TEXTURE_SHADOW1D_ARRAY:
781 case TGSI_TEXTURE_SHADOW2D:
782 case TGSI_TEXTURE_SHADOWRECT:
783 address[count++] = coords[2];
784 break;
785 case TGSI_TEXTURE_SHADOWCUBE:
786 case TGSI_TEXTURE_SHADOW2D_ARRAY:
787 address[count++] = coords[3];
788 break;
789 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
790 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
791 }
792
793 /* Pack texture coordinates */
794 address[count++] = coords[0];
795 switch (target) {
796 case TGSI_TEXTURE_2D:
797 case TGSI_TEXTURE_2D_ARRAY:
798 case TGSI_TEXTURE_3D:
799 case TGSI_TEXTURE_CUBE:
800 case TGSI_TEXTURE_RECT:
801 case TGSI_TEXTURE_SHADOW2D:
802 case TGSI_TEXTURE_SHADOWRECT:
803 case TGSI_TEXTURE_SHADOW2D_ARRAY:
804 case TGSI_TEXTURE_SHADOWCUBE:
805 case TGSI_TEXTURE_2D_MSAA:
806 case TGSI_TEXTURE_2D_ARRAY_MSAA:
807 case TGSI_TEXTURE_CUBE_ARRAY:
808 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
809 address[count++] = coords[1];
810 }
811 switch (target) {
812 case TGSI_TEXTURE_3D:
813 case TGSI_TEXTURE_CUBE:
814 case TGSI_TEXTURE_SHADOWCUBE:
815 case TGSI_TEXTURE_CUBE_ARRAY:
816 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
817 address[count++] = coords[2];
818 }
819
820 /* Pack array slice */
821 switch (target) {
822 case TGSI_TEXTURE_1D_ARRAY:
823 address[count++] = coords[1];
824 }
825 switch (target) {
826 case TGSI_TEXTURE_2D_ARRAY:
827 case TGSI_TEXTURE_2D_ARRAY_MSAA:
828 case TGSI_TEXTURE_SHADOW2D_ARRAY:
829 address[count++] = coords[2];
830 }
831 switch (target) {
832 case TGSI_TEXTURE_CUBE_ARRAY:
833 case TGSI_TEXTURE_SHADOW1D_ARRAY:
834 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
835 address[count++] = coords[3];
836 }
837
838 /* Pack LOD */
839 if (opcode == TGSI_OPCODE_TXL)
840 address[count++] = coords[3];
841
842 if (count > 16) {
843 assert(!"Cannot handle more than 16 texture address parameters");
844 count = 16;
845 }
846
847 for (chan = 0; chan < count; chan++ ) {
848 address[chan] = LLVMBuildBitCast(gallivm->builder,
849 address[chan],
850 LLVMInt32TypeInContext(gallivm->context),
851 "");
852 }
853
854 /* Pad to power of two vector */
855 while (count < util_next_power_of_two(count))
856 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
857
858 emit_data->args[1] = lp_build_gather_values(gallivm, address, count);
859
860 /* Resource */
861 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
862 offset = lp_build_const_int32(bld_base->base.gallivm,
863 emit_data->inst->Src[1].Register.Index);
864 emit_data->args[2] = build_indexed_load(si_shader_ctx,
865 ptr, offset);
866
867 /* Sampler */
868 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
869 offset = lp_build_const_int32(bld_base->base.gallivm,
870 emit_data->inst->Src[1].Register.Index);
871 emit_data->args[3] = build_indexed_load(si_shader_ctx,
872 ptr, offset);
873
874 /* Dimensions */
875 emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm, target);
876
877 emit_data->arg_count = 5;
878 /* XXX: To optimize, we could use a float or v2f32, if the last bits of
879 * the writemask are clear */
880 emit_data->dst_type = LLVMVectorType(
881 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
882 4);
883 }
884
885 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
886 struct lp_build_tgsi_context * bld_base,
887 struct lp_build_emit_data * emit_data)
888 {
889 struct lp_build_context * base = &bld_base->base;
890 char intr_name[23];
891
892 sprintf(intr_name, "%sv%ui32", action->intr_name,
893 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[1])));
894
895 emit_data->output[emit_data->chan] = lp_build_intrinsic(
896 base->gallivm->builder, intr_name, emit_data->dst_type,
897 emit_data->args, emit_data->arg_count);
898 }
899
900 static const struct lp_build_tgsi_action tex_action = {
901 .fetch_args = tex_fetch_args,
902 .emit = build_tex_intrinsic,
903 .intr_name = "llvm.SI.sample."
904 };
905
906 static const struct lp_build_tgsi_action txb_action = {
907 .fetch_args = tex_fetch_args,
908 .emit = build_tex_intrinsic,
909 .intr_name = "llvm.SI.sampleb."
910 };
911
912 static const struct lp_build_tgsi_action txl_action = {
913 .fetch_args = tex_fetch_args,
914 .emit = build_tex_intrinsic,
915 .intr_name = "llvm.SI.samplel."
916 };
917
918 static void create_meta_data(struct si_shader_context *si_shader_ctx)
919 {
920 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
921 LLVMValueRef args[3];
922
923 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
924 args[1] = 0;
925 args[2] = lp_build_const_int32(gallivm, 1);
926
927 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
928 }
929
930 static void create_function(struct si_shader_context *si_shader_ctx)
931 {
932 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
933 LLVMTypeRef params[20], f32, i8, i32, v2i32, v3i32;
934 unsigned i;
935
936 i8 = LLVMInt8TypeInContext(gallivm->context);
937 i32 = LLVMInt32TypeInContext(gallivm->context);
938 f32 = LLVMFloatTypeInContext(gallivm->context);
939 v2i32 = LLVMVectorType(i32, 2);
940 v3i32 = LLVMVectorType(i32, 3);
941
942 params[SI_PARAM_CONST] = LLVMPointerType(LLVMVectorType(i8, 16), CONST_ADDR_SPACE);
943 params[SI_PARAM_SAMPLER] = params[SI_PARAM_CONST];
944 params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), CONST_ADDR_SPACE);
945
946 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
947 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
948 params[SI_PARAM_VERTEX_INDEX] = i32;
949 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 5);
950
951 } else {
952 params[SI_PARAM_PRIM_MASK] = i32;
953 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
954 params[SI_PARAM_PERSP_CENTER] = v2i32;
955 params[SI_PARAM_PERSP_CENTROID] = v2i32;
956 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
957 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
958 params[SI_PARAM_LINEAR_CENTER] = v2i32;
959 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
960 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
961 params[SI_PARAM_POS_X_FLOAT] = f32;
962 params[SI_PARAM_POS_Y_FLOAT] = f32;
963 params[SI_PARAM_POS_Z_FLOAT] = f32;
964 params[SI_PARAM_POS_W_FLOAT] = f32;
965 params[SI_PARAM_FRONT_FACE] = f32;
966 params[SI_PARAM_ANCILLARY] = f32;
967 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
968 params[SI_PARAM_POS_FIXED_PT] = f32;
969 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 20);
970 }
971
972 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
973 for (i = SI_PARAM_CONST; i <= SI_PARAM_VERTEX_BUFFER; ++i) {
974 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
975 LLVMAddAttribute(P, LLVMInRegAttribute);
976 }
977 }
978
979 int si_pipe_shader_create(
980 struct pipe_context *ctx,
981 struct si_pipe_shader *shader,
982 struct si_shader_key key)
983 {
984 struct r600_context *rctx = (struct r600_context*)ctx;
985 struct si_pipe_shader_selector *sel = shader->selector;
986 struct si_shader_context si_shader_ctx;
987 struct tgsi_shader_info shader_info;
988 struct lp_build_tgsi_context * bld_base;
989 LLVMModuleRef mod;
990 unsigned char * inst_bytes;
991 unsigned inst_byte_count;
992 unsigned i;
993 uint32_t *ptr;
994 bool dump;
995
996 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
997
998 assert(shader->shader.noutput == 0);
999 assert(shader->shader.ninterp == 0);
1000 assert(shader->shader.ninput == 0);
1001
1002 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
1003 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
1004 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
1005
1006 tgsi_scan_shader(sel->tokens, &shader_info);
1007 shader->shader.uses_kill = shader_info.uses_kill;
1008 bld_base->info = &shader_info;
1009 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
1010 bld_base->emit_epilogue = si_llvm_emit_epilogue;
1011
1012 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1013 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
1014 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
1015 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
1016
1017 si_shader_ctx.radeon_bld.load_input = declare_input;
1018 si_shader_ctx.tokens = sel->tokens;
1019 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
1020 si_shader_ctx.shader = shader;
1021 si_shader_ctx.key = key;
1022 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
1023 si_shader_ctx.rctx = rctx;
1024
1025 create_meta_data(&si_shader_ctx);
1026 create_function(&si_shader_ctx);
1027
1028 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
1029
1030 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
1031 * conversion fails. */
1032 if (dump) {
1033 tgsi_dump(sel->tokens, 0);
1034 }
1035
1036 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
1037 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
1038 return -EINVAL;
1039 }
1040
1041 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
1042
1043 mod = bld_base->base.gallivm->module;
1044 if (dump) {
1045 LLVMDumpModule(mod);
1046 }
1047 radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count, "SI", dump);
1048 if (dump) {
1049 fprintf(stderr, "SI CODE:\n");
1050 for (i = 0; i < inst_byte_count; i+=4 ) {
1051 fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3],
1052 inst_bytes[i + 2], inst_bytes[i + 1],
1053 inst_bytes[i]);
1054 }
1055 }
1056
1057 shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes);
1058 shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4));
1059 shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8));
1060
1061 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
1062 tgsi_parse_free(&si_shader_ctx.parse);
1063
1064 /* copy new shader */
1065 si_resource_reference(&shader->bo, NULL);
1066 shader->bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
1067 inst_byte_count - 12);
1068 if (shader->bo == NULL) {
1069 return -ENOMEM;
1070 }
1071
1072 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1073 if (0 /*R600_BIG_ENDIAN*/) {
1074 for (i = 0; i < (inst_byte_count-12)/4; ++i) {
1075 ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4));
1076 }
1077 } else {
1078 memcpy(ptr, inst_bytes + 12, inst_byte_count - 12);
1079 }
1080 rctx->ws->buffer_unmap(shader->bo->cs_buf);
1081
1082 free(inst_bytes);
1083
1084 return 0;
1085 }
1086
1087 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
1088 {
1089 si_resource_reference(&shader->bo, NULL);
1090 }