src/gallium/drivers/radeonsi/radeonsi_shader.c

   1
   2 #include "gallivm/lp_bld_tgsi_action.h"
   3 #include "gallivm/lp_bld_const.h"
   4 #include "gallivm/lp_bld_intr.h"
   5 #include "gallivm/lp_bld_tgsi.h"
   6 #include "radeon_llvm.h"
   7 #include "radeon_llvm_emit.h"
   8 #include "tgsi/tgsi_info.h"
   9 #include "tgsi/tgsi_parse.h"
  10 #include "tgsi/tgsi_scan.h"
  11 #include "tgsi/tgsi_dump.h"
  12
  13 #include "radeonsi_pipe.h"
  14 #include "radeonsi_shader.h"
  15 #include "sid.h"
  16
  17 #include <assert.h>
  18 #include <errno.h>
  19 #include <stdio.h>
  20
  21 /*
  22 static ps_remap_inputs(
  23         struct tgsi_llvm_context * tl_ctx,
  24         unsigned tgsi_index,
  25         unsigned tgsi_chan)
  26 {
  27         :
  28 }
  29
  30 struct si_input
  31 {
  32         struct list_head head;
  33         unsigned tgsi_index;
  34         unsigned tgsi_chan;
  35         unsigned order;
  36 };
  37 */
  38
  39
  40 struct si_shader_context
  41 {
  42         struct radeon_llvm_context radeon_bld;
  43         struct r600_context *rctx;
  44         struct tgsi_parse_context parse;
  45         struct tgsi_token * tokens;
  46         struct si_pipe_shader *shader;
  47         unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
  48 /*      unsigned num_inputs; */
  49 /*      struct list_head inputs; */
  50 /*      unsigned * input_mappings *//* From TGSI to SI hw */
  51 /*      struct tgsi_shader_info info;*/
  52 };
  53
  54 static struct si_shader_context * si_shader_context(
  55         struct lp_build_tgsi_context * bld_base)
  56 {
  57         return (struct si_shader_context *)bld_base;
  58 }
  59
  60
  61 #define PERSPECTIVE_BASE 0
  62 #define LINEAR_BASE 9
  63
  64 #define SAMPLE_OFFSET 0
  65 #define CENTER_OFFSET 2
  66 #define CENTROID_OFSET 4
  67
  68 #define USE_SGPR_MAX_SUFFIX_LEN 5
  69 #define CONST_ADDR_SPACE 2
  70
  71 enum sgpr_type {
  72         SGPR_CONST_PTR_F32,
  73         SGPR_CONST_PTR_V4I32,
  74         SGPR_CONST_PTR_V8I32,
  75         SGPR_I32,
  76         SGPR_I64
  77 };
  78
  79 /**
  80  * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
  81  *
  82  * @param offset The offset parameter specifies the number of
  83  * elements to offset, not the number of bytes or dwords.  An element is the
  84  * the type pointed to by the base_ptr parameter (e.g. int is the element of
  85  * an int* pointer)
  86  *
  87  * When LLVM lowers the load instruction, it will convert the element offset
  88  * into a dword offset automatically.
  89  *
  90  */
  91 static LLVMValueRef build_indexed_load(
  92         struct gallivm_state * gallivm,
  93         LLVMValueRef base_ptr,
  94         LLVMValueRef offset)
  95 {
  96         LLVMValueRef computed_ptr = LLVMBuildGEP(
  97                 gallivm->builder, base_ptr, &offset, 1, "");
  98
  99         return LLVMBuildLoad(gallivm->builder, computed_ptr, "");
 100 }
 101
 102 /*
 103  * XXX: Instead of using an intrinsic to use a specific SGPR, we should be
 104  * using load instructions.  The loads should load from the USER_SGPR address
 105  * space and use the sgpr index as the pointer.
 106  */
 107 static LLVMValueRef use_sgpr(
 108         struct gallivm_state * gallivm,
 109         enum sgpr_type type,
 110         unsigned sgpr)
 111 {
 112         LLVMValueRef sgpr_index;
 113         LLVMTypeRef ret_type;
 114
 115         sgpr_index = lp_build_const_int32(gallivm, sgpr);
 116
 117         switch (type) {
 118         case SGPR_CONST_PTR_F32:
 119                 ret_type = LLVMFloatTypeInContext(gallivm->context);
 120                 ret_type = LLVMPointerType(ret_type, CONST_ADDR_SPACE);
 121                 return lp_build_intrinsic_unary(gallivm->builder,
 122                                                 "llvm.SI.use.sgprptrcf32.",
 123                                                 ret_type, sgpr_index);
 124         case SGPR_I32:
 125                 ret_type = LLVMInt32TypeInContext(gallivm->context);
 126                 return lp_build_intrinsic_unary(gallivm->builder,
 127                                                 "llvm.SI.use.sgpr.i32",
 128                                                 ret_type, sgpr_index);
 129         case SGPR_I64:
 130                 ret_type= LLVMInt64TypeInContext(gallivm->context);
 131                 return lp_build_intrinsic_unary(gallivm->builder,
 132                                 "llvm.SI.use.sgpr.i64",
 133                                  ret_type, sgpr_index);
 134         case SGPR_CONST_PTR_V4I32:
 135                 ret_type = LLVMInt32TypeInContext(gallivm->context);
 136                 ret_type = LLVMVectorType(ret_type, 4);
 137                 ret_type = LLVMPointerType(ret_type, CONST_ADDR_SPACE);
 138                 return lp_build_intrinsic_unary(gallivm->builder,
 139                                                 "llvm.SI.use.sgprptrci128.",
 140                                                 ret_type, sgpr_index);
 141         case SGPR_CONST_PTR_V8I32:
 142                 ret_type = LLVMInt32TypeInContext(gallivm->context);
 143                 ret_type = LLVMVectorType(ret_type, 8);
 144                 ret_type = LLVMPointerType(ret_type, CONST_ADDR_SPACE);
 145                 return lp_build_intrinsic_unary(gallivm->builder,
 146                                                 "llvm.SI.use.sgprptrci256.",
 147                                                 ret_type, sgpr_index);
 148         default:
 149                 assert(!"Unsupported SGPR type in use_sgpr()");
 150                 return NULL;
 151         }
 152 }
 153
 154 static void declare_input_vs(
 155         struct si_shader_context * si_shader_ctx,
 156         unsigned input_index,
 157         const struct tgsi_full_declaration *decl)
 158 {
 159         LLVMValueRef t_list_ptr;
 160         LLVMValueRef t_offset;
 161         LLVMValueRef t_list;
 162         LLVMValueRef attribute_offset;
 163         LLVMValueRef buffer_index_reg;
 164         LLVMValueRef args[3];
 165         LLVMTypeRef vec4_type;
 166         LLVMValueRef input;
 167         struct lp_build_context * uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
 168         struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
 169         struct r600_context *rctx = si_shader_ctx->rctx;
 170         struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[input_index];
 171         unsigned chan;
 172
 173         /* Load the T list */
 174         /* XXX: Communicate with the rest of the driver about which SGPR the T#
 175          * list pointer is going to be stored in.  Hard code to SGPR[6:7] for
 176          * now */
 177         t_list_ptr = use_sgpr(base->gallivm, SGPR_CONST_PTR_V4I32, 3);
 178
 179         t_offset = lp_build_const_int32(base->gallivm, velem->vertex_buffer_index);
 180
 181         t_list = build_indexed_load(base->gallivm, t_list_ptr, t_offset);
 182
 183         /* Build the attribute offset */
 184         attribute_offset = lp_build_const_int32(base->gallivm, velem->src_offset);
 185
 186         /* Load the buffer index is always, which is always stored in VGPR0
 187          * for Vertex Shaders */
 188         buffer_index_reg = lp_build_intrinsic(base->gallivm->builder,
 189                 "llvm.SI.vs.load.buffer.index", uint->elem_type, NULL, 0);
 190
 191         vec4_type = LLVMVectorType(base->elem_type, 4);
 192         args[0] = t_list;
 193         args[1] = attribute_offset;
 194         args[2] = buffer_index_reg;
 195         input = lp_build_intrinsic(base->gallivm->builder,
 196                 "llvm.SI.vs.load.input", vec4_type, args, 3);
 197
 198         /* Break up the vec4 into individual components */
 199         for (chan = 0; chan < 4; chan++) {
 200                 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
 201                 /* XXX: Use a helper function for this.  There is one in
 202                  * tgsi_llvm.c. */
 203                 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
 204                                 LLVMBuildExtractElement(base->gallivm->builder,
 205                                 input, llvm_chan, "");
 206         }
 207 }
 208
 209 static void declare_input_fs(
 210         struct si_shader_context * si_shader_ctx,
 211         unsigned input_index,
 212         const struct tgsi_full_declaration *decl)
 213 {
 214         const char * intr_name;
 215         unsigned chan;
 216         struct lp_build_context * base =
 217                                 &si_shader_ctx->radeon_bld.soa.bld_base.base;
 218         struct gallivm_state * gallivm = base->gallivm;
 219
 220         /* This value is:
 221          * [15:0] NewPrimMask (Bit mask for each quad.  It is set it the
 222          *                     quad begins a new primitive.  Bit 0 always needs
 223          *                     to be unset)
 224          * [32:16] ParamOffset
 225          *
 226          */
 227         /* XXX: This register number must be identical to the S_00B02C_USER_SGPR
 228          * register field value
 229          */
 230         LLVMValueRef params = use_sgpr(base->gallivm, SGPR_I32, 6);
 231
 232
 233         /* XXX: Is this the input_index? */
 234         LLVMValueRef attr_number = lp_build_const_int32(gallivm, input_index);
 235
 236         /* XXX: Handle all possible interpolation modes */
 237         switch (decl->Interp.Interpolate) {
 238         case TGSI_INTERPOLATE_COLOR:
 239                 if (si_shader_ctx->rctx->rasterizer->flatshade) {
 240                         intr_name = "llvm.SI.fs.interp.constant";
 241                 } else {
 242                         if (decl->Interp.Centroid)
 243                                 intr_name = "llvm.SI.fs.interp.persp.centroid";
 244                         else
 245                                 intr_name = "llvm.SI.fs.interp.persp.center";
 246                 }
 247                 break;
 248         case TGSI_INTERPOLATE_CONSTANT:
 249                 intr_name = "llvm.SI.fs.interp.constant";
 250                 break;
 251         case TGSI_INTERPOLATE_LINEAR:
 252                 if (decl->Interp.Centroid)
 253                         intr_name = "llvm.SI.fs.interp.linear.centroid";
 254                 else
 255                         intr_name = "llvm.SI.fs.interp.linear.center";
 256                 break;
 257         case TGSI_INTERPOLATE_PERSPECTIVE:
 258                 if (decl->Interp.Centroid)
 259                         intr_name = "llvm.SI.fs.interp.persp.centroid";
 260                 else
 261                         intr_name = "llvm.SI.fs.interp.persp.center";
 262                 break;
 263         default:
 264                 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
 265                 return;
 266         }
 267
 268         /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
 269         for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 270                 LLVMValueRef args[3];
 271                 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
 272                 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
 273                 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
 274                 args[0] = llvm_chan;
 275                 args[1] = attr_number;
 276                 args[2] = params;
 277                 si_shader_ctx->radeon_bld.inputs[soa_index] =
 278                         lp_build_intrinsic(gallivm->builder, intr_name,
 279                                                 input_type, args, 3);
 280         }
 281 }
 282
 283 static void declare_input(
 284         struct radeon_llvm_context * radeon_bld,
 285         unsigned input_index,
 286         const struct tgsi_full_declaration *decl)
 287 {
 288         struct si_shader_context * si_shader_ctx =
 289                                 si_shader_context(&radeon_bld->soa.bld_base);
 290         if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
 291                 declare_input_vs(si_shader_ctx, input_index, decl);
 292         } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
 293                 declare_input_fs(si_shader_ctx, input_index, decl);
 294         } else {
 295                 fprintf(stderr, "Warning: Unsupported shader type,\n");
 296         }
 297 }
 298
 299 static LLVMValueRef fetch_constant(
 300         struct lp_build_tgsi_context * bld_base,
 301         const struct tgsi_full_src_register *reg,
 302         enum tgsi_opcode_type type,
 303         unsigned swizzle)
 304 {
 305         struct lp_build_context * base = &bld_base->base;
 306
 307         LLVMValueRef const_ptr;
 308         LLVMValueRef offset;
 309
 310         /* XXX: Assume the pointer to the constant buffer is being stored in
 311          * SGPR[0:1] */
 312         const_ptr = use_sgpr(base->gallivm, SGPR_CONST_PTR_F32, 0);
 313
 314         /* XXX: This assumes that the constant buffer is not packed, so
 315          * CONST[0].x will have an offset of 0 and CONST[1].x will have an
 316          * offset of 4. */
 317         offset = lp_build_const_int32(base->gallivm,
 318                                         (reg->Register.Index * 4) + swizzle);
 319
 320         return build_indexed_load(base->gallivm, const_ptr, offset);
 321 }
 322
 323
 324 /* Declare some intrinsics with the correct attributes */
 325 static void si_llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
 326 {
 327         LLVMValueRef function;
 328         struct gallivm_state * gallivm = bld_base->base.gallivm;
 329
 330         LLVMTypeRef i64 = LLVMInt64TypeInContext(gallivm->context);
 331         LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
 332
 333         /* declare i32 @llvm.SI.use.sgpr.i32(i32) */
 334         function = lp_declare_intrinsic(gallivm->module, "llvm.SI.use.sgpr.i32",
 335                                         i32, &i32, 1);
 336         LLVMAddFunctionAttr(function, LLVMReadNoneAttribute);
 337
 338         /* declare i64 @llvm.SI.use.sgpr.i64(i32) */
 339         function = lp_declare_intrinsic(gallivm->module, "llvm.SI.use.sgpr.i64",
 340                                         i64, &i32, 1);
 341         LLVMAddFunctionAttr(function, LLVMReadNoneAttribute);
 342 }
 343
 344 /* XXX: This is partially implemented for VS only at this point.  It is not complete */
 345 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
 346 {
 347         struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
 348         struct r600_shader * shader = &si_shader_ctx->shader->shader;
 349         struct lp_build_context * base = &bld_base->base;
 350         struct lp_build_context * uint =
 351                                 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
 352         struct tgsi_parse_context *parse = &si_shader_ctx->parse;
 353         LLVMValueRef last_args[9] = { 0 };
 354
 355         while (!tgsi_parse_end_of_tokens(parse)) {
 356                 /* XXX: component_bits controls which components of the output
 357                  * registers actually get exported. (e.g bit 0 means export
 358                  * X component, bit 1 means export Y component, etc.)  I'm
 359                  * hard coding this to 0xf for now.  In the future, we might
 360                  * want to do something else. */
 361                 unsigned component_bits = 0xf;
 362                 unsigned chan;
 363                 struct tgsi_full_declaration *d =
 364                                         &parse->FullToken.FullDeclaration;
 365                 LLVMValueRef args[9];
 366                 unsigned target;
 367                 unsigned index;
 368                 unsigned color_count = 0;
 369                 unsigned param_count = 0;
 370                 int i;
 371
 372                 tgsi_parse_token(parse);
 373                 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
 374                         continue;
 375
 376                 switch (d->Declaration.File) {
 377                 case TGSI_FILE_INPUT:
 378                         i = shader->ninput++;
 379                         shader->input[i].name = d->Semantic.Name;
 380                         shader->input[i].sid = d->Semantic.Index;
 381                         shader->input[i].interpolate = d->Interp.Interpolate;
 382                         shader->input[i].centroid = d->Interp.Centroid;
 383                         break;
 384                 case TGSI_FILE_OUTPUT:
 385                         i = shader->noutput++;
 386                         shader->output[i].name = d->Semantic.Name;
 387                         shader->output[i].sid = d->Semantic.Index;
 388                         shader->output[i].interpolate = d->Interp.Interpolate;
 389                         break;
 390                 }
 391
 392                 if (d->Declaration.File != TGSI_FILE_OUTPUT)
 393                         continue;
 394
 395                 for (index = d->Range.First; index <= d->Range.Last; index++) {
 396                         for (chan = 0; chan < 4; chan++ ) {
 397                                 LLVMValueRef out_ptr =
 398                                         si_shader_ctx->radeon_bld.soa.outputs
 399                                         [index][chan];
 400                                 /* +5 because the first output value will be
 401                                  * the 6th argument to the intrinsic. */
 402                                 args[chan + 5]= LLVMBuildLoad(
 403                                         base->gallivm->builder, out_ptr, "");
 404                         }
 405
 406                         /* XXX: We probably need to keep track of the output
 407                          * values, so we know what we are passing to the next
 408                          * stage. */
 409
 410                         /* Select the correct target */
 411                         switch(d->Semantic.Name) {
 412                         case TGSI_SEMANTIC_POSITION:
 413                                 target = V_008DFC_SQ_EXP_POS;
 414                                 break;
 415                         case TGSI_SEMANTIC_COLOR:
 416                                 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
 417                                         target = V_008DFC_SQ_EXP_PARAM + param_count;
 418                                         shader->output[i].param_offset = param_count;
 419                                         param_count++;
 420                                 } else {
 421                                         target = V_008DFC_SQ_EXP_MRT + color_count;
 422                                         color_count++;
 423                                 }
 424                                 break;
 425                         case TGSI_SEMANTIC_GENERIC:
 426                                 target = V_008DFC_SQ_EXP_PARAM + param_count;
 427                                 shader->output[i].param_offset = param_count;
 428                                 param_count++;
 429                                 break;
 430                         default:
 431                                 target = 0;
 432                                 fprintf(stderr,
 433                                         "Warning: SI unhandled output type:%d\n",
 434                                         d->Semantic.Name);
 435                         }
 436
 437                         /* Specify which components to enable */
 438                         args[0] = lp_build_const_int32(base->gallivm,
 439                                                                 component_bits);
 440
 441                         /* Specify whether the EXEC mask represents the valid mask */
 442                         args[1] = lp_build_const_int32(base->gallivm, 0);
 443
 444                         /* Specify whether this is the last export */
 445                         args[2] = lp_build_const_int32(base->gallivm, 0);
 446
 447                         /* Specify the target we are exporting */
 448                         args[3] = lp_build_const_int32(base->gallivm, target);
 449
 450                         /* Set COMPR flag to zero to export data as 32-bit */
 451                         args[4] = uint->zero;
 452
 453                         if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
 454                             (d->Semantic.Name == TGSI_SEMANTIC_POSITION) :
 455                             (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) {
 456                                 if (last_args[0]) {
 457                                         lp_build_intrinsic(base->gallivm->builder,
 458                                                            "llvm.SI.export",
 459                                                            LLVMVoidTypeInContext(base->gallivm->context),
 460                                                            last_args, 9);
 461                                 }
 462
 463                                 memcpy(last_args, args, sizeof(args));
 464                         } else {
 465                                 lp_build_intrinsic(base->gallivm->builder,
 466                                                    "llvm.SI.export",
 467                                                    LLVMVoidTypeInContext(base->gallivm->context),
 468                                                    args, 9);
 469                         }
 470
 471                 }
 472         }
 473
 474         /* Specify whether the EXEC mask represents the valid mask */
 475         last_args[1] = lp_build_const_int32(base->gallivm,
 476                                             si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
 477
 478         /* Specify that this is the last export */
 479         last_args[2] = lp_build_const_int32(base->gallivm, 1);
 480
 481         lp_build_intrinsic(base->gallivm->builder,
 482                            "llvm.SI.export",
 483                            LLVMVoidTypeInContext(base->gallivm->context),
 484                            last_args, 9);
 485
 486 /* XXX: Look up what this function does */
 487 /*              ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
 488 }
 489
 490 static void tex_fetch_args(
 491         struct lp_build_tgsi_context * bld_base,
 492         struct lp_build_emit_data * emit_data)
 493 {
 494         LLVMValueRef ptr;
 495         LLVMValueRef offset;
 496
 497         /* WriteMask */
 498         emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm,
 499                                 emit_data->inst->Dst[0].Register.WriteMask);
 500
 501         /* Coordinates */
 502         /* XXX: Not all sample instructions need 4 address arguments. */
 503         emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
 504                                                         0, LP_CHAN_ALL);
 505
 506         /* Resource */
 507         ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V8I32, 2);
 508         offset = lp_build_const_int32(bld_base->base.gallivm,
 509                                   8 * emit_data->inst->Src[1].Register.Index);
 510         emit_data->args[2] = build_indexed_load(bld_base->base.gallivm,
 511                                                 ptr, offset);
 512
 513         /* Sampler */
 514         ptr = use_sgpr(bld_base->base.gallivm, SGPR_CONST_PTR_V4I32, 1);
 515         offset = lp_build_const_int32(bld_base->base.gallivm,
 516                                   4 * emit_data->inst->Src[1].Register.Index);
 517         emit_data->args[3] = build_indexed_load(bld_base->base.gallivm,
 518                                                 ptr, offset);
 519
 520         /* Dimensions */
 521         /* XXX: We might want to pass this information to the shader at some. */
 522 /*      emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm,
 523                                         emit_data->inst->Texture.Texture);
 524 */
 525
 526         emit_data->arg_count = 4;
 527         /* XXX: To optimize, we could use a float or v2f32, if the last bits of
 528          * the writemask are clear */
 529         emit_data->dst_type = LLVMVectorType(
 530                         LLVMFloatTypeInContext(bld_base->base.gallivm->context),
 531                         4);
 532 }
 533
 534 static const struct lp_build_tgsi_action tex_action = {
 535         .fetch_args = tex_fetch_args,
 536         .emit = lp_build_tgsi_intrinsic,
 537         .intr_name = "llvm.SI.sample"
 538 };
 539
 540
 541 int si_pipe_shader_create(
 542         struct pipe_context *ctx,
 543         struct si_pipe_shader *shader)
 544 {
 545         struct r600_context *rctx = (struct r600_context*)ctx;
 546         struct si_shader_context si_shader_ctx;
 547         struct tgsi_shader_info shader_info;
 548         struct lp_build_tgsi_context * bld_base;
 549         LLVMModuleRef mod;
 550         unsigned char * inst_bytes;
 551         unsigned inst_byte_count;
 552         unsigned i;
 553
 554         radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
 555         bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
 556
 557         tgsi_scan_shader(shader->tokens, &shader_info);
 558         bld_base->info = &shader_info;
 559         bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
 560         bld_base->emit_prologue = si_llvm_emit_prologue;
 561         bld_base->emit_epilogue = si_llvm_emit_epilogue;
 562
 563         bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
 564
 565         si_shader_ctx.radeon_bld.load_input = declare_input;
 566         si_shader_ctx.tokens = shader->tokens;
 567         tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
 568         si_shader_ctx.shader = shader;
 569         si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
 570         si_shader_ctx.rctx = rctx;
 571
 572         shader->shader.nr_cbufs = rctx->nr_cbufs;
 573
 574         lp_build_tgsi_llvm(bld_base, shader->tokens);
 575
 576         radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
 577
 578         mod = bld_base->base.gallivm->module;
 579         tgsi_dump(shader->tokens, 0);
 580         LLVMDumpModule(mod);
 581         radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count, "SI", 1 /* dump */);
 582         fprintf(stderr, "SI CODE:\n");
 583         for (i = 0; i < inst_byte_count; i+=4 ) {
 584                 fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3],
 585                         inst_bytes[i + 2], inst_bytes[i + 1],
 586                         inst_bytes[i]);
 587         }
 588
 589         shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes);
 590         shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4));
 591         shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8));
 592
 593         tgsi_parse_free(&si_shader_ctx.parse);
 594
 595         /* copy new shader */
 596         if (shader->bo == NULL) {
 597                 uint32_t *ptr;
 598
 599                 shader->bo = (struct r600_resource*)
 600                         pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, inst_byte_count);
 601                 if (shader->bo == NULL) {
 602                         return -ENOMEM;
 603                 }
 604                 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
 605                 if (0 /*R600_BIG_ENDIAN*/) {
 606                         for (i = 0; i < (inst_byte_count-12)/4; ++i) {
 607                                 ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4));
 608                         }
 609                 } else {
 610                         memcpy(ptr, inst_bytes + 12, inst_byte_count - 12);
 611                 }
 612                 rctx->ws->buffer_unmap(shader->bo->cs_buf);
 613         }
 614
 615         free(inst_bytes);
 616
 617         return 0;
 618 }
 619
 620 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
 621 {
 622         pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
 623
 624         memset(&shader->shader,0,sizeof(struct r600_shader));
 625 }