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radeon/llvm: make SGPRs proper function arguments v2
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "radeon_llvm.h"
37 #include "radeon_llvm_emit.h"
38 #include "tgsi/tgsi_info.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_scan.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "radeonsi_pipe.h"
44 #include "radeonsi_shader.h"
45 #include "si_state.h"
46 #include "sid.h"
47
48 #include <assert.h>
49 #include <errno.h>
50 #include <stdio.h>
51
52 struct si_shader_context
53 {
54 struct radeon_llvm_context radeon_bld;
55 struct r600_context *rctx;
56 struct tgsi_parse_context parse;
57 struct tgsi_token * tokens;
58 struct si_pipe_shader *shader;
59 struct si_shader_key key;
60 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
61 unsigned ninput_emitted;
62 /* struct list_head inputs; */
63 /* unsigned * input_mappings *//* From TGSI to SI hw */
64 /* struct tgsi_shader_info info;*/
65 };
66
67 static struct si_shader_context * si_shader_context(
68 struct lp_build_tgsi_context * bld_base)
69 {
70 return (struct si_shader_context *)bld_base;
71 }
72
73
74 #define PERSPECTIVE_BASE 0
75 #define LINEAR_BASE 9
76
77 #define SAMPLE_OFFSET 0
78 #define CENTER_OFFSET 2
79 #define CENTROID_OFSET 4
80
81 #define USE_SGPR_MAX_SUFFIX_LEN 5
82 #define CONST_ADDR_SPACE 2
83 #define USER_SGPR_ADDR_SPACE 8
84
85 /**
86 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
87 *
88 * @param offset The offset parameter specifies the number of
89 * elements to offset, not the number of bytes or dwords. An element is the
90 * the type pointed to by the base_ptr parameter (e.g. int is the element of
91 * an int* pointer)
92 *
93 * When LLVM lowers the load instruction, it will convert the element offset
94 * into a dword offset automatically.
95 *
96 */
97 static LLVMValueRef build_indexed_load(
98 struct gallivm_state * gallivm,
99 LLVMValueRef base_ptr,
100 LLVMValueRef offset)
101 {
102 LLVMValueRef computed_ptr = LLVMBuildGEP(
103 gallivm->builder, base_ptr, &offset, 1, "");
104
105 return LLVMBuildLoad(gallivm->builder, computed_ptr, "");
106 }
107
108 static void declare_input_vs(
109 struct si_shader_context * si_shader_ctx,
110 unsigned input_index,
111 const struct tgsi_full_declaration *decl)
112 {
113 LLVMValueRef t_list_ptr;
114 LLVMValueRef t_offset;
115 LLVMValueRef t_list;
116 LLVMValueRef attribute_offset;
117 LLVMValueRef buffer_index_reg;
118 LLVMValueRef args[3];
119 LLVMTypeRef vec4_type;
120 LLVMValueRef input;
121 struct lp_build_context * uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
122 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
123 //struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[input_index];
124 unsigned chan;
125
126 /* Load the T list */
127 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
128
129 t_offset = lp_build_const_int32(base->gallivm, input_index);
130
131 t_list = build_indexed_load(base->gallivm, t_list_ptr, t_offset);
132
133 /* Build the attribute offset */
134 attribute_offset = lp_build_const_int32(base->gallivm, 0);
135
136 /* Load the buffer index is always, which is always stored in VGPR0
137 * for Vertex Shaders */
138 buffer_index_reg = build_intrinsic(base->gallivm->builder,
139 "llvm.SI.vs.load.buffer.index", uint->elem_type, NULL, 0,
140 LLVMReadNoneAttribute);
141
142 vec4_type = LLVMVectorType(base->elem_type, 4);
143 args[0] = t_list;
144 args[1] = attribute_offset;
145 args[2] = buffer_index_reg;
146 input = lp_build_intrinsic(base->gallivm->builder,
147 "llvm.SI.vs.load.input", vec4_type, args, 3);
148
149 /* Break up the vec4 into individual components */
150 for (chan = 0; chan < 4; chan++) {
151 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
152 /* XXX: Use a helper function for this. There is one in
153 * tgsi_llvm.c. */
154 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
155 LLVMBuildExtractElement(base->gallivm->builder,
156 input, llvm_chan, "");
157 }
158 }
159
160 static void declare_input_fs(
161 struct si_shader_context * si_shader_ctx,
162 unsigned input_index,
163 const struct tgsi_full_declaration *decl)
164 {
165 const char * intr_name;
166 unsigned chan;
167 struct si_shader *shader = &si_shader_ctx->shader->shader;
168 struct lp_build_context * base =
169 &si_shader_ctx->radeon_bld.soa.bld_base.base;
170 struct gallivm_state * gallivm = base->gallivm;
171 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
172
173 /* This value is:
174 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
175 * quad begins a new primitive. Bit 0 always needs
176 * to be unset)
177 * [32:16] ParamOffset
178 *
179 */
180 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
181 LLVMValueRef attr_number;
182
183 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
184 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
185 LLVMValueRef args[1];
186 unsigned soa_index =
187 radeon_llvm_reg_index_soa(input_index, chan);
188 args[0] = lp_build_const_int32(gallivm, chan);
189 si_shader_ctx->radeon_bld.inputs[soa_index] =
190 build_intrinsic(base->gallivm->builder,
191 "llvm.SI.fs.read.pos", input_type,
192 args, 1, LLVMReadNoneAttribute);
193
194 if (chan == 3)
195 /* RCP for fragcoord.w */
196 si_shader_ctx->radeon_bld.inputs[soa_index] =
197 LLVMBuildFDiv(gallivm->builder,
198 lp_build_const_float(gallivm, 1.0f),
199 si_shader_ctx->radeon_bld.inputs[soa_index],
200 "");
201 }
202 return;
203 }
204
205 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
206 LLVMValueRef face, is_face_positive;
207
208 face = build_intrinsic(gallivm->builder,
209 "llvm.SI.fs.read.face",
210 input_type,
211 NULL, 0, LLVMReadNoneAttribute);
212 is_face_positive = LLVMBuildFCmp(gallivm->builder,
213 LLVMRealUGT, face,
214 lp_build_const_float(gallivm, 0.0f),
215 "");
216
217 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
218 LLVMBuildSelect(gallivm->builder,
219 is_face_positive,
220 lp_build_const_float(gallivm, 1.0f),
221 lp_build_const_float(gallivm, 0.0f),
222 "");
223 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
224 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
225 lp_build_const_float(gallivm, 0.0f);
226 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
227 lp_build_const_float(gallivm, 1.0f);
228
229 return;
230 }
231
232 shader->input[input_index].param_offset = shader->ninterp++;
233 attr_number = lp_build_const_int32(gallivm,
234 shader->input[input_index].param_offset);
235
236 /* XXX: Handle all possible interpolation modes */
237 switch (decl->Interp.Interpolate) {
238 case TGSI_INTERPOLATE_COLOR:
239 if (si_shader_ctx->key.flatshade) {
240 intr_name = "llvm.SI.fs.interp.constant";
241 } else {
242 if (decl->Interp.Centroid)
243 intr_name = "llvm.SI.fs.interp.persp.centroid";
244 else
245 intr_name = "llvm.SI.fs.interp.persp.center";
246 }
247 break;
248 case TGSI_INTERPOLATE_CONSTANT:
249 intr_name = "llvm.SI.fs.interp.constant";
250 break;
251 case TGSI_INTERPOLATE_LINEAR:
252 if (decl->Interp.Centroid)
253 intr_name = "llvm.SI.fs.interp.linear.centroid";
254 else
255 intr_name = "llvm.SI.fs.interp.linear.center";
256 break;
257 case TGSI_INTERPOLATE_PERSPECTIVE:
258 if (decl->Interp.Centroid)
259 intr_name = "llvm.SI.fs.interp.persp.centroid";
260 else
261 intr_name = "llvm.SI.fs.interp.persp.center";
262 break;
263 default:
264 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
265 return;
266 }
267
268 if (!si_shader_ctx->ninput_emitted++) {
269 /* Enable whole quad mode */
270 lp_build_intrinsic(gallivm->builder,
271 "llvm.SI.wqm",
272 LLVMVoidTypeInContext(gallivm->context),
273 NULL, 0);
274 }
275
276 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
277 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
278 si_shader_ctx->key.color_two_side) {
279 LLVMValueRef args[3];
280 LLVMValueRef face, is_face_positive;
281 LLVMValueRef back_attr_number =
282 lp_build_const_int32(gallivm,
283 shader->input[input_index].param_offset + 1);
284
285 face = build_intrinsic(gallivm->builder,
286 "llvm.SI.fs.read.face",
287 input_type,
288 NULL, 0, LLVMReadNoneAttribute);
289 is_face_positive = LLVMBuildFCmp(gallivm->builder,
290 LLVMRealUGT, face,
291 lp_build_const_float(gallivm, 0.0f),
292 "");
293
294 args[2] = params;
295 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
296 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
297 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
298 LLVMValueRef front, back;
299
300 args[0] = llvm_chan;
301 args[1] = attr_number;
302 front = build_intrinsic(base->gallivm->builder, intr_name,
303 input_type, args, 3, LLVMReadOnlyAttribute);
304
305 args[1] = back_attr_number;
306 back = build_intrinsic(base->gallivm->builder, intr_name,
307 input_type, args, 3, LLVMReadOnlyAttribute);
308
309 si_shader_ctx->radeon_bld.inputs[soa_index] =
310 LLVMBuildSelect(gallivm->builder,
311 is_face_positive,
312 front,
313 back,
314 "");
315 }
316
317 shader->ninterp++;
318 } else {
319 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
320 LLVMValueRef args[3];
321 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
322 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
323 args[0] = llvm_chan;
324 args[1] = attr_number;
325 args[2] = params;
326 si_shader_ctx->radeon_bld.inputs[soa_index] =
327 build_intrinsic(base->gallivm->builder, intr_name,
328 input_type, args, 3, LLVMReadOnlyAttribute);
329 }
330 }
331 }
332
333 static void declare_input(
334 struct radeon_llvm_context * radeon_bld,
335 unsigned input_index,
336 const struct tgsi_full_declaration *decl)
337 {
338 struct si_shader_context * si_shader_ctx =
339 si_shader_context(&radeon_bld->soa.bld_base);
340 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
341 declare_input_vs(si_shader_ctx, input_index, decl);
342 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
343 declare_input_fs(si_shader_ctx, input_index, decl);
344 } else {
345 fprintf(stderr, "Warning: Unsupported shader type,\n");
346 }
347 }
348
349 static LLVMValueRef fetch_constant(
350 struct lp_build_tgsi_context * bld_base,
351 const struct tgsi_full_src_register *reg,
352 enum tgsi_opcode_type type,
353 unsigned swizzle)
354 {
355 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
356 struct lp_build_context * base = &bld_base->base;
357 unsigned idx;
358
359 LLVMValueRef const_ptr;
360 LLVMValueRef offset;
361 LLVMValueRef load;
362
363 if (swizzle == LP_CHAN_ALL) {
364 unsigned chan;
365 LLVMValueRef values[4];
366 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
367 values[chan] = fetch_constant(bld_base, reg, type, chan);
368
369 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
370 }
371
372 /* currently not supported */
373 if (reg->Register.Indirect) {
374 assert(0);
375 load = lp_build_const_int32(base->gallivm, 0);
376 return bitcast(bld_base, type, load);
377 }
378
379 const_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
380
381 /* XXX: This assumes that the constant buffer is not packed, so
382 * CONST[0].x will have an offset of 0 and CONST[1].x will have an
383 * offset of 4. */
384 idx = (reg->Register.Index * 4) + swizzle;
385 offset = lp_build_const_int32(base->gallivm, idx);
386
387 load = build_indexed_load(base->gallivm, const_ptr, offset);
388 return bitcast(bld_base, type, load);
389 }
390
391 /* Initialize arguments for the shader export intrinsic */
392 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
393 struct tgsi_full_declaration *d,
394 unsigned index,
395 unsigned target,
396 LLVMValueRef *args)
397 {
398 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
399 struct lp_build_context *uint =
400 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
401 struct lp_build_context *base = &bld_base->base;
402 unsigned compressed = 0;
403 unsigned chan;
404
405 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
406 int cbuf = target - V_008DFC_SQ_EXP_MRT;
407
408 if (cbuf >= 0 && cbuf < 8) {
409 compressed = (si_shader_ctx->key.export_16bpc >> cbuf) & 0x1;
410
411 if (compressed)
412 si_shader_ctx->shader->spi_shader_col_format |=
413 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
414 else
415 si_shader_ctx->shader->spi_shader_col_format |=
416 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
417 }
418 }
419
420 if (compressed) {
421 /* Pixel shader needs to pack output values before export */
422 for (chan = 0; chan < 2; chan++ ) {
423 LLVMValueRef *out_ptr =
424 si_shader_ctx->radeon_bld.soa.outputs[index];
425 args[0] = LLVMBuildLoad(base->gallivm->builder,
426 out_ptr[2 * chan], "");
427 args[1] = LLVMBuildLoad(base->gallivm->builder,
428 out_ptr[2 * chan + 1], "");
429 args[chan + 5] =
430 build_intrinsic(base->gallivm->builder,
431 "llvm.SI.packf16",
432 LLVMInt32TypeInContext(base->gallivm->context),
433 args, 2,
434 LLVMReadNoneAttribute);
435 args[chan + 7] = args[chan + 5] =
436 LLVMBuildBitCast(base->gallivm->builder,
437 args[chan + 5],
438 LLVMFloatTypeInContext(base->gallivm->context),
439 "");
440 }
441
442 /* Set COMPR flag */
443 args[4] = uint->one;
444 } else {
445 for (chan = 0; chan < 4; chan++ ) {
446 LLVMValueRef out_ptr =
447 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
448 /* +5 because the first output value will be
449 * the 6th argument to the intrinsic. */
450 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
451 out_ptr, "");
452 }
453
454 /* Clear COMPR flag */
455 args[4] = uint->zero;
456 }
457
458 /* XXX: This controls which components of the output
459 * registers actually get exported. (e.g bit 0 means export
460 * X component, bit 1 means export Y component, etc.) I'm
461 * hard coding this to 0xf for now. In the future, we might
462 * want to do something else. */
463 args[0] = lp_build_const_int32(base->gallivm, 0xf);
464
465 /* Specify whether the EXEC mask represents the valid mask */
466 args[1] = uint->zero;
467
468 /* Specify whether this is the last export */
469 args[2] = uint->zero;
470
471 /* Specify the target we are exporting */
472 args[3] = lp_build_const_int32(base->gallivm, target);
473
474 /* XXX: We probably need to keep track of the output
475 * values, so we know what we are passing to the next
476 * stage. */
477 }
478
479 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
480 unsigned index)
481 {
482 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
483 struct gallivm_state *gallivm = bld_base->base.gallivm;
484
485 if (si_shader_ctx->key.alpha_func != PIPE_FUNC_NEVER) {
486 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
487 LLVMValueRef alpha_pass =
488 lp_build_cmp(&bld_base->base,
489 si_shader_ctx->key.alpha_func,
490 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
491 lp_build_const_float(gallivm, si_shader_ctx->key.alpha_ref));
492 LLVMValueRef arg =
493 lp_build_select(&bld_base->base,
494 alpha_pass,
495 lp_build_const_float(gallivm, 1.0f),
496 lp_build_const_float(gallivm, -1.0f));
497
498 build_intrinsic(gallivm->builder,
499 "llvm.AMDGPU.kill",
500 LLVMVoidTypeInContext(gallivm->context),
501 &arg, 1, 0);
502 } else {
503 build_intrinsic(gallivm->builder,
504 "llvm.AMDGPU.kilp",
505 LLVMVoidTypeInContext(gallivm->context),
506 NULL, 0, 0);
507 }
508 }
509
510 /* XXX: This is partially implemented for VS only at this point. It is not complete */
511 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
512 {
513 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
514 struct si_shader * shader = &si_shader_ctx->shader->shader;
515 struct lp_build_context * base = &bld_base->base;
516 struct lp_build_context * uint =
517 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
518 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
519 LLVMValueRef args[9];
520 LLVMValueRef last_args[9] = { 0 };
521 unsigned color_count = 0;
522 unsigned param_count = 0;
523 int depth_index = -1, stencil_index = -1;
524
525 while (!tgsi_parse_end_of_tokens(parse)) {
526 struct tgsi_full_declaration *d =
527 &parse->FullToken.FullDeclaration;
528 unsigned target;
529 unsigned index;
530 int i;
531
532 tgsi_parse_token(parse);
533
534 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
535 parse->FullToken.FullProperty.Property.PropertyName ==
536 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
537 shader->fs_write_all = TRUE;
538
539 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
540 continue;
541
542 switch (d->Declaration.File) {
543 case TGSI_FILE_INPUT:
544 i = shader->ninput++;
545 shader->input[i].name = d->Semantic.Name;
546 shader->input[i].sid = d->Semantic.Index;
547 shader->input[i].interpolate = d->Interp.Interpolate;
548 shader->input[i].centroid = d->Interp.Centroid;
549 continue;
550
551 case TGSI_FILE_OUTPUT:
552 i = shader->noutput++;
553 shader->output[i].name = d->Semantic.Name;
554 shader->output[i].sid = d->Semantic.Index;
555 shader->output[i].interpolate = d->Interp.Interpolate;
556 break;
557
558 default:
559 continue;
560 }
561
562 for (index = d->Range.First; index <= d->Range.Last; index++) {
563 /* Select the correct target */
564 switch(d->Semantic.Name) {
565 case TGSI_SEMANTIC_PSIZE:
566 target = V_008DFC_SQ_EXP_POS;
567 break;
568 case TGSI_SEMANTIC_POSITION:
569 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
570 target = V_008DFC_SQ_EXP_POS;
571 break;
572 } else {
573 depth_index = index;
574 continue;
575 }
576 case TGSI_SEMANTIC_STENCIL:
577 stencil_index = index;
578 continue;
579 case TGSI_SEMANTIC_COLOR:
580 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
581 case TGSI_SEMANTIC_BCOLOR:
582 target = V_008DFC_SQ_EXP_PARAM + param_count;
583 shader->output[i].param_offset = param_count;
584 param_count++;
585 } else {
586 target = V_008DFC_SQ_EXP_MRT + color_count;
587 if (color_count == 0 &&
588 si_shader_ctx->key.alpha_func != PIPE_FUNC_ALWAYS)
589 si_alpha_test(bld_base, index);
590
591 color_count++;
592 }
593 break;
594 case TGSI_SEMANTIC_FOG:
595 case TGSI_SEMANTIC_GENERIC:
596 target = V_008DFC_SQ_EXP_PARAM + param_count;
597 shader->output[i].param_offset = param_count;
598 param_count++;
599 break;
600 default:
601 target = 0;
602 fprintf(stderr,
603 "Warning: SI unhandled output type:%d\n",
604 d->Semantic.Name);
605 }
606
607 si_llvm_init_export_args(bld_base, d, index, target, args);
608
609 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
610 (d->Semantic.Name == TGSI_SEMANTIC_POSITION) :
611 (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) {
612 if (last_args[0]) {
613 lp_build_intrinsic(base->gallivm->builder,
614 "llvm.SI.export",
615 LLVMVoidTypeInContext(base->gallivm->context),
616 last_args, 9);
617 }
618
619 memcpy(last_args, args, sizeof(args));
620 } else {
621 lp_build_intrinsic(base->gallivm->builder,
622 "llvm.SI.export",
623 LLVMVoidTypeInContext(base->gallivm->context),
624 args, 9);
625 }
626
627 }
628 }
629
630 if (depth_index >= 0 || stencil_index >= 0) {
631 LLVMValueRef out_ptr;
632 unsigned mask = 0;
633
634 /* Specify the target we are exporting */
635 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
636
637 if (depth_index >= 0) {
638 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
639 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
640 mask |= 0x1;
641
642 if (stencil_index < 0) {
643 args[6] =
644 args[7] =
645 args[8] = args[5];
646 }
647 }
648
649 if (stencil_index >= 0) {
650 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
651 args[7] =
652 args[8] =
653 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
654 mask |= 0x2;
655
656 if (depth_index < 0)
657 args[5] = args[6];
658 }
659
660 /* Specify which components to enable */
661 args[0] = lp_build_const_int32(base->gallivm, mask);
662
663 args[1] =
664 args[2] =
665 args[4] = uint->zero;
666
667 if (last_args[0])
668 lp_build_intrinsic(base->gallivm->builder,
669 "llvm.SI.export",
670 LLVMVoidTypeInContext(base->gallivm->context),
671 args, 9);
672 else
673 memcpy(last_args, args, sizeof(args));
674 }
675
676 if (!last_args[0]) {
677 assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
678
679 /* Specify which components to enable */
680 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
681
682 /* Specify the target we are exporting */
683 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
684
685 /* Set COMPR flag to zero to export data as 32-bit */
686 last_args[4] = uint->zero;
687
688 /* dummy bits */
689 last_args[5]= uint->zero;
690 last_args[6]= uint->zero;
691 last_args[7]= uint->zero;
692 last_args[8]= uint->zero;
693
694 si_shader_ctx->shader->spi_shader_col_format |=
695 V_028714_SPI_SHADER_32_ABGR;
696 }
697
698 /* Specify whether the EXEC mask represents the valid mask */
699 last_args[1] = lp_build_const_int32(base->gallivm,
700 si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
701
702 if (shader->fs_write_all && shader->nr_cbufs > 1) {
703 int i;
704
705 /* Specify that this is not yet the last export */
706 last_args[2] = lp_build_const_int32(base->gallivm, 0);
707
708 for (i = 1; i < shader->nr_cbufs; i++) {
709 /* Specify the target we are exporting */
710 last_args[3] = lp_build_const_int32(base->gallivm,
711 V_008DFC_SQ_EXP_MRT + i);
712
713 lp_build_intrinsic(base->gallivm->builder,
714 "llvm.SI.export",
715 LLVMVoidTypeInContext(base->gallivm->context),
716 last_args, 9);
717
718 si_shader_ctx->shader->spi_shader_col_format |=
719 si_shader_ctx->shader->spi_shader_col_format << 4;
720 }
721
722 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
723 }
724
725 /* Specify that this is the last export */
726 last_args[2] = lp_build_const_int32(base->gallivm, 1);
727
728 lp_build_intrinsic(base->gallivm->builder,
729 "llvm.SI.export",
730 LLVMVoidTypeInContext(base->gallivm->context),
731 last_args, 9);
732
733 /* XXX: Look up what this function does */
734 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
735 }
736
737 static void tex_fetch_args(
738 struct lp_build_tgsi_context * bld_base,
739 struct lp_build_emit_data * emit_data)
740 {
741 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
742 struct gallivm_state *gallivm = bld_base->base.gallivm;
743 const struct tgsi_full_instruction * inst = emit_data->inst;
744 unsigned opcode = inst->Instruction.Opcode;
745 unsigned target = inst->Texture.Texture;
746 LLVMValueRef ptr;
747 LLVMValueRef offset;
748 LLVMValueRef coords[4];
749 LLVMValueRef address[16];
750 unsigned count = 0;
751 unsigned chan;
752
753 /* WriteMask */
754 /* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
755 emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm, 0xf);
756
757 /* Fetch and project texture coordinates */
758 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
759 for (chan = 0; chan < 3; chan++ ) {
760 coords[chan] = lp_build_emit_fetch(bld_base,
761 emit_data->inst, 0,
762 chan);
763 if (opcode == TGSI_OPCODE_TXP)
764 coords[chan] = lp_build_emit_llvm_binary(bld_base,
765 TGSI_OPCODE_DIV,
766 coords[chan],
767 coords[3]);
768 }
769
770 if (opcode == TGSI_OPCODE_TXP)
771 coords[3] = bld_base->base.one;
772
773 /* Pack LOD bias value */
774 if (opcode == TGSI_OPCODE_TXB)
775 address[count++] = coords[3];
776
777 if ((target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE) &&
778 opcode != TGSI_OPCODE_TXQ)
779 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
780
781 /* Pack depth comparison value */
782 switch (target) {
783 case TGSI_TEXTURE_SHADOW1D:
784 case TGSI_TEXTURE_SHADOW1D_ARRAY:
785 case TGSI_TEXTURE_SHADOW2D:
786 case TGSI_TEXTURE_SHADOWRECT:
787 address[count++] = coords[2];
788 break;
789 case TGSI_TEXTURE_SHADOWCUBE:
790 case TGSI_TEXTURE_SHADOW2D_ARRAY:
791 address[count++] = coords[3];
792 break;
793 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
794 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
795 }
796
797 /* Pack texture coordinates */
798 address[count++] = coords[0];
799 switch (target) {
800 case TGSI_TEXTURE_2D:
801 case TGSI_TEXTURE_2D_ARRAY:
802 case TGSI_TEXTURE_3D:
803 case TGSI_TEXTURE_CUBE:
804 case TGSI_TEXTURE_RECT:
805 case TGSI_TEXTURE_SHADOW2D:
806 case TGSI_TEXTURE_SHADOWRECT:
807 case TGSI_TEXTURE_SHADOW2D_ARRAY:
808 case TGSI_TEXTURE_SHADOWCUBE:
809 case TGSI_TEXTURE_2D_MSAA:
810 case TGSI_TEXTURE_2D_ARRAY_MSAA:
811 case TGSI_TEXTURE_CUBE_ARRAY:
812 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
813 address[count++] = coords[1];
814 }
815 switch (target) {
816 case TGSI_TEXTURE_3D:
817 case TGSI_TEXTURE_CUBE:
818 case TGSI_TEXTURE_SHADOWCUBE:
819 case TGSI_TEXTURE_CUBE_ARRAY:
820 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
821 address[count++] = coords[2];
822 }
823
824 /* Pack array slice */
825 switch (target) {
826 case TGSI_TEXTURE_1D_ARRAY:
827 address[count++] = coords[1];
828 }
829 switch (target) {
830 case TGSI_TEXTURE_2D_ARRAY:
831 case TGSI_TEXTURE_2D_ARRAY_MSAA:
832 case TGSI_TEXTURE_SHADOW2D_ARRAY:
833 address[count++] = coords[2];
834 }
835 switch (target) {
836 case TGSI_TEXTURE_CUBE_ARRAY:
837 case TGSI_TEXTURE_SHADOW1D_ARRAY:
838 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
839 address[count++] = coords[3];
840 }
841
842 /* Pack LOD */
843 if (opcode == TGSI_OPCODE_TXL)
844 address[count++] = coords[3];
845
846 if (count > 16) {
847 assert(!"Cannot handle more than 16 texture address parameters");
848 count = 16;
849 }
850
851 for (chan = 0; chan < count; chan++ ) {
852 address[chan] = LLVMBuildBitCast(gallivm->builder,
853 address[chan],
854 LLVMInt32TypeInContext(gallivm->context),
855 "");
856 }
857
858 /* Pad to power of two vector */
859 while (count < util_next_power_of_two(count))
860 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
861
862 emit_data->args[1] = lp_build_gather_values(gallivm, address, count);
863
864 /* Resource */
865 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
866 offset = lp_build_const_int32(bld_base->base.gallivm,
867 emit_data->inst->Src[1].Register.Index);
868 emit_data->args[2] = build_indexed_load(bld_base->base.gallivm,
869 ptr, offset);
870
871 /* Sampler */
872 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
873 offset = lp_build_const_int32(bld_base->base.gallivm,
874 emit_data->inst->Src[1].Register.Index);
875 emit_data->args[3] = build_indexed_load(bld_base->base.gallivm,
876 ptr, offset);
877
878 /* Dimensions */
879 emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm, target);
880
881 emit_data->arg_count = 5;
882 /* XXX: To optimize, we could use a float or v2f32, if the last bits of
883 * the writemask are clear */
884 emit_data->dst_type = LLVMVectorType(
885 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
886 4);
887 }
888
889 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
890 struct lp_build_tgsi_context * bld_base,
891 struct lp_build_emit_data * emit_data)
892 {
893 struct lp_build_context * base = &bld_base->base;
894 char intr_name[23];
895
896 sprintf(intr_name, "%sv%ui32", action->intr_name,
897 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[1])));
898
899 emit_data->output[emit_data->chan] = lp_build_intrinsic(
900 base->gallivm->builder, intr_name, emit_data->dst_type,
901 emit_data->args, emit_data->arg_count);
902 }
903
904 static const struct lp_build_tgsi_action tex_action = {
905 .fetch_args = tex_fetch_args,
906 .emit = build_tex_intrinsic,
907 .intr_name = "llvm.SI.sample."
908 };
909
910 static const struct lp_build_tgsi_action txb_action = {
911 .fetch_args = tex_fetch_args,
912 .emit = build_tex_intrinsic,
913 .intr_name = "llvm.SI.sampleb."
914 };
915
916 static const struct lp_build_tgsi_action txl_action = {
917 .fetch_args = tex_fetch_args,
918 .emit = build_tex_intrinsic,
919 .intr_name = "llvm.SI.samplel."
920 };
921
922 static void create_function(struct si_shader_context *si_shader_ctx)
923 {
924 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
925 LLVMTypeRef params[4], f, i8;
926 unsigned i;
927
928 f = LLVMFloatTypeInContext(gallivm->context);
929 i8 = LLVMInt8TypeInContext(gallivm->context);
930 params[SI_PARAM_CONST] = LLVMPointerType(f, CONST_ADDR_SPACE);
931 params[SI_PARAM_SAMPLER] = LLVMPointerType(LLVMVectorType(i8, 16), CONST_ADDR_SPACE);
932 params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), CONST_ADDR_SPACE);
933
934 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
935 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
936 else
937 params[SI_PARAM_PRIM_MASK] = LLVMInt32TypeInContext(gallivm->context);
938
939 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 4);
940
941 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
942 for (i = SI_PARAM_CONST; i <= SI_PARAM_VERTEX_BUFFER; ++i) {
943 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
944 LLVMAddAttribute(P, LLVMInRegAttribute);
945 }
946 }
947
948 int si_pipe_shader_create(
949 struct pipe_context *ctx,
950 struct si_pipe_shader *shader,
951 struct si_shader_key key)
952 {
953 struct r600_context *rctx = (struct r600_context*)ctx;
954 struct si_pipe_shader_selector *sel = shader->selector;
955 struct si_shader_context si_shader_ctx;
956 struct tgsi_shader_info shader_info;
957 struct lp_build_tgsi_context * bld_base;
958 LLVMModuleRef mod;
959 unsigned char * inst_bytes;
960 unsigned inst_byte_count;
961 unsigned i;
962 uint32_t *ptr;
963 bool dump;
964
965 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
966
967 assert(shader->shader.noutput == 0);
968 assert(shader->shader.ninterp == 0);
969 assert(shader->shader.ninput == 0);
970
971 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
972 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
973 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
974
975 tgsi_scan_shader(sel->tokens, &shader_info);
976 if (shader_info.indirect_files != 0) {
977 fprintf(stderr, "Indirect addressing not fully handled yet\n");
978 return -ENOSYS;
979 }
980
981 shader->shader.uses_kill = shader_info.uses_kill;
982 bld_base->info = &shader_info;
983 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
984 bld_base->emit_epilogue = si_llvm_emit_epilogue;
985
986 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
987 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
988 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
989 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
990
991 si_shader_ctx.radeon_bld.load_input = declare_input;
992 si_shader_ctx.tokens = sel->tokens;
993 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
994 si_shader_ctx.shader = shader;
995 si_shader_ctx.key = key;
996 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
997 si_shader_ctx.rctx = rctx;
998
999 create_function(&si_shader_ctx);
1000
1001 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
1002
1003 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
1004 * conversion fails. */
1005 if (dump) {
1006 tgsi_dump(sel->tokens, 0);
1007 }
1008
1009 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
1010 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
1011 return -EINVAL;
1012 }
1013
1014 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
1015
1016 mod = bld_base->base.gallivm->module;
1017 if (dump) {
1018 LLVMDumpModule(mod);
1019 }
1020 radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count, "SI", dump);
1021 if (dump) {
1022 fprintf(stderr, "SI CODE:\n");
1023 for (i = 0; i < inst_byte_count; i+=4 ) {
1024 fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3],
1025 inst_bytes[i + 2], inst_bytes[i + 1],
1026 inst_bytes[i]);
1027 }
1028 }
1029
1030 shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes);
1031 shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4));
1032 shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8));
1033
1034 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
1035 tgsi_parse_free(&si_shader_ctx.parse);
1036
1037 /* copy new shader */
1038 si_resource_reference(&shader->bo, NULL);
1039 shader->bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
1040 inst_byte_count - 12);
1041 if (shader->bo == NULL) {
1042 return -ENOMEM;
1043 }
1044
1045 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1046 if (0 /*R600_BIG_ENDIAN*/) {
1047 for (i = 0; i < (inst_byte_count-12)/4; ++i) {
1048 ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4));
1049 }
1050 } else {
1051 memcpy(ptr, inst_bytes + 12, inst_byte_count - 12);
1052 }
1053 rctx->ws->buffer_unmap(shader->bo->cs_buf);
1054
1055 free(inst_bytes);
1056
1057 return 0;
1058 }
1059
1060 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
1061 {
1062 si_resource_reference(&shader->bo, NULL);
1063 }