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radeonsi: remove SI.vs.load.buffer.index
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "radeon_llvm.h"
37 #include "radeon_llvm_emit.h"
38 #include "tgsi/tgsi_info.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_scan.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "radeonsi_pipe.h"
44 #include "radeonsi_shader.h"
45 #include "si_state.h"
46 #include "sid.h"
47
48 #include <assert.h>
49 #include <errno.h>
50 #include <stdio.h>
51
52 struct si_shader_context
53 {
54 struct radeon_llvm_context radeon_bld;
55 struct r600_context *rctx;
56 struct tgsi_parse_context parse;
57 struct tgsi_token * tokens;
58 struct si_pipe_shader *shader;
59 struct si_shader_key key;
60 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
61 unsigned ninput_emitted;
62 /* struct list_head inputs; */
63 /* unsigned * input_mappings *//* From TGSI to SI hw */
64 /* struct tgsi_shader_info info;*/
65 };
66
67 static struct si_shader_context * si_shader_context(
68 struct lp_build_tgsi_context * bld_base)
69 {
70 return (struct si_shader_context *)bld_base;
71 }
72
73
74 #define PERSPECTIVE_BASE 0
75 #define LINEAR_BASE 9
76
77 #define SAMPLE_OFFSET 0
78 #define CENTER_OFFSET 2
79 #define CENTROID_OFSET 4
80
81 #define USE_SGPR_MAX_SUFFIX_LEN 5
82 #define CONST_ADDR_SPACE 2
83 #define USER_SGPR_ADDR_SPACE 8
84
85 /**
86 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
87 *
88 * @param offset The offset parameter specifies the number of
89 * elements to offset, not the number of bytes or dwords. An element is the
90 * the type pointed to by the base_ptr parameter (e.g. int is the element of
91 * an int* pointer)
92 *
93 * When LLVM lowers the load instruction, it will convert the element offset
94 * into a dword offset automatically.
95 *
96 */
97 static LLVMValueRef build_indexed_load(
98 struct gallivm_state * gallivm,
99 LLVMValueRef base_ptr,
100 LLVMValueRef offset)
101 {
102 LLVMValueRef computed_ptr = LLVMBuildGEP(
103 gallivm->builder, base_ptr, &offset, 1, "");
104
105 return LLVMBuildLoad(gallivm->builder, computed_ptr, "");
106 }
107
108 static void declare_input_vs(
109 struct si_shader_context * si_shader_ctx,
110 unsigned input_index,
111 const struct tgsi_full_declaration *decl)
112 {
113 LLVMValueRef t_list_ptr;
114 LLVMValueRef t_offset;
115 LLVMValueRef t_list;
116 LLVMValueRef attribute_offset;
117 LLVMValueRef buffer_index_reg;
118 LLVMValueRef args[3];
119 LLVMTypeRef vec4_type;
120 LLVMValueRef input;
121 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
122 //struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[input_index];
123 unsigned chan;
124
125 /* Load the T list */
126 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
127
128 t_offset = lp_build_const_int32(base->gallivm, input_index);
129
130 t_list = build_indexed_load(base->gallivm, t_list_ptr, t_offset);
131
132 /* Build the attribute offset */
133 attribute_offset = lp_build_const_int32(base->gallivm, 0);
134
135 /* Load the buffer index, which is always stored in VGPR0
136 * for Vertex Shaders */
137 buffer_index_reg = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_INDEX);
138
139 vec4_type = LLVMVectorType(base->elem_type, 4);
140 args[0] = t_list;
141 args[1] = attribute_offset;
142 args[2] = buffer_index_reg;
143 input = lp_build_intrinsic(base->gallivm->builder,
144 "llvm.SI.vs.load.input", vec4_type, args, 3);
145
146 /* Break up the vec4 into individual components */
147 for (chan = 0; chan < 4; chan++) {
148 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
149 /* XXX: Use a helper function for this. There is one in
150 * tgsi_llvm.c. */
151 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
152 LLVMBuildExtractElement(base->gallivm->builder,
153 input, llvm_chan, "");
154 }
155 }
156
157 static void declare_input_fs(
158 struct si_shader_context * si_shader_ctx,
159 unsigned input_index,
160 const struct tgsi_full_declaration *decl)
161 {
162 const char * intr_name;
163 unsigned chan;
164 struct si_shader *shader = &si_shader_ctx->shader->shader;
165 struct lp_build_context * base =
166 &si_shader_ctx->radeon_bld.soa.bld_base.base;
167 struct gallivm_state * gallivm = base->gallivm;
168 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
169
170 /* This value is:
171 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
172 * quad begins a new primitive. Bit 0 always needs
173 * to be unset)
174 * [32:16] ParamOffset
175 *
176 */
177 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
178 LLVMValueRef attr_number;
179
180 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
181 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
182 LLVMValueRef args[1];
183 unsigned soa_index =
184 radeon_llvm_reg_index_soa(input_index, chan);
185 args[0] = lp_build_const_int32(gallivm, chan);
186 si_shader_ctx->radeon_bld.inputs[soa_index] =
187 build_intrinsic(base->gallivm->builder,
188 "llvm.SI.fs.read.pos", input_type,
189 args, 1, LLVMReadNoneAttribute);
190
191 if (chan == 3)
192 /* RCP for fragcoord.w */
193 si_shader_ctx->radeon_bld.inputs[soa_index] =
194 LLVMBuildFDiv(gallivm->builder,
195 lp_build_const_float(gallivm, 1.0f),
196 si_shader_ctx->radeon_bld.inputs[soa_index],
197 "");
198 }
199 return;
200 }
201
202 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
203 LLVMValueRef face, is_face_positive;
204
205 face = build_intrinsic(gallivm->builder,
206 "llvm.SI.fs.read.face",
207 input_type,
208 NULL, 0, LLVMReadNoneAttribute);
209 is_face_positive = LLVMBuildFCmp(gallivm->builder,
210 LLVMRealUGT, face,
211 lp_build_const_float(gallivm, 0.0f),
212 "");
213
214 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
215 LLVMBuildSelect(gallivm->builder,
216 is_face_positive,
217 lp_build_const_float(gallivm, 1.0f),
218 lp_build_const_float(gallivm, 0.0f),
219 "");
220 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
221 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
222 lp_build_const_float(gallivm, 0.0f);
223 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
224 lp_build_const_float(gallivm, 1.0f);
225
226 return;
227 }
228
229 shader->input[input_index].param_offset = shader->ninterp++;
230 attr_number = lp_build_const_int32(gallivm,
231 shader->input[input_index].param_offset);
232
233 /* XXX: Handle all possible interpolation modes */
234 switch (decl->Interp.Interpolate) {
235 case TGSI_INTERPOLATE_COLOR:
236 if (si_shader_ctx->key.flatshade) {
237 intr_name = "llvm.SI.fs.interp.constant";
238 } else {
239 if (decl->Interp.Centroid)
240 intr_name = "llvm.SI.fs.interp.persp.centroid";
241 else
242 intr_name = "llvm.SI.fs.interp.persp.center";
243 }
244 break;
245 case TGSI_INTERPOLATE_CONSTANT:
246 intr_name = "llvm.SI.fs.interp.constant";
247 break;
248 case TGSI_INTERPOLATE_LINEAR:
249 if (decl->Interp.Centroid)
250 intr_name = "llvm.SI.fs.interp.linear.centroid";
251 else
252 intr_name = "llvm.SI.fs.interp.linear.center";
253 break;
254 case TGSI_INTERPOLATE_PERSPECTIVE:
255 if (decl->Interp.Centroid)
256 intr_name = "llvm.SI.fs.interp.persp.centroid";
257 else
258 intr_name = "llvm.SI.fs.interp.persp.center";
259 break;
260 default:
261 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
262 return;
263 }
264
265 if (!si_shader_ctx->ninput_emitted++) {
266 /* Enable whole quad mode */
267 lp_build_intrinsic(gallivm->builder,
268 "llvm.SI.wqm",
269 LLVMVoidTypeInContext(gallivm->context),
270 NULL, 0);
271 }
272
273 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
274 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
275 si_shader_ctx->key.color_two_side) {
276 LLVMValueRef args[3];
277 LLVMValueRef face, is_face_positive;
278 LLVMValueRef back_attr_number =
279 lp_build_const_int32(gallivm,
280 shader->input[input_index].param_offset + 1);
281
282 face = build_intrinsic(gallivm->builder,
283 "llvm.SI.fs.read.face",
284 input_type,
285 NULL, 0, LLVMReadNoneAttribute);
286 is_face_positive = LLVMBuildFCmp(gallivm->builder,
287 LLVMRealUGT, face,
288 lp_build_const_float(gallivm, 0.0f),
289 "");
290
291 args[2] = params;
292 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
293 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
294 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
295 LLVMValueRef front, back;
296
297 args[0] = llvm_chan;
298 args[1] = attr_number;
299 front = build_intrinsic(base->gallivm->builder, intr_name,
300 input_type, args, 3, LLVMReadOnlyAttribute);
301
302 args[1] = back_attr_number;
303 back = build_intrinsic(base->gallivm->builder, intr_name,
304 input_type, args, 3, LLVMReadOnlyAttribute);
305
306 si_shader_ctx->radeon_bld.inputs[soa_index] =
307 LLVMBuildSelect(gallivm->builder,
308 is_face_positive,
309 front,
310 back,
311 "");
312 }
313
314 shader->ninterp++;
315 } else {
316 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
317 LLVMValueRef args[3];
318 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
319 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
320 args[0] = llvm_chan;
321 args[1] = attr_number;
322 args[2] = params;
323 si_shader_ctx->radeon_bld.inputs[soa_index] =
324 build_intrinsic(base->gallivm->builder, intr_name,
325 input_type, args, 3, LLVMReadOnlyAttribute);
326 }
327 }
328 }
329
330 static void declare_input(
331 struct radeon_llvm_context * radeon_bld,
332 unsigned input_index,
333 const struct tgsi_full_declaration *decl)
334 {
335 struct si_shader_context * si_shader_ctx =
336 si_shader_context(&radeon_bld->soa.bld_base);
337 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
338 declare_input_vs(si_shader_ctx, input_index, decl);
339 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
340 declare_input_fs(si_shader_ctx, input_index, decl);
341 } else {
342 fprintf(stderr, "Warning: Unsupported shader type,\n");
343 }
344 }
345
346 static LLVMValueRef fetch_constant(
347 struct lp_build_tgsi_context * bld_base,
348 const struct tgsi_full_src_register *reg,
349 enum tgsi_opcode_type type,
350 unsigned swizzle)
351 {
352 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
353 struct lp_build_context * base = &bld_base->base;
354 unsigned idx;
355
356 LLVMValueRef const_ptr;
357 LLVMValueRef offset;
358 LLVMValueRef load;
359
360 if (swizzle == LP_CHAN_ALL) {
361 unsigned chan;
362 LLVMValueRef values[4];
363 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
364 values[chan] = fetch_constant(bld_base, reg, type, chan);
365
366 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
367 }
368
369 /* currently not supported */
370 if (reg->Register.Indirect) {
371 assert(0);
372 load = lp_build_const_int32(base->gallivm, 0);
373 return bitcast(bld_base, type, load);
374 }
375
376 const_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
377
378 /* XXX: This assumes that the constant buffer is not packed, so
379 * CONST[0].x will have an offset of 0 and CONST[1].x will have an
380 * offset of 4. */
381 idx = (reg->Register.Index * 4) + swizzle;
382 offset = lp_build_const_int32(base->gallivm, idx);
383
384 load = build_indexed_load(base->gallivm, const_ptr, offset);
385 return bitcast(bld_base, type, load);
386 }
387
388 /* Initialize arguments for the shader export intrinsic */
389 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
390 struct tgsi_full_declaration *d,
391 unsigned index,
392 unsigned target,
393 LLVMValueRef *args)
394 {
395 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
396 struct lp_build_context *uint =
397 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
398 struct lp_build_context *base = &bld_base->base;
399 unsigned compressed = 0;
400 unsigned chan;
401
402 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
403 int cbuf = target - V_008DFC_SQ_EXP_MRT;
404
405 if (cbuf >= 0 && cbuf < 8) {
406 compressed = (si_shader_ctx->key.export_16bpc >> cbuf) & 0x1;
407
408 if (compressed)
409 si_shader_ctx->shader->spi_shader_col_format |=
410 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
411 else
412 si_shader_ctx->shader->spi_shader_col_format |=
413 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
414 }
415 }
416
417 if (compressed) {
418 /* Pixel shader needs to pack output values before export */
419 for (chan = 0; chan < 2; chan++ ) {
420 LLVMValueRef *out_ptr =
421 si_shader_ctx->radeon_bld.soa.outputs[index];
422 args[0] = LLVMBuildLoad(base->gallivm->builder,
423 out_ptr[2 * chan], "");
424 args[1] = LLVMBuildLoad(base->gallivm->builder,
425 out_ptr[2 * chan + 1], "");
426 args[chan + 5] =
427 build_intrinsic(base->gallivm->builder,
428 "llvm.SI.packf16",
429 LLVMInt32TypeInContext(base->gallivm->context),
430 args, 2,
431 LLVMReadNoneAttribute);
432 args[chan + 7] = args[chan + 5] =
433 LLVMBuildBitCast(base->gallivm->builder,
434 args[chan + 5],
435 LLVMFloatTypeInContext(base->gallivm->context),
436 "");
437 }
438
439 /* Set COMPR flag */
440 args[4] = uint->one;
441 } else {
442 for (chan = 0; chan < 4; chan++ ) {
443 LLVMValueRef out_ptr =
444 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
445 /* +5 because the first output value will be
446 * the 6th argument to the intrinsic. */
447 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
448 out_ptr, "");
449 }
450
451 /* Clear COMPR flag */
452 args[4] = uint->zero;
453 }
454
455 /* XXX: This controls which components of the output
456 * registers actually get exported. (e.g bit 0 means export
457 * X component, bit 1 means export Y component, etc.) I'm
458 * hard coding this to 0xf for now. In the future, we might
459 * want to do something else. */
460 args[0] = lp_build_const_int32(base->gallivm, 0xf);
461
462 /* Specify whether the EXEC mask represents the valid mask */
463 args[1] = uint->zero;
464
465 /* Specify whether this is the last export */
466 args[2] = uint->zero;
467
468 /* Specify the target we are exporting */
469 args[3] = lp_build_const_int32(base->gallivm, target);
470
471 /* XXX: We probably need to keep track of the output
472 * values, so we know what we are passing to the next
473 * stage. */
474 }
475
476 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
477 unsigned index)
478 {
479 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
480 struct gallivm_state *gallivm = bld_base->base.gallivm;
481
482 if (si_shader_ctx->key.alpha_func != PIPE_FUNC_NEVER) {
483 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
484 LLVMValueRef alpha_pass =
485 lp_build_cmp(&bld_base->base,
486 si_shader_ctx->key.alpha_func,
487 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
488 lp_build_const_float(gallivm, si_shader_ctx->key.alpha_ref));
489 LLVMValueRef arg =
490 lp_build_select(&bld_base->base,
491 alpha_pass,
492 lp_build_const_float(gallivm, 1.0f),
493 lp_build_const_float(gallivm, -1.0f));
494
495 build_intrinsic(gallivm->builder,
496 "llvm.AMDGPU.kill",
497 LLVMVoidTypeInContext(gallivm->context),
498 &arg, 1, 0);
499 } else {
500 build_intrinsic(gallivm->builder,
501 "llvm.AMDGPU.kilp",
502 LLVMVoidTypeInContext(gallivm->context),
503 NULL, 0, 0);
504 }
505 }
506
507 /* XXX: This is partially implemented for VS only at this point. It is not complete */
508 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
509 {
510 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
511 struct si_shader * shader = &si_shader_ctx->shader->shader;
512 struct lp_build_context * base = &bld_base->base;
513 struct lp_build_context * uint =
514 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
515 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
516 LLVMValueRef args[9];
517 LLVMValueRef last_args[9] = { 0 };
518 unsigned color_count = 0;
519 unsigned param_count = 0;
520 int depth_index = -1, stencil_index = -1;
521
522 while (!tgsi_parse_end_of_tokens(parse)) {
523 struct tgsi_full_declaration *d =
524 &parse->FullToken.FullDeclaration;
525 unsigned target;
526 unsigned index;
527 int i;
528
529 tgsi_parse_token(parse);
530
531 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
532 parse->FullToken.FullProperty.Property.PropertyName ==
533 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
534 shader->fs_write_all = TRUE;
535
536 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
537 continue;
538
539 switch (d->Declaration.File) {
540 case TGSI_FILE_INPUT:
541 i = shader->ninput++;
542 shader->input[i].name = d->Semantic.Name;
543 shader->input[i].sid = d->Semantic.Index;
544 shader->input[i].interpolate = d->Interp.Interpolate;
545 shader->input[i].centroid = d->Interp.Centroid;
546 continue;
547
548 case TGSI_FILE_OUTPUT:
549 i = shader->noutput++;
550 shader->output[i].name = d->Semantic.Name;
551 shader->output[i].sid = d->Semantic.Index;
552 shader->output[i].interpolate = d->Interp.Interpolate;
553 break;
554
555 default:
556 continue;
557 }
558
559 for (index = d->Range.First; index <= d->Range.Last; index++) {
560 /* Select the correct target */
561 switch(d->Semantic.Name) {
562 case TGSI_SEMANTIC_PSIZE:
563 target = V_008DFC_SQ_EXP_POS;
564 break;
565 case TGSI_SEMANTIC_POSITION:
566 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
567 target = V_008DFC_SQ_EXP_POS;
568 break;
569 } else {
570 depth_index = index;
571 continue;
572 }
573 case TGSI_SEMANTIC_STENCIL:
574 stencil_index = index;
575 continue;
576 case TGSI_SEMANTIC_COLOR:
577 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
578 case TGSI_SEMANTIC_BCOLOR:
579 target = V_008DFC_SQ_EXP_PARAM + param_count;
580 shader->output[i].param_offset = param_count;
581 param_count++;
582 } else {
583 target = V_008DFC_SQ_EXP_MRT + color_count;
584 if (color_count == 0 &&
585 si_shader_ctx->key.alpha_func != PIPE_FUNC_ALWAYS)
586 si_alpha_test(bld_base, index);
587
588 color_count++;
589 }
590 break;
591 case TGSI_SEMANTIC_FOG:
592 case TGSI_SEMANTIC_GENERIC:
593 target = V_008DFC_SQ_EXP_PARAM + param_count;
594 shader->output[i].param_offset = param_count;
595 param_count++;
596 break;
597 default:
598 target = 0;
599 fprintf(stderr,
600 "Warning: SI unhandled output type:%d\n",
601 d->Semantic.Name);
602 }
603
604 si_llvm_init_export_args(bld_base, d, index, target, args);
605
606 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
607 (d->Semantic.Name == TGSI_SEMANTIC_POSITION) :
608 (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) {
609 if (last_args[0]) {
610 lp_build_intrinsic(base->gallivm->builder,
611 "llvm.SI.export",
612 LLVMVoidTypeInContext(base->gallivm->context),
613 last_args, 9);
614 }
615
616 memcpy(last_args, args, sizeof(args));
617 } else {
618 lp_build_intrinsic(base->gallivm->builder,
619 "llvm.SI.export",
620 LLVMVoidTypeInContext(base->gallivm->context),
621 args, 9);
622 }
623
624 }
625 }
626
627 if (depth_index >= 0 || stencil_index >= 0) {
628 LLVMValueRef out_ptr;
629 unsigned mask = 0;
630
631 /* Specify the target we are exporting */
632 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
633
634 if (depth_index >= 0) {
635 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
636 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
637 mask |= 0x1;
638
639 if (stencil_index < 0) {
640 args[6] =
641 args[7] =
642 args[8] = args[5];
643 }
644 }
645
646 if (stencil_index >= 0) {
647 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
648 args[7] =
649 args[8] =
650 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
651 mask |= 0x2;
652
653 if (depth_index < 0)
654 args[5] = args[6];
655 }
656
657 /* Specify which components to enable */
658 args[0] = lp_build_const_int32(base->gallivm, mask);
659
660 args[1] =
661 args[2] =
662 args[4] = uint->zero;
663
664 if (last_args[0])
665 lp_build_intrinsic(base->gallivm->builder,
666 "llvm.SI.export",
667 LLVMVoidTypeInContext(base->gallivm->context),
668 args, 9);
669 else
670 memcpy(last_args, args, sizeof(args));
671 }
672
673 if (!last_args[0]) {
674 assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
675
676 /* Specify which components to enable */
677 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
678
679 /* Specify the target we are exporting */
680 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
681
682 /* Set COMPR flag to zero to export data as 32-bit */
683 last_args[4] = uint->zero;
684
685 /* dummy bits */
686 last_args[5]= uint->zero;
687 last_args[6]= uint->zero;
688 last_args[7]= uint->zero;
689 last_args[8]= uint->zero;
690
691 si_shader_ctx->shader->spi_shader_col_format |=
692 V_028714_SPI_SHADER_32_ABGR;
693 }
694
695 /* Specify whether the EXEC mask represents the valid mask */
696 last_args[1] = lp_build_const_int32(base->gallivm,
697 si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
698
699 if (shader->fs_write_all && shader->nr_cbufs > 1) {
700 int i;
701
702 /* Specify that this is not yet the last export */
703 last_args[2] = lp_build_const_int32(base->gallivm, 0);
704
705 for (i = 1; i < shader->nr_cbufs; i++) {
706 /* Specify the target we are exporting */
707 last_args[3] = lp_build_const_int32(base->gallivm,
708 V_008DFC_SQ_EXP_MRT + i);
709
710 lp_build_intrinsic(base->gallivm->builder,
711 "llvm.SI.export",
712 LLVMVoidTypeInContext(base->gallivm->context),
713 last_args, 9);
714
715 si_shader_ctx->shader->spi_shader_col_format |=
716 si_shader_ctx->shader->spi_shader_col_format << 4;
717 }
718
719 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
720 }
721
722 /* Specify that this is the last export */
723 last_args[2] = lp_build_const_int32(base->gallivm, 1);
724
725 lp_build_intrinsic(base->gallivm->builder,
726 "llvm.SI.export",
727 LLVMVoidTypeInContext(base->gallivm->context),
728 last_args, 9);
729
730 /* XXX: Look up what this function does */
731 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
732 }
733
734 static void tex_fetch_args(
735 struct lp_build_tgsi_context * bld_base,
736 struct lp_build_emit_data * emit_data)
737 {
738 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
739 struct gallivm_state *gallivm = bld_base->base.gallivm;
740 const struct tgsi_full_instruction * inst = emit_data->inst;
741 unsigned opcode = inst->Instruction.Opcode;
742 unsigned target = inst->Texture.Texture;
743 LLVMValueRef ptr;
744 LLVMValueRef offset;
745 LLVMValueRef coords[4];
746 LLVMValueRef address[16];
747 unsigned count = 0;
748 unsigned chan;
749
750 /* WriteMask */
751 /* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
752 emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm, 0xf);
753
754 /* Fetch and project texture coordinates */
755 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
756 for (chan = 0; chan < 3; chan++ ) {
757 coords[chan] = lp_build_emit_fetch(bld_base,
758 emit_data->inst, 0,
759 chan);
760 if (opcode == TGSI_OPCODE_TXP)
761 coords[chan] = lp_build_emit_llvm_binary(bld_base,
762 TGSI_OPCODE_DIV,
763 coords[chan],
764 coords[3]);
765 }
766
767 if (opcode == TGSI_OPCODE_TXP)
768 coords[3] = bld_base->base.one;
769
770 /* Pack LOD bias value */
771 if (opcode == TGSI_OPCODE_TXB)
772 address[count++] = coords[3];
773
774 if ((target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE) &&
775 opcode != TGSI_OPCODE_TXQ)
776 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
777
778 /* Pack depth comparison value */
779 switch (target) {
780 case TGSI_TEXTURE_SHADOW1D:
781 case TGSI_TEXTURE_SHADOW1D_ARRAY:
782 case TGSI_TEXTURE_SHADOW2D:
783 case TGSI_TEXTURE_SHADOWRECT:
784 address[count++] = coords[2];
785 break;
786 case TGSI_TEXTURE_SHADOWCUBE:
787 case TGSI_TEXTURE_SHADOW2D_ARRAY:
788 address[count++] = coords[3];
789 break;
790 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
791 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
792 }
793
794 /* Pack texture coordinates */
795 address[count++] = coords[0];
796 switch (target) {
797 case TGSI_TEXTURE_2D:
798 case TGSI_TEXTURE_2D_ARRAY:
799 case TGSI_TEXTURE_3D:
800 case TGSI_TEXTURE_CUBE:
801 case TGSI_TEXTURE_RECT:
802 case TGSI_TEXTURE_SHADOW2D:
803 case TGSI_TEXTURE_SHADOWRECT:
804 case TGSI_TEXTURE_SHADOW2D_ARRAY:
805 case TGSI_TEXTURE_SHADOWCUBE:
806 case TGSI_TEXTURE_2D_MSAA:
807 case TGSI_TEXTURE_2D_ARRAY_MSAA:
808 case TGSI_TEXTURE_CUBE_ARRAY:
809 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
810 address[count++] = coords[1];
811 }
812 switch (target) {
813 case TGSI_TEXTURE_3D:
814 case TGSI_TEXTURE_CUBE:
815 case TGSI_TEXTURE_SHADOWCUBE:
816 case TGSI_TEXTURE_CUBE_ARRAY:
817 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
818 address[count++] = coords[2];
819 }
820
821 /* Pack array slice */
822 switch (target) {
823 case TGSI_TEXTURE_1D_ARRAY:
824 address[count++] = coords[1];
825 }
826 switch (target) {
827 case TGSI_TEXTURE_2D_ARRAY:
828 case TGSI_TEXTURE_2D_ARRAY_MSAA:
829 case TGSI_TEXTURE_SHADOW2D_ARRAY:
830 address[count++] = coords[2];
831 }
832 switch (target) {
833 case TGSI_TEXTURE_CUBE_ARRAY:
834 case TGSI_TEXTURE_SHADOW1D_ARRAY:
835 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
836 address[count++] = coords[3];
837 }
838
839 /* Pack LOD */
840 if (opcode == TGSI_OPCODE_TXL)
841 address[count++] = coords[3];
842
843 if (count > 16) {
844 assert(!"Cannot handle more than 16 texture address parameters");
845 count = 16;
846 }
847
848 for (chan = 0; chan < count; chan++ ) {
849 address[chan] = LLVMBuildBitCast(gallivm->builder,
850 address[chan],
851 LLVMInt32TypeInContext(gallivm->context),
852 "");
853 }
854
855 /* Pad to power of two vector */
856 while (count < util_next_power_of_two(count))
857 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
858
859 emit_data->args[1] = lp_build_gather_values(gallivm, address, count);
860
861 /* Resource */
862 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
863 offset = lp_build_const_int32(bld_base->base.gallivm,
864 emit_data->inst->Src[1].Register.Index);
865 emit_data->args[2] = build_indexed_load(bld_base->base.gallivm,
866 ptr, offset);
867
868 /* Sampler */
869 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
870 offset = lp_build_const_int32(bld_base->base.gallivm,
871 emit_data->inst->Src[1].Register.Index);
872 emit_data->args[3] = build_indexed_load(bld_base->base.gallivm,
873 ptr, offset);
874
875 /* Dimensions */
876 emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm, target);
877
878 emit_data->arg_count = 5;
879 /* XXX: To optimize, we could use a float or v2f32, if the last bits of
880 * the writemask are clear */
881 emit_data->dst_type = LLVMVectorType(
882 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
883 4);
884 }
885
886 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
887 struct lp_build_tgsi_context * bld_base,
888 struct lp_build_emit_data * emit_data)
889 {
890 struct lp_build_context * base = &bld_base->base;
891 char intr_name[23];
892
893 sprintf(intr_name, "%sv%ui32", action->intr_name,
894 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[1])));
895
896 emit_data->output[emit_data->chan] = lp_build_intrinsic(
897 base->gallivm->builder, intr_name, emit_data->dst_type,
898 emit_data->args, emit_data->arg_count);
899 }
900
901 static const struct lp_build_tgsi_action tex_action = {
902 .fetch_args = tex_fetch_args,
903 .emit = build_tex_intrinsic,
904 .intr_name = "llvm.SI.sample."
905 };
906
907 static const struct lp_build_tgsi_action txb_action = {
908 .fetch_args = tex_fetch_args,
909 .emit = build_tex_intrinsic,
910 .intr_name = "llvm.SI.sampleb."
911 };
912
913 static const struct lp_build_tgsi_action txl_action = {
914 .fetch_args = tex_fetch_args,
915 .emit = build_tex_intrinsic,
916 .intr_name = "llvm.SI.samplel."
917 };
918
919 static void create_function(struct si_shader_context *si_shader_ctx)
920 {
921 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
922 LLVMTypeRef params[5], f, i8, i32;
923 unsigned i;
924
925 f = LLVMFloatTypeInContext(gallivm->context);
926 i8 = LLVMInt8TypeInContext(gallivm->context);
927 i32 = LLVMInt32TypeInContext(gallivm->context);
928
929 params[SI_PARAM_CONST] = LLVMPointerType(f, CONST_ADDR_SPACE);
930 params[SI_PARAM_SAMPLER] = LLVMPointerType(LLVMVectorType(i8, 16), CONST_ADDR_SPACE);
931 params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), CONST_ADDR_SPACE);
932
933 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
934 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
935 params[SI_PARAM_VERTEX_INDEX] = i32;
936 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 5);
937 } else {
938 params[SI_PARAM_PRIM_MASK] = LLVMInt32TypeInContext(gallivm->context);
939 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 4);
940 }
941
942 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
943 for (i = SI_PARAM_CONST; i <= SI_PARAM_VERTEX_BUFFER; ++i) {
944 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
945 LLVMAddAttribute(P, LLVMInRegAttribute);
946 }
947 }
948
949 int si_pipe_shader_create(
950 struct pipe_context *ctx,
951 struct si_pipe_shader *shader,
952 struct si_shader_key key)
953 {
954 struct r600_context *rctx = (struct r600_context*)ctx;
955 struct si_pipe_shader_selector *sel = shader->selector;
956 struct si_shader_context si_shader_ctx;
957 struct tgsi_shader_info shader_info;
958 struct lp_build_tgsi_context * bld_base;
959 LLVMModuleRef mod;
960 unsigned char * inst_bytes;
961 unsigned inst_byte_count;
962 unsigned i;
963 uint32_t *ptr;
964 bool dump;
965
966 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
967
968 assert(shader->shader.noutput == 0);
969 assert(shader->shader.ninterp == 0);
970 assert(shader->shader.ninput == 0);
971
972 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
973 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
974 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
975
976 tgsi_scan_shader(sel->tokens, &shader_info);
977 if (shader_info.indirect_files != 0) {
978 fprintf(stderr, "Indirect addressing not fully handled yet\n");
979 return -ENOSYS;
980 }
981
982 shader->shader.uses_kill = shader_info.uses_kill;
983 bld_base->info = &shader_info;
984 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
985 bld_base->emit_epilogue = si_llvm_emit_epilogue;
986
987 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
988 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
989 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
990 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
991
992 si_shader_ctx.radeon_bld.load_input = declare_input;
993 si_shader_ctx.tokens = sel->tokens;
994 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
995 si_shader_ctx.shader = shader;
996 si_shader_ctx.key = key;
997 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
998 si_shader_ctx.rctx = rctx;
999
1000 create_function(&si_shader_ctx);
1001
1002 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
1003
1004 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
1005 * conversion fails. */
1006 if (dump) {
1007 tgsi_dump(sel->tokens, 0);
1008 }
1009
1010 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
1011 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
1012 return -EINVAL;
1013 }
1014
1015 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
1016
1017 mod = bld_base->base.gallivm->module;
1018 if (dump) {
1019 LLVMDumpModule(mod);
1020 }
1021 radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count, "SI", dump);
1022 if (dump) {
1023 fprintf(stderr, "SI CODE:\n");
1024 for (i = 0; i < inst_byte_count; i+=4 ) {
1025 fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3],
1026 inst_bytes[i + 2], inst_bytes[i + 1],
1027 inst_bytes[i]);
1028 }
1029 }
1030
1031 shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes);
1032 shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4));
1033 shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8));
1034
1035 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
1036 tgsi_parse_free(&si_shader_ctx.parse);
1037
1038 /* copy new shader */
1039 si_resource_reference(&shader->bo, NULL);
1040 shader->bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
1041 inst_byte_count - 12);
1042 if (shader->bo == NULL) {
1043 return -ENOMEM;
1044 }
1045
1046 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1047 if (0 /*R600_BIG_ENDIAN*/) {
1048 for (i = 0; i < (inst_byte_count-12)/4; ++i) {
1049 ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4));
1050 }
1051 } else {
1052 memcpy(ptr, inst_bytes + 12, inst_byte_count - 12);
1053 }
1054 rctx->ws->buffer_unmap(shader->bo->cs_buf);
1055
1056 free(inst_bytes);
1057
1058 return 0;
1059 }
1060
1061 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
1062 {
1063 si_resource_reference(&shader->bo, NULL);
1064 }