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radeonsi: add start instance support
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "gallivm/lp_bld_arit.h"
37 #include "radeon_llvm.h"
38 #include "radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "tgsi/tgsi_info.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "radeonsi_pipe.h"
46 #include "radeonsi_shader.h"
47 #include "si_state.h"
48 #include "sid.h"
49
50 #include <assert.h>
51 #include <errno.h>
52 #include <stdio.h>
53
54 struct si_shader_context
55 {
56 struct radeon_llvm_context radeon_bld;
57 struct r600_context *rctx;
58 struct tgsi_parse_context parse;
59 struct tgsi_token * tokens;
60 struct si_pipe_shader *shader;
61 struct si_shader_key key;
62 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
63 LLVMValueRef const_md;
64 LLVMValueRef const_resource;
65 LLVMValueRef *constants;
66 LLVMValueRef *resources;
67 LLVMValueRef *samplers;
68 };
69
70 static struct si_shader_context * si_shader_context(
71 struct lp_build_tgsi_context * bld_base)
72 {
73 return (struct si_shader_context *)bld_base;
74 }
75
76
77 #define PERSPECTIVE_BASE 0
78 #define LINEAR_BASE 9
79
80 #define SAMPLE_OFFSET 0
81 #define CENTER_OFFSET 2
82 #define CENTROID_OFSET 4
83
84 #define USE_SGPR_MAX_SUFFIX_LEN 5
85 #define CONST_ADDR_SPACE 2
86 #define USER_SGPR_ADDR_SPACE 8
87
88 /**
89 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
90 *
91 * @param offset The offset parameter specifies the number of
92 * elements to offset, not the number of bytes or dwords. An element is the
93 * the type pointed to by the base_ptr parameter (e.g. int is the element of
94 * an int* pointer)
95 *
96 * When LLVM lowers the load instruction, it will convert the element offset
97 * into a dword offset automatically.
98 *
99 */
100 static LLVMValueRef build_indexed_load(
101 struct si_shader_context * si_shader_ctx,
102 LLVMValueRef base_ptr,
103 LLVMValueRef offset)
104 {
105 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
106
107 LLVMValueRef computed_ptr = LLVMBuildGEP(
108 base->gallivm->builder, base_ptr, &offset, 1, "");
109
110 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
111 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
112 return result;
113 }
114
115 static void declare_input_vs(
116 struct si_shader_context * si_shader_ctx,
117 unsigned input_index,
118 const struct tgsi_full_declaration *decl)
119 {
120 LLVMValueRef t_list_ptr;
121 LLVMValueRef t_offset;
122 LLVMValueRef t_list;
123 LLVMValueRef attribute_offset;
124 LLVMValueRef buffer_index_reg;
125 LLVMValueRef args[3];
126 LLVMTypeRef vec4_type;
127 LLVMValueRef input;
128 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
129 //struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[input_index];
130 unsigned chan;
131
132 /* Load the T list */
133 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
134
135 t_offset = lp_build_const_int32(base->gallivm, input_index);
136
137 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
138
139 /* Build the attribute offset */
140 attribute_offset = lp_build_const_int32(base->gallivm, 0);
141
142 /* Load the buffer index, which is always stored in VGPR0
143 * for Vertex Shaders */
144 buffer_index_reg = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_ID);
145
146 vec4_type = LLVMVectorType(base->elem_type, 4);
147 args[0] = t_list;
148 args[1] = attribute_offset;
149 args[2] = buffer_index_reg;
150 input = build_intrinsic(base->gallivm->builder,
151 "llvm.SI.vs.load.input", vec4_type, args, 3,
152 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
153
154 /* Break up the vec4 into individual components */
155 for (chan = 0; chan < 4; chan++) {
156 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
157 /* XXX: Use a helper function for this. There is one in
158 * tgsi_llvm.c. */
159 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
160 LLVMBuildExtractElement(base->gallivm->builder,
161 input, llvm_chan, "");
162 }
163 }
164
165 static void declare_input_fs(
166 struct si_shader_context * si_shader_ctx,
167 unsigned input_index,
168 const struct tgsi_full_declaration *decl)
169 {
170 struct si_shader *shader = &si_shader_ctx->shader->shader;
171 struct lp_build_context * base =
172 &si_shader_ctx->radeon_bld.soa.bld_base.base;
173 struct gallivm_state * gallivm = base->gallivm;
174 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
175 LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
176
177 LLVMValueRef interp_param;
178 const char * intr_name;
179
180 /* This value is:
181 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
182 * quad begins a new primitive. Bit 0 always needs
183 * to be unset)
184 * [32:16] ParamOffset
185 *
186 */
187 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
188 LLVMValueRef attr_number;
189
190 unsigned chan;
191
192 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
193 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
194 unsigned soa_index =
195 radeon_llvm_reg_index_soa(input_index, chan);
196 si_shader_ctx->radeon_bld.inputs[soa_index] =
197 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
198
199 if (chan == 3)
200 /* RCP for fragcoord.w */
201 si_shader_ctx->radeon_bld.inputs[soa_index] =
202 LLVMBuildFDiv(gallivm->builder,
203 lp_build_const_float(gallivm, 1.0f),
204 si_shader_ctx->radeon_bld.inputs[soa_index],
205 "");
206 }
207 return;
208 }
209
210 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
211 LLVMValueRef face, is_face_positive;
212
213 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
214
215 is_face_positive = LLVMBuildFCmp(gallivm->builder,
216 LLVMRealUGT, face,
217 lp_build_const_float(gallivm, 0.0f),
218 "");
219
220 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
221 LLVMBuildSelect(gallivm->builder,
222 is_face_positive,
223 lp_build_const_float(gallivm, 1.0f),
224 lp_build_const_float(gallivm, 0.0f),
225 "");
226 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
227 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
228 lp_build_const_float(gallivm, 0.0f);
229 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
230 lp_build_const_float(gallivm, 1.0f);
231
232 return;
233 }
234
235 shader->input[input_index].param_offset = shader->ninterp++;
236 attr_number = lp_build_const_int32(gallivm,
237 shader->input[input_index].param_offset);
238
239 /* XXX: Handle all possible interpolation modes */
240 switch (decl->Interp.Interpolate) {
241 case TGSI_INTERPOLATE_COLOR:
242 if (si_shader_ctx->key.flatshade) {
243 interp_param = 0;
244 } else {
245 if (decl->Interp.Centroid)
246 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
247 else
248 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
249 }
250 break;
251 case TGSI_INTERPOLATE_CONSTANT:
252 interp_param = 0;
253 break;
254 case TGSI_INTERPOLATE_LINEAR:
255 if (decl->Interp.Centroid)
256 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
257 else
258 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
259 break;
260 case TGSI_INTERPOLATE_PERSPECTIVE:
261 if (decl->Interp.Centroid)
262 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
263 else
264 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
265 break;
266 default:
267 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
268 return;
269 }
270
271 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
272
273 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
274 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
275 si_shader_ctx->key.color_two_side) {
276 LLVMValueRef args[4];
277 LLVMValueRef face, is_face_positive;
278 LLVMValueRef back_attr_number =
279 lp_build_const_int32(gallivm,
280 shader->input[input_index].param_offset + 1);
281
282 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
283
284 is_face_positive = LLVMBuildFCmp(gallivm->builder,
285 LLVMRealUGT, face,
286 lp_build_const_float(gallivm, 0.0f),
287 "");
288
289 args[2] = params;
290 args[3] = interp_param;
291 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
292 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
293 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
294 LLVMValueRef front, back;
295
296 args[0] = llvm_chan;
297 args[1] = attr_number;
298 front = build_intrinsic(base->gallivm->builder, intr_name,
299 input_type, args, args[3] ? 4 : 3,
300 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
301
302 args[1] = back_attr_number;
303 back = build_intrinsic(base->gallivm->builder, intr_name,
304 input_type, args, args[3] ? 4 : 3,
305 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
306
307 si_shader_ctx->radeon_bld.inputs[soa_index] =
308 LLVMBuildSelect(gallivm->builder,
309 is_face_positive,
310 front,
311 back,
312 "");
313 }
314
315 shader->ninterp++;
316 } else {
317 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
318 LLVMValueRef args[4];
319 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
320 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
321 args[0] = llvm_chan;
322 args[1] = attr_number;
323 args[2] = params;
324 args[3] = interp_param;
325 si_shader_ctx->radeon_bld.inputs[soa_index] =
326 build_intrinsic(base->gallivm->builder, intr_name,
327 input_type, args, args[3] ? 4 : 3,
328 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
329 }
330 }
331 }
332
333 static void declare_input(
334 struct radeon_llvm_context * radeon_bld,
335 unsigned input_index,
336 const struct tgsi_full_declaration *decl)
337 {
338 struct si_shader_context * si_shader_ctx =
339 si_shader_context(&radeon_bld->soa.bld_base);
340 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
341 declare_input_vs(si_shader_ctx, input_index, decl);
342 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
343 declare_input_fs(si_shader_ctx, input_index, decl);
344 } else {
345 fprintf(stderr, "Warning: Unsupported shader type,\n");
346 }
347 }
348
349 static void declare_system_value(
350 struct radeon_llvm_context * radeon_bld,
351 unsigned index,
352 const struct tgsi_full_declaration *decl)
353 {
354 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
355
356 LLVMValueRef value = 0;
357
358 switch (decl->Semantic.Name) {
359 case TGSI_SEMANTIC_INSTANCEID:
360 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_INSTANCE_ID);
361 value = LLVMBuildAdd(gallivm->builder, value,
362 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
363 break;
364
365 case TGSI_SEMANTIC_VERTEXID:
366 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_VERTEX_ID);
367 break;
368
369 default:
370 assert(!"unknown system value");
371 return;
372 }
373
374 radeon_bld->system_values[index] = value;
375 }
376
377 static LLVMValueRef fetch_constant(
378 struct lp_build_tgsi_context * bld_base,
379 const struct tgsi_full_src_register *reg,
380 enum tgsi_opcode_type type,
381 unsigned swizzle)
382 {
383 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
384 struct lp_build_context * base = &bld_base->base;
385 const struct tgsi_ind_register *ireg = &reg->Indirect;
386 unsigned idx;
387
388 LLVMValueRef args[2];
389 LLVMValueRef addr;
390 LLVMValueRef result;
391
392 if (swizzle == LP_CHAN_ALL) {
393 unsigned chan;
394 LLVMValueRef values[4];
395 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
396 values[chan] = fetch_constant(bld_base, reg, type, chan);
397
398 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
399 }
400
401 idx = reg->Register.Index * 4 + swizzle;
402 if (!reg->Register.Indirect)
403 return bitcast(bld_base, type, si_shader_ctx->constants[idx]);
404
405 args[0] = si_shader_ctx->const_resource;
406 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
407 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
408 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
409 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
410 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
411
412 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
413 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
414
415 return bitcast(bld_base, type, result);
416 }
417
418 /* Initialize arguments for the shader export intrinsic */
419 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
420 struct tgsi_full_declaration *d,
421 unsigned index,
422 unsigned target,
423 LLVMValueRef *args)
424 {
425 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
426 struct lp_build_context *uint =
427 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
428 struct lp_build_context *base = &bld_base->base;
429 unsigned compressed = 0;
430 unsigned chan;
431
432 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
433 int cbuf = target - V_008DFC_SQ_EXP_MRT;
434
435 if (cbuf >= 0 && cbuf < 8) {
436 compressed = (si_shader_ctx->key.export_16bpc >> cbuf) & 0x1;
437
438 if (compressed)
439 si_shader_ctx->shader->spi_shader_col_format |=
440 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
441 else
442 si_shader_ctx->shader->spi_shader_col_format |=
443 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
444 }
445 }
446
447 if (compressed) {
448 /* Pixel shader needs to pack output values before export */
449 for (chan = 0; chan < 2; chan++ ) {
450 LLVMValueRef *out_ptr =
451 si_shader_ctx->radeon_bld.soa.outputs[index];
452 args[0] = LLVMBuildLoad(base->gallivm->builder,
453 out_ptr[2 * chan], "");
454 args[1] = LLVMBuildLoad(base->gallivm->builder,
455 out_ptr[2 * chan + 1], "");
456 args[chan + 5] =
457 build_intrinsic(base->gallivm->builder,
458 "llvm.SI.packf16",
459 LLVMInt32TypeInContext(base->gallivm->context),
460 args, 2,
461 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
462 args[chan + 7] = args[chan + 5] =
463 LLVMBuildBitCast(base->gallivm->builder,
464 args[chan + 5],
465 LLVMFloatTypeInContext(base->gallivm->context),
466 "");
467 }
468
469 /* Set COMPR flag */
470 args[4] = uint->one;
471 } else {
472 for (chan = 0; chan < 4; chan++ ) {
473 LLVMValueRef out_ptr =
474 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
475 /* +5 because the first output value will be
476 * the 6th argument to the intrinsic. */
477 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
478 out_ptr, "");
479 }
480
481 /* Clear COMPR flag */
482 args[4] = uint->zero;
483 }
484
485 /* XXX: This controls which components of the output
486 * registers actually get exported. (e.g bit 0 means export
487 * X component, bit 1 means export Y component, etc.) I'm
488 * hard coding this to 0xf for now. In the future, we might
489 * want to do something else. */
490 args[0] = lp_build_const_int32(base->gallivm, 0xf);
491
492 /* Specify whether the EXEC mask represents the valid mask */
493 args[1] = uint->zero;
494
495 /* Specify whether this is the last export */
496 args[2] = uint->zero;
497
498 /* Specify the target we are exporting */
499 args[3] = lp_build_const_int32(base->gallivm, target);
500
501 /* XXX: We probably need to keep track of the output
502 * values, so we know what we are passing to the next
503 * stage. */
504 }
505
506 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
507 unsigned index)
508 {
509 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
510 struct gallivm_state *gallivm = bld_base->base.gallivm;
511
512 if (si_shader_ctx->key.alpha_func != PIPE_FUNC_NEVER) {
513 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
514 LLVMValueRef alpha_pass =
515 lp_build_cmp(&bld_base->base,
516 si_shader_ctx->key.alpha_func,
517 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
518 lp_build_const_float(gallivm, si_shader_ctx->key.alpha_ref));
519 LLVMValueRef arg =
520 lp_build_select(&bld_base->base,
521 alpha_pass,
522 lp_build_const_float(gallivm, 1.0f),
523 lp_build_const_float(gallivm, -1.0f));
524
525 build_intrinsic(gallivm->builder,
526 "llvm.AMDGPU.kill",
527 LLVMVoidTypeInContext(gallivm->context),
528 &arg, 1, 0);
529 } else {
530 build_intrinsic(gallivm->builder,
531 "llvm.AMDGPU.kilp",
532 LLVMVoidTypeInContext(gallivm->context),
533 NULL, 0, 0);
534 }
535 }
536
537 /* XXX: This is partially implemented for VS only at this point. It is not complete */
538 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
539 {
540 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
541 struct si_shader * shader = &si_shader_ctx->shader->shader;
542 struct lp_build_context * base = &bld_base->base;
543 struct lp_build_context * uint =
544 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
545 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
546 LLVMValueRef args[9];
547 LLVMValueRef last_args[9] = { 0 };
548 unsigned color_count = 0;
549 unsigned param_count = 0;
550 int depth_index = -1, stencil_index = -1;
551
552 while (!tgsi_parse_end_of_tokens(parse)) {
553 struct tgsi_full_declaration *d =
554 &parse->FullToken.FullDeclaration;
555 unsigned target;
556 unsigned index;
557 int i;
558
559 tgsi_parse_token(parse);
560
561 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
562 parse->FullToken.FullProperty.Property.PropertyName ==
563 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
564 shader->fs_write_all = TRUE;
565
566 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
567 continue;
568
569 switch (d->Declaration.File) {
570 case TGSI_FILE_INPUT:
571 i = shader->ninput++;
572 shader->input[i].name = d->Semantic.Name;
573 shader->input[i].sid = d->Semantic.Index;
574 shader->input[i].interpolate = d->Interp.Interpolate;
575 shader->input[i].centroid = d->Interp.Centroid;
576 continue;
577
578 case TGSI_FILE_OUTPUT:
579 i = shader->noutput++;
580 shader->output[i].name = d->Semantic.Name;
581 shader->output[i].sid = d->Semantic.Index;
582 shader->output[i].interpolate = d->Interp.Interpolate;
583 break;
584
585 default:
586 continue;
587 }
588
589 for (index = d->Range.First; index <= d->Range.Last; index++) {
590 /* Select the correct target */
591 switch(d->Semantic.Name) {
592 case TGSI_SEMANTIC_PSIZE:
593 target = V_008DFC_SQ_EXP_POS;
594 break;
595 case TGSI_SEMANTIC_POSITION:
596 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
597 target = V_008DFC_SQ_EXP_POS;
598 break;
599 } else {
600 depth_index = index;
601 continue;
602 }
603 case TGSI_SEMANTIC_STENCIL:
604 stencil_index = index;
605 continue;
606 case TGSI_SEMANTIC_COLOR:
607 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
608 case TGSI_SEMANTIC_BCOLOR:
609 target = V_008DFC_SQ_EXP_PARAM + param_count;
610 shader->output[i].param_offset = param_count;
611 param_count++;
612 } else {
613 target = V_008DFC_SQ_EXP_MRT + color_count;
614 if (color_count == 0 &&
615 si_shader_ctx->key.alpha_func != PIPE_FUNC_ALWAYS)
616 si_alpha_test(bld_base, index);
617
618 color_count++;
619 }
620 break;
621 case TGSI_SEMANTIC_FOG:
622 case TGSI_SEMANTIC_GENERIC:
623 target = V_008DFC_SQ_EXP_PARAM + param_count;
624 shader->output[i].param_offset = param_count;
625 param_count++;
626 break;
627 default:
628 target = 0;
629 fprintf(stderr,
630 "Warning: SI unhandled output type:%d\n",
631 d->Semantic.Name);
632 }
633
634 si_llvm_init_export_args(bld_base, d, index, target, args);
635
636 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
637 (d->Semantic.Name == TGSI_SEMANTIC_POSITION) :
638 (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) {
639 if (last_args[0]) {
640 lp_build_intrinsic(base->gallivm->builder,
641 "llvm.SI.export",
642 LLVMVoidTypeInContext(base->gallivm->context),
643 last_args, 9);
644 }
645
646 memcpy(last_args, args, sizeof(args));
647 } else {
648 lp_build_intrinsic(base->gallivm->builder,
649 "llvm.SI.export",
650 LLVMVoidTypeInContext(base->gallivm->context),
651 args, 9);
652 }
653
654 }
655 }
656
657 if (depth_index >= 0 || stencil_index >= 0) {
658 LLVMValueRef out_ptr;
659 unsigned mask = 0;
660
661 /* Specify the target we are exporting */
662 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
663
664 if (depth_index >= 0) {
665 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
666 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
667 mask |= 0x1;
668
669 if (stencil_index < 0) {
670 args[6] =
671 args[7] =
672 args[8] = args[5];
673 }
674 }
675
676 if (stencil_index >= 0) {
677 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
678 args[7] =
679 args[8] =
680 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
681 mask |= 0x2;
682
683 if (depth_index < 0)
684 args[5] = args[6];
685 }
686
687 /* Specify which components to enable */
688 args[0] = lp_build_const_int32(base->gallivm, mask);
689
690 args[1] =
691 args[2] =
692 args[4] = uint->zero;
693
694 if (last_args[0])
695 lp_build_intrinsic(base->gallivm->builder,
696 "llvm.SI.export",
697 LLVMVoidTypeInContext(base->gallivm->context),
698 args, 9);
699 else
700 memcpy(last_args, args, sizeof(args));
701 }
702
703 if (!last_args[0]) {
704 assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
705
706 /* Specify which components to enable */
707 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
708
709 /* Specify the target we are exporting */
710 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
711
712 /* Set COMPR flag to zero to export data as 32-bit */
713 last_args[4] = uint->zero;
714
715 /* dummy bits */
716 last_args[5]= uint->zero;
717 last_args[6]= uint->zero;
718 last_args[7]= uint->zero;
719 last_args[8]= uint->zero;
720
721 si_shader_ctx->shader->spi_shader_col_format |=
722 V_028714_SPI_SHADER_32_ABGR;
723 }
724
725 /* Specify whether the EXEC mask represents the valid mask */
726 last_args[1] = lp_build_const_int32(base->gallivm,
727 si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
728
729 if (shader->fs_write_all && shader->nr_cbufs > 1) {
730 int i;
731
732 /* Specify that this is not yet the last export */
733 last_args[2] = lp_build_const_int32(base->gallivm, 0);
734
735 for (i = 1; i < shader->nr_cbufs; i++) {
736 /* Specify the target we are exporting */
737 last_args[3] = lp_build_const_int32(base->gallivm,
738 V_008DFC_SQ_EXP_MRT + i);
739
740 lp_build_intrinsic(base->gallivm->builder,
741 "llvm.SI.export",
742 LLVMVoidTypeInContext(base->gallivm->context),
743 last_args, 9);
744
745 si_shader_ctx->shader->spi_shader_col_format |=
746 si_shader_ctx->shader->spi_shader_col_format << 4;
747 }
748
749 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
750 }
751
752 /* Specify that this is the last export */
753 last_args[2] = lp_build_const_int32(base->gallivm, 1);
754
755 lp_build_intrinsic(base->gallivm->builder,
756 "llvm.SI.export",
757 LLVMVoidTypeInContext(base->gallivm->context),
758 last_args, 9);
759
760 /* XXX: Look up what this function does */
761 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
762 }
763
764 static void tex_fetch_args(
765 struct lp_build_tgsi_context * bld_base,
766 struct lp_build_emit_data * emit_data)
767 {
768 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
769 struct gallivm_state *gallivm = bld_base->base.gallivm;
770 const struct tgsi_full_instruction * inst = emit_data->inst;
771 unsigned opcode = inst->Instruction.Opcode;
772 unsigned target = inst->Texture.Texture;
773 LLVMValueRef coords[4];
774 LLVMValueRef address[16];
775 unsigned count = 0;
776 unsigned chan;
777
778 /* WriteMask */
779 /* XXX: should be optimized using emit_data->inst->Dst[0].Register.WriteMask*/
780 emit_data->args[0] = lp_build_const_int32(bld_base->base.gallivm, 0xf);
781
782 /* Fetch and project texture coordinates */
783 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
784 for (chan = 0; chan < 3; chan++ ) {
785 coords[chan] = lp_build_emit_fetch(bld_base,
786 emit_data->inst, 0,
787 chan);
788 if (opcode == TGSI_OPCODE_TXP)
789 coords[chan] = lp_build_emit_llvm_binary(bld_base,
790 TGSI_OPCODE_DIV,
791 coords[chan],
792 coords[3]);
793 }
794
795 if (opcode == TGSI_OPCODE_TXP)
796 coords[3] = bld_base->base.one;
797
798 /* Pack LOD bias value */
799 if (opcode == TGSI_OPCODE_TXB)
800 address[count++] = coords[3];
801
802 if ((target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE) &&
803 opcode != TGSI_OPCODE_TXQ)
804 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
805
806 /* Pack depth comparison value */
807 switch (target) {
808 case TGSI_TEXTURE_SHADOW1D:
809 case TGSI_TEXTURE_SHADOW1D_ARRAY:
810 case TGSI_TEXTURE_SHADOW2D:
811 case TGSI_TEXTURE_SHADOWRECT:
812 address[count++] = coords[2];
813 break;
814 case TGSI_TEXTURE_SHADOWCUBE:
815 case TGSI_TEXTURE_SHADOW2D_ARRAY:
816 address[count++] = coords[3];
817 break;
818 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
819 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
820 }
821
822 /* Pack texture coordinates */
823 address[count++] = coords[0];
824 switch (target) {
825 case TGSI_TEXTURE_2D:
826 case TGSI_TEXTURE_2D_ARRAY:
827 case TGSI_TEXTURE_3D:
828 case TGSI_TEXTURE_CUBE:
829 case TGSI_TEXTURE_RECT:
830 case TGSI_TEXTURE_SHADOW2D:
831 case TGSI_TEXTURE_SHADOWRECT:
832 case TGSI_TEXTURE_SHADOW2D_ARRAY:
833 case TGSI_TEXTURE_SHADOWCUBE:
834 case TGSI_TEXTURE_2D_MSAA:
835 case TGSI_TEXTURE_2D_ARRAY_MSAA:
836 case TGSI_TEXTURE_CUBE_ARRAY:
837 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
838 address[count++] = coords[1];
839 }
840 switch (target) {
841 case TGSI_TEXTURE_3D:
842 case TGSI_TEXTURE_CUBE:
843 case TGSI_TEXTURE_SHADOWCUBE:
844 case TGSI_TEXTURE_CUBE_ARRAY:
845 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
846 address[count++] = coords[2];
847 }
848
849 /* Pack array slice */
850 switch (target) {
851 case TGSI_TEXTURE_1D_ARRAY:
852 address[count++] = coords[1];
853 }
854 switch (target) {
855 case TGSI_TEXTURE_2D_ARRAY:
856 case TGSI_TEXTURE_2D_ARRAY_MSAA:
857 case TGSI_TEXTURE_SHADOW2D_ARRAY:
858 address[count++] = coords[2];
859 }
860 switch (target) {
861 case TGSI_TEXTURE_CUBE_ARRAY:
862 case TGSI_TEXTURE_SHADOW1D_ARRAY:
863 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
864 address[count++] = coords[3];
865 }
866
867 /* Pack LOD */
868 if (opcode == TGSI_OPCODE_TXL)
869 address[count++] = coords[3];
870
871 if (count > 16) {
872 assert(!"Cannot handle more than 16 texture address parameters");
873 count = 16;
874 }
875
876 for (chan = 0; chan < count; chan++ ) {
877 address[chan] = LLVMBuildBitCast(gallivm->builder,
878 address[chan],
879 LLVMInt32TypeInContext(gallivm->context),
880 "");
881 }
882
883 /* Pad to power of two vector */
884 while (count < util_next_power_of_two(count))
885 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
886
887 emit_data->args[1] = lp_build_gather_values(gallivm, address, count);
888
889 /* Resource */
890 emit_data->args[2] = si_shader_ctx->resources[emit_data->inst->Src[1].Register.Index];
891
892 /* Sampler */
893 emit_data->args[3] = si_shader_ctx->samplers[emit_data->inst->Src[1].Register.Index];
894
895 /* Dimensions */
896 emit_data->args[4] = lp_build_const_int32(bld_base->base.gallivm, target);
897
898 emit_data->arg_count = 5;
899 /* XXX: To optimize, we could use a float or v2f32, if the last bits of
900 * the writemask are clear */
901 emit_data->dst_type = LLVMVectorType(
902 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
903 4);
904 }
905
906 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
907 struct lp_build_tgsi_context * bld_base,
908 struct lp_build_emit_data * emit_data)
909 {
910 struct lp_build_context * base = &bld_base->base;
911 char intr_name[23];
912
913 sprintf(intr_name, "%sv%ui32", action->intr_name,
914 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[1])));
915
916 emit_data->output[emit_data->chan] = build_intrinsic(
917 base->gallivm->builder, intr_name, emit_data->dst_type,
918 emit_data->args, emit_data->arg_count,
919 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
920 }
921
922 static const struct lp_build_tgsi_action tex_action = {
923 .fetch_args = tex_fetch_args,
924 .emit = build_tex_intrinsic,
925 .intr_name = "llvm.SI.sample."
926 };
927
928 static const struct lp_build_tgsi_action txb_action = {
929 .fetch_args = tex_fetch_args,
930 .emit = build_tex_intrinsic,
931 .intr_name = "llvm.SI.sampleb."
932 };
933
934 static const struct lp_build_tgsi_action txl_action = {
935 .fetch_args = tex_fetch_args,
936 .emit = build_tex_intrinsic,
937 .intr_name = "llvm.SI.samplel."
938 };
939
940 static void create_meta_data(struct si_shader_context *si_shader_ctx)
941 {
942 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
943 LLVMValueRef args[3];
944
945 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
946 args[1] = 0;
947 args[2] = lp_build_const_int32(gallivm, 1);
948
949 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
950 }
951
952 static void create_function(struct si_shader_context *si_shader_ctx)
953 {
954 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
955 LLVMTypeRef params[20], f32, i8, i32, v2i32, v3i32;
956 unsigned i;
957
958 i8 = LLVMInt8TypeInContext(gallivm->context);
959 i32 = LLVMInt32TypeInContext(gallivm->context);
960 f32 = LLVMFloatTypeInContext(gallivm->context);
961 v2i32 = LLVMVectorType(i32, 2);
962 v3i32 = LLVMVectorType(i32, 3);
963
964 params[SI_PARAM_CONST] = LLVMPointerType(LLVMVectorType(i8, 16), CONST_ADDR_SPACE);
965 params[SI_PARAM_SAMPLER] = params[SI_PARAM_CONST];
966 params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), CONST_ADDR_SPACE);
967
968 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
969 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
970 params[SI_PARAM_START_INSTANCE] = i32;
971 params[SI_PARAM_VERTEX_ID] = i32;
972 params[SI_PARAM_DUMMY_0] = i32;
973 params[SI_PARAM_DUMMY_1] = i32;
974 params[SI_PARAM_INSTANCE_ID] = i32;
975 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 9);
976
977 } else {
978 params[SI_PARAM_PRIM_MASK] = i32;
979 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
980 params[SI_PARAM_PERSP_CENTER] = v2i32;
981 params[SI_PARAM_PERSP_CENTROID] = v2i32;
982 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
983 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
984 params[SI_PARAM_LINEAR_CENTER] = v2i32;
985 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
986 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
987 params[SI_PARAM_POS_X_FLOAT] = f32;
988 params[SI_PARAM_POS_Y_FLOAT] = f32;
989 params[SI_PARAM_POS_Z_FLOAT] = f32;
990 params[SI_PARAM_POS_W_FLOAT] = f32;
991 params[SI_PARAM_FRONT_FACE] = f32;
992 params[SI_PARAM_ANCILLARY] = f32;
993 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
994 params[SI_PARAM_POS_FIXED_PT] = f32;
995 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 20);
996 }
997
998 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
999 for (i = SI_PARAM_CONST; i <= SI_PARAM_VERTEX_BUFFER; ++i) {
1000 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
1001 LLVMAddAttribute(P, LLVMInRegAttribute);
1002 }
1003
1004 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
1005 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1006 SI_PARAM_START_INSTANCE);
1007 LLVMAddAttribute(P, LLVMInRegAttribute);
1008 }
1009 }
1010
1011 static void preload_constants(struct si_shader_context *si_shader_ctx)
1012 {
1013 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1014 struct gallivm_state * gallivm = bld_base->base.gallivm;
1015 const struct tgsi_shader_info * info = bld_base->info;
1016
1017 unsigned i, num_const = info->file_max[TGSI_FILE_CONSTANT] + 1;
1018
1019 LLVMValueRef ptr;
1020
1021 if (num_const == 0)
1022 return;
1023
1024 /* Allocate space for the constant values */
1025 si_shader_ctx->constants = CALLOC(num_const * 4, sizeof(LLVMValueRef));
1026
1027 /* Load the resource descriptor */
1028 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1029 si_shader_ctx->const_resource = build_indexed_load(si_shader_ctx, ptr, bld_base->uint_bld.zero);
1030
1031 /* Load the constants, we rely on the code sinking to do the rest */
1032 for (i = 0; i < num_const * 4; ++i) {
1033 LLVMValueRef args[2] = {
1034 si_shader_ctx->const_resource,
1035 lp_build_const_int32(gallivm, i * 4)
1036 };
1037 si_shader_ctx->constants[i] = build_intrinsic(gallivm->builder, "llvm.SI.load.const",
1038 bld_base->base.elem_type, args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1039 }
1040 }
1041
1042 static void preload_samplers(struct si_shader_context *si_shader_ctx)
1043 {
1044 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1045 struct gallivm_state * gallivm = bld_base->base.gallivm;
1046 const struct tgsi_shader_info * info = bld_base->info;
1047
1048 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
1049
1050 LLVMValueRef res_ptr, samp_ptr;
1051 LLVMValueRef offset;
1052
1053 if (num_samplers == 0)
1054 return;
1055
1056 /* Allocate space for the values */
1057 si_shader_ctx->resources = CALLOC(num_samplers, sizeof(LLVMValueRef));
1058 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
1059
1060 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
1061 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
1062
1063 /* Load the resources and samplers, we rely on the code sinking to do the rest */
1064 for (i = 0; i < num_samplers; ++i) {
1065
1066 /* Resource */
1067 offset = lp_build_const_int32(gallivm, i);
1068 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
1069
1070 /* Sampler */
1071 offset = lp_build_const_int32(gallivm, i);
1072 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
1073 }
1074 }
1075
1076 int si_pipe_shader_create(
1077 struct pipe_context *ctx,
1078 struct si_pipe_shader *shader,
1079 struct si_shader_key key)
1080 {
1081 struct r600_context *rctx = (struct r600_context*)ctx;
1082 struct si_pipe_shader_selector *sel = shader->selector;
1083 struct si_shader_context si_shader_ctx;
1084 struct tgsi_shader_info shader_info;
1085 struct lp_build_tgsi_context * bld_base;
1086 LLVMModuleRef mod;
1087 unsigned char * inst_bytes;
1088 unsigned inst_byte_count;
1089 unsigned i;
1090 uint32_t *ptr;
1091 bool dump;
1092
1093 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
1094
1095 assert(shader->shader.noutput == 0);
1096 assert(shader->shader.ninterp == 0);
1097 assert(shader->shader.ninput == 0);
1098
1099 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
1100 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
1101 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
1102
1103 tgsi_scan_shader(sel->tokens, &shader_info);
1104 shader->shader.uses_kill = shader_info.uses_kill;
1105 shader->shader.uses_instanceid = shader_info.uses_instanceid;
1106 bld_base->info = &shader_info;
1107 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
1108 bld_base->emit_epilogue = si_llvm_emit_epilogue;
1109
1110 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1111 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
1112 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
1113 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
1114
1115 si_shader_ctx.radeon_bld.load_input = declare_input;
1116 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
1117 si_shader_ctx.tokens = sel->tokens;
1118 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
1119 si_shader_ctx.shader = shader;
1120 si_shader_ctx.key = key;
1121 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
1122 si_shader_ctx.rctx = rctx;
1123
1124 create_meta_data(&si_shader_ctx);
1125 create_function(&si_shader_ctx);
1126 preload_constants(&si_shader_ctx);
1127 preload_samplers(&si_shader_ctx);
1128
1129 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
1130
1131 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
1132 * conversion fails. */
1133 if (dump) {
1134 tgsi_dump(sel->tokens, 0);
1135 }
1136
1137 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
1138 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
1139 FREE(si_shader_ctx.constants);
1140 FREE(si_shader_ctx.resources);
1141 FREE(si_shader_ctx.samplers);
1142 return -EINVAL;
1143 }
1144
1145 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
1146
1147 mod = bld_base->base.gallivm->module;
1148 if (dump) {
1149 LLVMDumpModule(mod);
1150 }
1151 radeon_llvm_compile(mod, &inst_bytes, &inst_byte_count, "SI", dump);
1152 if (dump) {
1153 fprintf(stderr, "SI CODE:\n");
1154 for (i = 0; i < inst_byte_count; i+=4 ) {
1155 fprintf(stderr, "%02x%02x%02x%02x\n", inst_bytes[i + 3],
1156 inst_bytes[i + 2], inst_bytes[i + 1],
1157 inst_bytes[i]);
1158 }
1159 }
1160
1161 shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)inst_bytes);
1162 shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 4));
1163 shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(inst_bytes + 8));
1164
1165 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
1166 tgsi_parse_free(&si_shader_ctx.parse);
1167
1168 /* copy new shader */
1169 si_resource_reference(&shader->bo, NULL);
1170 shader->bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
1171 inst_byte_count - 12);
1172 if (shader->bo == NULL) {
1173 FREE(si_shader_ctx.constants);
1174 FREE(si_shader_ctx.resources);
1175 FREE(si_shader_ctx.samplers);
1176 return -ENOMEM;
1177 }
1178
1179 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1180 if (0 /*R600_BIG_ENDIAN*/) {
1181 for (i = 0; i < (inst_byte_count-12)/4; ++i) {
1182 ptr[i] = util_bswap32(*(uint32_t*)(inst_bytes+12 + i*4));
1183 }
1184 } else {
1185 memcpy(ptr, inst_bytes + 12, inst_byte_count - 12);
1186 }
1187 rctx->ws->buffer_unmap(shader->bo->cs_buf);
1188
1189 FREE(si_shader_ctx.constants);
1190 FREE(si_shader_ctx.resources);
1191 FREE(si_shader_ctx.samplers);
1192 free(inst_bytes);
1193
1194 return 0;
1195 }
1196
1197 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
1198 {
1199 si_resource_reference(&shader->bo, NULL);
1200 }