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radeonsi: Read config values from the .AMDGPU.config ELF section
[mesa.git] / src / gallium / drivers / radeonsi / radeonsi_shader.c
1
2 /*
3 * Copyright 2012 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Tom Stellard <thomas.stellard@amd.com>
26 * Michel Dänzer <michel.daenzer@amd.com>
27 * Christian König <christian.koenig@amd.com>
28 */
29
30 #include "gallivm/lp_bld_tgsi_action.h"
31 #include "gallivm/lp_bld_const.h"
32 #include "gallivm/lp_bld_gather.h"
33 #include "gallivm/lp_bld_intr.h"
34 #include "gallivm/lp_bld_logic.h"
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "gallivm/lp_bld_arit.h"
37 #include "radeon_llvm.h"
38 #include "radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "tgsi/tgsi_info.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "radeonsi_pipe.h"
46 #include "radeonsi_shader.h"
47 #include "si_state.h"
48 #include "sid.h"
49
50 #include <assert.h>
51 #include <errno.h>
52 #include <stdio.h>
53
54 struct si_shader_context
55 {
56 struct radeon_llvm_context radeon_bld;
57 struct tgsi_parse_context parse;
58 struct tgsi_token * tokens;
59 struct si_pipe_shader *shader;
60 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
61 LLVMValueRef const_md;
62 LLVMValueRef const_resource;
63 LLVMValueRef *constants;
64 LLVMValueRef *resources;
65 LLVMValueRef *samplers;
66 };
67
68 static struct si_shader_context * si_shader_context(
69 struct lp_build_tgsi_context * bld_base)
70 {
71 return (struct si_shader_context *)bld_base;
72 }
73
74
75 #define PERSPECTIVE_BASE 0
76 #define LINEAR_BASE 9
77
78 #define SAMPLE_OFFSET 0
79 #define CENTER_OFFSET 2
80 #define CENTROID_OFSET 4
81
82 #define USE_SGPR_MAX_SUFFIX_LEN 5
83 #define CONST_ADDR_SPACE 2
84 #define USER_SGPR_ADDR_SPACE 8
85
86 /**
87 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
88 *
89 * @param offset The offset parameter specifies the number of
90 * elements to offset, not the number of bytes or dwords. An element is the
91 * the type pointed to by the base_ptr parameter (e.g. int is the element of
92 * an int* pointer)
93 *
94 * When LLVM lowers the load instruction, it will convert the element offset
95 * into a dword offset automatically.
96 *
97 */
98 static LLVMValueRef build_indexed_load(
99 struct si_shader_context * si_shader_ctx,
100 LLVMValueRef base_ptr,
101 LLVMValueRef offset)
102 {
103 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
104
105 LLVMValueRef computed_ptr = LLVMBuildGEP(
106 base->gallivm->builder, base_ptr, &offset, 1, "");
107
108 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
109 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
110 return result;
111 }
112
113 static LLVMValueRef get_instance_index(
114 struct radeon_llvm_context * radeon_bld,
115 unsigned divisor)
116 {
117 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
118
119 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_INSTANCE_ID);
120 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
121 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
122
123 if (divisor > 1)
124 result = LLVMBuildUDiv(gallivm->builder, result,
125 lp_build_const_int32(gallivm, divisor), "");
126
127 return result;
128 }
129
130 static void declare_input_vs(
131 struct si_shader_context * si_shader_ctx,
132 unsigned input_index,
133 const struct tgsi_full_declaration *decl)
134 {
135 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
136 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
137
138 unsigned chan;
139
140 LLVMValueRef t_list_ptr;
141 LLVMValueRef t_offset;
142 LLVMValueRef t_list;
143 LLVMValueRef attribute_offset;
144 LLVMValueRef buffer_index;
145 LLVMValueRef args[3];
146 LLVMTypeRef vec4_type;
147 LLVMValueRef input;
148
149 /* Load the T list */
150 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
151
152 t_offset = lp_build_const_int32(base->gallivm, input_index);
153
154 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
155
156 /* Build the attribute offset */
157 attribute_offset = lp_build_const_int32(base->gallivm, 0);
158
159 if (divisor) {
160 /* Build index from instance ID, start instance and divisor */
161 si_shader_ctx->shader->shader.uses_instanceid = true;
162 buffer_index = get_instance_index(&si_shader_ctx->radeon_bld, divisor);
163 } else {
164 /* Load the buffer index, which is always stored in VGPR0
165 * for Vertex Shaders */
166 buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_ID);
167 }
168
169 vec4_type = LLVMVectorType(base->elem_type, 4);
170 args[0] = t_list;
171 args[1] = attribute_offset;
172 args[2] = buffer_index;
173 input = build_intrinsic(base->gallivm->builder,
174 "llvm.SI.vs.load.input", vec4_type, args, 3,
175 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
176
177 /* Break up the vec4 into individual components */
178 for (chan = 0; chan < 4; chan++) {
179 LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
180 /* XXX: Use a helper function for this. There is one in
181 * tgsi_llvm.c. */
182 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
183 LLVMBuildExtractElement(base->gallivm->builder,
184 input, llvm_chan, "");
185 }
186 }
187
188 static void declare_input_fs(
189 struct si_shader_context * si_shader_ctx,
190 unsigned input_index,
191 const struct tgsi_full_declaration *decl)
192 {
193 struct si_shader *shader = &si_shader_ctx->shader->shader;
194 struct lp_build_context * base =
195 &si_shader_ctx->radeon_bld.soa.bld_base.base;
196 struct gallivm_state * gallivm = base->gallivm;
197 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
198 LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
199
200 LLVMValueRef interp_param;
201 const char * intr_name;
202
203 /* This value is:
204 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
205 * quad begins a new primitive. Bit 0 always needs
206 * to be unset)
207 * [32:16] ParamOffset
208 *
209 */
210 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
211 LLVMValueRef attr_number;
212
213 unsigned chan;
214
215 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
216 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
217 unsigned soa_index =
218 radeon_llvm_reg_index_soa(input_index, chan);
219 si_shader_ctx->radeon_bld.inputs[soa_index] =
220 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
221
222 if (chan == 3)
223 /* RCP for fragcoord.w */
224 si_shader_ctx->radeon_bld.inputs[soa_index] =
225 LLVMBuildFDiv(gallivm->builder,
226 lp_build_const_float(gallivm, 1.0f),
227 si_shader_ctx->radeon_bld.inputs[soa_index],
228 "");
229 }
230 return;
231 }
232
233 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
234 LLVMValueRef face, is_face_positive;
235
236 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
237
238 is_face_positive = LLVMBuildFCmp(gallivm->builder,
239 LLVMRealUGT, face,
240 lp_build_const_float(gallivm, 0.0f),
241 "");
242
243 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
244 LLVMBuildSelect(gallivm->builder,
245 is_face_positive,
246 lp_build_const_float(gallivm, 1.0f),
247 lp_build_const_float(gallivm, 0.0f),
248 "");
249 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
250 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
251 lp_build_const_float(gallivm, 0.0f);
252 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
253 lp_build_const_float(gallivm, 1.0f);
254
255 return;
256 }
257
258 shader->input[input_index].param_offset = shader->ninterp++;
259 attr_number = lp_build_const_int32(gallivm,
260 shader->input[input_index].param_offset);
261
262 /* XXX: Handle all possible interpolation modes */
263 switch (decl->Interp.Interpolate) {
264 case TGSI_INTERPOLATE_COLOR:
265 if (si_shader_ctx->shader->key.ps.flatshade) {
266 interp_param = 0;
267 } else {
268 if (decl->Interp.Centroid)
269 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
270 else
271 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
272 }
273 break;
274 case TGSI_INTERPOLATE_CONSTANT:
275 interp_param = 0;
276 break;
277 case TGSI_INTERPOLATE_LINEAR:
278 if (decl->Interp.Centroid)
279 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
280 else
281 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
282 break;
283 case TGSI_INTERPOLATE_PERSPECTIVE:
284 if (decl->Interp.Centroid)
285 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
286 else
287 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
288 break;
289 default:
290 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
291 return;
292 }
293
294 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
295
296 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
297 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
298 si_shader_ctx->shader->key.ps.color_two_side) {
299 LLVMValueRef args[4];
300 LLVMValueRef face, is_face_positive;
301 LLVMValueRef back_attr_number =
302 lp_build_const_int32(gallivm,
303 shader->input[input_index].param_offset + 1);
304
305 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
306
307 is_face_positive = LLVMBuildFCmp(gallivm->builder,
308 LLVMRealUGT, face,
309 lp_build_const_float(gallivm, 0.0f),
310 "");
311
312 args[2] = params;
313 args[3] = interp_param;
314 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
315 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
316 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
317 LLVMValueRef front, back;
318
319 args[0] = llvm_chan;
320 args[1] = attr_number;
321 front = build_intrinsic(base->gallivm->builder, intr_name,
322 input_type, args, args[3] ? 4 : 3,
323 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
324
325 args[1] = back_attr_number;
326 back = build_intrinsic(base->gallivm->builder, intr_name,
327 input_type, args, args[3] ? 4 : 3,
328 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
329
330 si_shader_ctx->radeon_bld.inputs[soa_index] =
331 LLVMBuildSelect(gallivm->builder,
332 is_face_positive,
333 front,
334 back,
335 "");
336 }
337
338 shader->ninterp++;
339 } else {
340 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
341 LLVMValueRef args[4];
342 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
343 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
344 args[0] = llvm_chan;
345 args[1] = attr_number;
346 args[2] = params;
347 args[3] = interp_param;
348 si_shader_ctx->radeon_bld.inputs[soa_index] =
349 build_intrinsic(base->gallivm->builder, intr_name,
350 input_type, args, args[3] ? 4 : 3,
351 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
352 }
353 }
354 }
355
356 static void declare_input(
357 struct radeon_llvm_context * radeon_bld,
358 unsigned input_index,
359 const struct tgsi_full_declaration *decl)
360 {
361 struct si_shader_context * si_shader_ctx =
362 si_shader_context(&radeon_bld->soa.bld_base);
363 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
364 declare_input_vs(si_shader_ctx, input_index, decl);
365 } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
366 declare_input_fs(si_shader_ctx, input_index, decl);
367 } else {
368 fprintf(stderr, "Warning: Unsupported shader type,\n");
369 }
370 }
371
372 static void declare_system_value(
373 struct radeon_llvm_context * radeon_bld,
374 unsigned index,
375 const struct tgsi_full_declaration *decl)
376 {
377
378 LLVMValueRef value = 0;
379
380 switch (decl->Semantic.Name) {
381 case TGSI_SEMANTIC_INSTANCEID:
382 value = get_instance_index(radeon_bld, 1);
383 break;
384
385 case TGSI_SEMANTIC_VERTEXID:
386 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_VERTEX_ID);
387 break;
388
389 default:
390 assert(!"unknown system value");
391 return;
392 }
393
394 radeon_bld->system_values[index] = value;
395 }
396
397 static LLVMValueRef fetch_constant(
398 struct lp_build_tgsi_context * bld_base,
399 const struct tgsi_full_src_register *reg,
400 enum tgsi_opcode_type type,
401 unsigned swizzle)
402 {
403 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
404 struct lp_build_context * base = &bld_base->base;
405 const struct tgsi_ind_register *ireg = &reg->Indirect;
406 unsigned idx;
407
408 LLVMValueRef args[2];
409 LLVMValueRef addr;
410 LLVMValueRef result;
411
412 if (swizzle == LP_CHAN_ALL) {
413 unsigned chan;
414 LLVMValueRef values[4];
415 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
416 values[chan] = fetch_constant(bld_base, reg, type, chan);
417
418 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
419 }
420
421 idx = reg->Register.Index * 4 + swizzle;
422 if (!reg->Register.Indirect)
423 return bitcast(bld_base, type, si_shader_ctx->constants[idx]);
424
425 args[0] = si_shader_ctx->const_resource;
426 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
427 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
428 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
429 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
430 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
431
432 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
433 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
434
435 return bitcast(bld_base, type, result);
436 }
437
438 /* Initialize arguments for the shader export intrinsic */
439 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
440 struct tgsi_full_declaration *d,
441 unsigned index,
442 unsigned target,
443 LLVMValueRef *args)
444 {
445 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
446 struct lp_build_context *uint =
447 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
448 struct lp_build_context *base = &bld_base->base;
449 unsigned compressed = 0;
450 unsigned chan;
451
452 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
453 int cbuf = target - V_008DFC_SQ_EXP_MRT;
454
455 if (cbuf >= 0 && cbuf < 8) {
456 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
457
458 if (compressed)
459 si_shader_ctx->shader->spi_shader_col_format |=
460 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
461 else
462 si_shader_ctx->shader->spi_shader_col_format |=
463 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
464 }
465 }
466
467 if (compressed) {
468 /* Pixel shader needs to pack output values before export */
469 for (chan = 0; chan < 2; chan++ ) {
470 LLVMValueRef *out_ptr =
471 si_shader_ctx->radeon_bld.soa.outputs[index];
472 args[0] = LLVMBuildLoad(base->gallivm->builder,
473 out_ptr[2 * chan], "");
474 args[1] = LLVMBuildLoad(base->gallivm->builder,
475 out_ptr[2 * chan + 1], "");
476 args[chan + 5] =
477 build_intrinsic(base->gallivm->builder,
478 "llvm.SI.packf16",
479 LLVMInt32TypeInContext(base->gallivm->context),
480 args, 2,
481 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
482 args[chan + 7] = args[chan + 5] =
483 LLVMBuildBitCast(base->gallivm->builder,
484 args[chan + 5],
485 LLVMFloatTypeInContext(base->gallivm->context),
486 "");
487 }
488
489 /* Set COMPR flag */
490 args[4] = uint->one;
491 } else {
492 for (chan = 0; chan < 4; chan++ ) {
493 LLVMValueRef out_ptr =
494 si_shader_ctx->radeon_bld.soa.outputs[index][chan];
495 /* +5 because the first output value will be
496 * the 6th argument to the intrinsic. */
497 args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
498 out_ptr, "");
499 }
500
501 /* Clear COMPR flag */
502 args[4] = uint->zero;
503 }
504
505 /* XXX: This controls which components of the output
506 * registers actually get exported. (e.g bit 0 means export
507 * X component, bit 1 means export Y component, etc.) I'm
508 * hard coding this to 0xf for now. In the future, we might
509 * want to do something else. */
510 args[0] = lp_build_const_int32(base->gallivm, 0xf);
511
512 /* Specify whether the EXEC mask represents the valid mask */
513 args[1] = uint->zero;
514
515 /* Specify whether this is the last export */
516 args[2] = uint->zero;
517
518 /* Specify the target we are exporting */
519 args[3] = lp_build_const_int32(base->gallivm, target);
520
521 /* XXX: We probably need to keep track of the output
522 * values, so we know what we are passing to the next
523 * stage. */
524 }
525
526 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
527 unsigned index)
528 {
529 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
530 struct gallivm_state *gallivm = bld_base->base.gallivm;
531
532 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
533 LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
534 LLVMValueRef alpha_pass =
535 lp_build_cmp(&bld_base->base,
536 si_shader_ctx->shader->key.ps.alpha_func,
537 LLVMBuildLoad(gallivm->builder, out_ptr, ""),
538 lp_build_const_float(gallivm, si_shader_ctx->shader->key.ps.alpha_ref));
539 LLVMValueRef arg =
540 lp_build_select(&bld_base->base,
541 alpha_pass,
542 lp_build_const_float(gallivm, 1.0f),
543 lp_build_const_float(gallivm, -1.0f));
544
545 build_intrinsic(gallivm->builder,
546 "llvm.AMDGPU.kill",
547 LLVMVoidTypeInContext(gallivm->context),
548 &arg, 1, 0);
549 } else {
550 build_intrinsic(gallivm->builder,
551 "llvm.AMDGPU.kilp",
552 LLVMVoidTypeInContext(gallivm->context),
553 NULL, 0, 0);
554 }
555 }
556
557 /* XXX: This is partially implemented for VS only at this point. It is not complete */
558 static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
559 {
560 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
561 struct si_shader * shader = &si_shader_ctx->shader->shader;
562 struct lp_build_context * base = &bld_base->base;
563 struct lp_build_context * uint =
564 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
565 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
566 LLVMValueRef args[9];
567 LLVMValueRef last_args[9] = { 0 };
568 unsigned color_count = 0;
569 unsigned param_count = 0;
570 int depth_index = -1, stencil_index = -1;
571
572 while (!tgsi_parse_end_of_tokens(parse)) {
573 struct tgsi_full_declaration *d =
574 &parse->FullToken.FullDeclaration;
575 unsigned target;
576 unsigned index;
577 int i;
578
579 tgsi_parse_token(parse);
580
581 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
582 parse->FullToken.FullProperty.Property.PropertyName ==
583 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
584 shader->fs_write_all = TRUE;
585
586 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
587 continue;
588
589 switch (d->Declaration.File) {
590 case TGSI_FILE_INPUT:
591 i = shader->ninput++;
592 shader->input[i].name = d->Semantic.Name;
593 shader->input[i].sid = d->Semantic.Index;
594 shader->input[i].interpolate = d->Interp.Interpolate;
595 shader->input[i].centroid = d->Interp.Centroid;
596 continue;
597
598 case TGSI_FILE_OUTPUT:
599 i = shader->noutput++;
600 shader->output[i].name = d->Semantic.Name;
601 shader->output[i].sid = d->Semantic.Index;
602 shader->output[i].interpolate = d->Interp.Interpolate;
603 break;
604
605 default:
606 continue;
607 }
608
609 for (index = d->Range.First; index <= d->Range.Last; index++) {
610 /* Select the correct target */
611 switch(d->Semantic.Name) {
612 case TGSI_SEMANTIC_PSIZE:
613 target = V_008DFC_SQ_EXP_POS;
614 break;
615 case TGSI_SEMANTIC_POSITION:
616 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
617 target = V_008DFC_SQ_EXP_POS;
618 break;
619 } else {
620 depth_index = index;
621 continue;
622 }
623 case TGSI_SEMANTIC_STENCIL:
624 stencil_index = index;
625 continue;
626 case TGSI_SEMANTIC_COLOR:
627 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
628 case TGSI_SEMANTIC_BCOLOR:
629 target = V_008DFC_SQ_EXP_PARAM + param_count;
630 shader->output[i].param_offset = param_count;
631 param_count++;
632 } else {
633 target = V_008DFC_SQ_EXP_MRT + color_count;
634 if (color_count == 0 &&
635 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
636 si_alpha_test(bld_base, index);
637
638 color_count++;
639 }
640 break;
641 case TGSI_SEMANTIC_FOG:
642 case TGSI_SEMANTIC_GENERIC:
643 target = V_008DFC_SQ_EXP_PARAM + param_count;
644 shader->output[i].param_offset = param_count;
645 param_count++;
646 break;
647 default:
648 target = 0;
649 fprintf(stderr,
650 "Warning: SI unhandled output type:%d\n",
651 d->Semantic.Name);
652 }
653
654 si_llvm_init_export_args(bld_base, d, index, target, args);
655
656 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX ?
657 (d->Semantic.Name == TGSI_SEMANTIC_POSITION) :
658 (d->Semantic.Name == TGSI_SEMANTIC_COLOR)) {
659 if (last_args[0]) {
660 lp_build_intrinsic(base->gallivm->builder,
661 "llvm.SI.export",
662 LLVMVoidTypeInContext(base->gallivm->context),
663 last_args, 9);
664 }
665
666 memcpy(last_args, args, sizeof(args));
667 } else {
668 lp_build_intrinsic(base->gallivm->builder,
669 "llvm.SI.export",
670 LLVMVoidTypeInContext(base->gallivm->context),
671 args, 9);
672 }
673
674 }
675 }
676
677 if (depth_index >= 0 || stencil_index >= 0) {
678 LLVMValueRef out_ptr;
679 unsigned mask = 0;
680
681 /* Specify the target we are exporting */
682 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
683
684 if (depth_index >= 0) {
685 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
686 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
687 mask |= 0x1;
688
689 if (stencil_index < 0) {
690 args[6] =
691 args[7] =
692 args[8] = args[5];
693 }
694 }
695
696 if (stencil_index >= 0) {
697 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
698 args[7] =
699 args[8] =
700 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
701 mask |= 0x2;
702
703 if (depth_index < 0)
704 args[5] = args[6];
705 }
706
707 /* Specify which components to enable */
708 args[0] = lp_build_const_int32(base->gallivm, mask);
709
710 args[1] =
711 args[2] =
712 args[4] = uint->zero;
713
714 if (last_args[0])
715 lp_build_intrinsic(base->gallivm->builder,
716 "llvm.SI.export",
717 LLVMVoidTypeInContext(base->gallivm->context),
718 args, 9);
719 else
720 memcpy(last_args, args, sizeof(args));
721 }
722
723 if (!last_args[0]) {
724 assert(si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
725
726 /* Specify which components to enable */
727 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
728
729 /* Specify the target we are exporting */
730 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
731
732 /* Set COMPR flag to zero to export data as 32-bit */
733 last_args[4] = uint->zero;
734
735 /* dummy bits */
736 last_args[5]= uint->zero;
737 last_args[6]= uint->zero;
738 last_args[7]= uint->zero;
739 last_args[8]= uint->zero;
740
741 si_shader_ctx->shader->spi_shader_col_format |=
742 V_028714_SPI_SHADER_32_ABGR;
743 }
744
745 /* Specify whether the EXEC mask represents the valid mask */
746 last_args[1] = lp_build_const_int32(base->gallivm,
747 si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT);
748
749 if (shader->fs_write_all && shader->nr_cbufs > 1) {
750 int i;
751
752 /* Specify that this is not yet the last export */
753 last_args[2] = lp_build_const_int32(base->gallivm, 0);
754
755 for (i = 1; i < shader->nr_cbufs; i++) {
756 /* Specify the target we are exporting */
757 last_args[3] = lp_build_const_int32(base->gallivm,
758 V_008DFC_SQ_EXP_MRT + i);
759
760 lp_build_intrinsic(base->gallivm->builder,
761 "llvm.SI.export",
762 LLVMVoidTypeInContext(base->gallivm->context),
763 last_args, 9);
764
765 si_shader_ctx->shader->spi_shader_col_format |=
766 si_shader_ctx->shader->spi_shader_col_format << 4;
767 }
768
769 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
770 }
771
772 /* Specify that this is the last export */
773 last_args[2] = lp_build_const_int32(base->gallivm, 1);
774
775 lp_build_intrinsic(base->gallivm->builder,
776 "llvm.SI.export",
777 LLVMVoidTypeInContext(base->gallivm->context),
778 last_args, 9);
779
780 /* XXX: Look up what this function does */
781 /* ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
782 }
783
784 static void tex_fetch_args(
785 struct lp_build_tgsi_context * bld_base,
786 struct lp_build_emit_data * emit_data)
787 {
788 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
789 struct gallivm_state *gallivm = bld_base->base.gallivm;
790 const struct tgsi_full_instruction * inst = emit_data->inst;
791 unsigned opcode = inst->Instruction.Opcode;
792 unsigned target = inst->Texture.Texture;
793 LLVMValueRef coords[4];
794 LLVMValueRef address[16];
795 unsigned count = 0;
796 unsigned chan;
797
798 /* Fetch and project texture coordinates */
799 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
800 for (chan = 0; chan < 3; chan++ ) {
801 coords[chan] = lp_build_emit_fetch(bld_base,
802 emit_data->inst, 0,
803 chan);
804 if (opcode == TGSI_OPCODE_TXP)
805 coords[chan] = lp_build_emit_llvm_binary(bld_base,
806 TGSI_OPCODE_DIV,
807 coords[chan],
808 coords[3]);
809 }
810
811 if (opcode == TGSI_OPCODE_TXP)
812 coords[3] = bld_base->base.one;
813
814 /* Pack LOD bias value */
815 if (opcode == TGSI_OPCODE_TXB)
816 address[count++] = coords[3];
817
818 if ((target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE) &&
819 opcode != TGSI_OPCODE_TXQ)
820 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
821
822 /* Pack depth comparison value */
823 switch (target) {
824 case TGSI_TEXTURE_SHADOW1D:
825 case TGSI_TEXTURE_SHADOW1D_ARRAY:
826 case TGSI_TEXTURE_SHADOW2D:
827 case TGSI_TEXTURE_SHADOWRECT:
828 address[count++] = coords[2];
829 break;
830 case TGSI_TEXTURE_SHADOWCUBE:
831 case TGSI_TEXTURE_SHADOW2D_ARRAY:
832 address[count++] = coords[3];
833 break;
834 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
835 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
836 }
837
838 /* Pack texture coordinates */
839 address[count++] = coords[0];
840 switch (target) {
841 case TGSI_TEXTURE_2D:
842 case TGSI_TEXTURE_2D_ARRAY:
843 case TGSI_TEXTURE_3D:
844 case TGSI_TEXTURE_CUBE:
845 case TGSI_TEXTURE_RECT:
846 case TGSI_TEXTURE_SHADOW2D:
847 case TGSI_TEXTURE_SHADOWRECT:
848 case TGSI_TEXTURE_SHADOW2D_ARRAY:
849 case TGSI_TEXTURE_SHADOWCUBE:
850 case TGSI_TEXTURE_2D_MSAA:
851 case TGSI_TEXTURE_2D_ARRAY_MSAA:
852 case TGSI_TEXTURE_CUBE_ARRAY:
853 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
854 address[count++] = coords[1];
855 }
856 switch (target) {
857 case TGSI_TEXTURE_3D:
858 case TGSI_TEXTURE_CUBE:
859 case TGSI_TEXTURE_SHADOWCUBE:
860 case TGSI_TEXTURE_CUBE_ARRAY:
861 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
862 address[count++] = coords[2];
863 }
864
865 /* Pack array slice */
866 switch (target) {
867 case TGSI_TEXTURE_1D_ARRAY:
868 address[count++] = coords[1];
869 }
870 switch (target) {
871 case TGSI_TEXTURE_2D_ARRAY:
872 case TGSI_TEXTURE_2D_ARRAY_MSAA:
873 case TGSI_TEXTURE_SHADOW2D_ARRAY:
874 address[count++] = coords[2];
875 }
876 switch (target) {
877 case TGSI_TEXTURE_CUBE_ARRAY:
878 case TGSI_TEXTURE_SHADOW1D_ARRAY:
879 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
880 address[count++] = coords[3];
881 }
882
883 /* Pack LOD */
884 if (opcode == TGSI_OPCODE_TXL)
885 address[count++] = coords[3];
886
887 if (count > 16) {
888 assert(!"Cannot handle more than 16 texture address parameters");
889 count = 16;
890 }
891
892 for (chan = 0; chan < count; chan++ ) {
893 address[chan] = LLVMBuildBitCast(gallivm->builder,
894 address[chan],
895 LLVMInt32TypeInContext(gallivm->context),
896 "");
897 }
898
899 /* Pad to power of two vector */
900 while (count < util_next_power_of_two(count))
901 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
902
903 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
904
905 /* Resource */
906 emit_data->args[1] = si_shader_ctx->resources[emit_data->inst->Src[1].Register.Index];
907
908 /* Sampler */
909 emit_data->args[2] = si_shader_ctx->samplers[emit_data->inst->Src[1].Register.Index];
910
911 /* Dimensions */
912 emit_data->args[3] = lp_build_const_int32(bld_base->base.gallivm, target);
913
914 emit_data->arg_count = 4;
915
916 emit_data->dst_type = LLVMVectorType(
917 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
918 4);
919 }
920
921 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
922 struct lp_build_tgsi_context * bld_base,
923 struct lp_build_emit_data * emit_data)
924 {
925 struct lp_build_context * base = &bld_base->base;
926 char intr_name[23];
927
928 sprintf(intr_name, "%sv%ui32", action->intr_name,
929 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
930
931 emit_data->output[emit_data->chan] = build_intrinsic(
932 base->gallivm->builder, intr_name, emit_data->dst_type,
933 emit_data->args, emit_data->arg_count,
934 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
935 }
936
937 static const struct lp_build_tgsi_action tex_action = {
938 .fetch_args = tex_fetch_args,
939 .emit = build_tex_intrinsic,
940 .intr_name = "llvm.SI.sample."
941 };
942
943 static const struct lp_build_tgsi_action txb_action = {
944 .fetch_args = tex_fetch_args,
945 .emit = build_tex_intrinsic,
946 .intr_name = "llvm.SI.sampleb."
947 };
948
949 static const struct lp_build_tgsi_action txl_action = {
950 .fetch_args = tex_fetch_args,
951 .emit = build_tex_intrinsic,
952 .intr_name = "llvm.SI.samplel."
953 };
954
955 static void create_meta_data(struct si_shader_context *si_shader_ctx)
956 {
957 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
958 LLVMValueRef args[3];
959
960 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
961 args[1] = 0;
962 args[2] = lp_build_const_int32(gallivm, 1);
963
964 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
965 }
966
967 static void create_function(struct si_shader_context *si_shader_ctx)
968 {
969 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
970 LLVMTypeRef params[20], f32, i8, i32, v2i32, v3i32;
971 unsigned i;
972
973 i8 = LLVMInt8TypeInContext(gallivm->context);
974 i32 = LLVMInt32TypeInContext(gallivm->context);
975 f32 = LLVMFloatTypeInContext(gallivm->context);
976 v2i32 = LLVMVectorType(i32, 2);
977 v3i32 = LLVMVectorType(i32, 3);
978
979 params[SI_PARAM_CONST] = LLVMPointerType(LLVMVectorType(i8, 16), CONST_ADDR_SPACE);
980 params[SI_PARAM_SAMPLER] = params[SI_PARAM_CONST];
981 params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), CONST_ADDR_SPACE);
982
983 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
984 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
985 params[SI_PARAM_START_INSTANCE] = i32;
986 params[SI_PARAM_VERTEX_ID] = i32;
987 params[SI_PARAM_DUMMY_0] = i32;
988 params[SI_PARAM_DUMMY_1] = i32;
989 params[SI_PARAM_INSTANCE_ID] = i32;
990 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 9);
991
992 } else {
993 params[SI_PARAM_PRIM_MASK] = i32;
994 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
995 params[SI_PARAM_PERSP_CENTER] = v2i32;
996 params[SI_PARAM_PERSP_CENTROID] = v2i32;
997 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
998 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
999 params[SI_PARAM_LINEAR_CENTER] = v2i32;
1000 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
1001 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
1002 params[SI_PARAM_POS_X_FLOAT] = f32;
1003 params[SI_PARAM_POS_Y_FLOAT] = f32;
1004 params[SI_PARAM_POS_Z_FLOAT] = f32;
1005 params[SI_PARAM_POS_W_FLOAT] = f32;
1006 params[SI_PARAM_FRONT_FACE] = f32;
1007 params[SI_PARAM_ANCILLARY] = f32;
1008 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
1009 params[SI_PARAM_POS_FIXED_PT] = f32;
1010 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 20);
1011 }
1012
1013 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
1014 for (i = SI_PARAM_CONST; i <= SI_PARAM_VERTEX_BUFFER; ++i) {
1015 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
1016 LLVMAddAttribute(P, LLVMInRegAttribute);
1017 }
1018
1019 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
1020 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1021 SI_PARAM_START_INSTANCE);
1022 LLVMAddAttribute(P, LLVMInRegAttribute);
1023 }
1024 }
1025
1026 static void preload_constants(struct si_shader_context *si_shader_ctx)
1027 {
1028 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1029 struct gallivm_state * gallivm = bld_base->base.gallivm;
1030 const struct tgsi_shader_info * info = bld_base->info;
1031
1032 unsigned i, num_const = info->file_max[TGSI_FILE_CONSTANT] + 1;
1033
1034 LLVMValueRef ptr;
1035
1036 if (num_const == 0)
1037 return;
1038
1039 /* Allocate space for the constant values */
1040 si_shader_ctx->constants = CALLOC(num_const * 4, sizeof(LLVMValueRef));
1041
1042 /* Load the resource descriptor */
1043 ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1044 si_shader_ctx->const_resource = build_indexed_load(si_shader_ctx, ptr, bld_base->uint_bld.zero);
1045
1046 /* Load the constants, we rely on the code sinking to do the rest */
1047 for (i = 0; i < num_const * 4; ++i) {
1048 LLVMValueRef args[2] = {
1049 si_shader_ctx->const_resource,
1050 lp_build_const_int32(gallivm, i * 4)
1051 };
1052 si_shader_ctx->constants[i] = build_intrinsic(gallivm->builder, "llvm.SI.load.const",
1053 bld_base->base.elem_type, args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1054 }
1055 }
1056
1057 static void preload_samplers(struct si_shader_context *si_shader_ctx)
1058 {
1059 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
1060 struct gallivm_state * gallivm = bld_base->base.gallivm;
1061 const struct tgsi_shader_info * info = bld_base->info;
1062
1063 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
1064
1065 LLVMValueRef res_ptr, samp_ptr;
1066 LLVMValueRef offset;
1067
1068 if (num_samplers == 0)
1069 return;
1070
1071 /* Allocate space for the values */
1072 si_shader_ctx->resources = CALLOC(num_samplers, sizeof(LLVMValueRef));
1073 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
1074
1075 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
1076 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
1077
1078 /* Load the resources and samplers, we rely on the code sinking to do the rest */
1079 for (i = 0; i < num_samplers; ++i) {
1080
1081 /* Resource */
1082 offset = lp_build_const_int32(gallivm, i);
1083 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
1084
1085 /* Sampler */
1086 offset = lp_build_const_int32(gallivm, i);
1087 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
1088 }
1089 }
1090
1091 int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader,
1092 LLVMModuleRef mod)
1093 {
1094 unsigned i;
1095 uint32_t *ptr;
1096 bool dump;
1097 struct radeon_llvm_binary binary;
1098
1099 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
1100
1101 memset(&binary, 0, sizeof(binary));
1102 radeon_llvm_compile(mod, &binary,
1103 r600_get_llvm_processor_name(rctx->screen->family), dump);
1104 if (dump) {
1105 fprintf(stderr, "SI CODE:\n");
1106 for (i = 0; i < binary.code_size; i+=4 ) {
1107 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
1108 binary.code[i + 2], binary.code[i + 1],
1109 binary.code[i]);
1110 }
1111 }
1112
1113 /* XXX: We may be able to emit some of these values directly rather than
1114 * extracting fields to be emitted later.
1115 */
1116 for (i = 0; i < binary.config_size; i+= 8) {
1117 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
1118 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
1119 switch (reg) {
1120 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
1121 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
1122 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
1123 case R_00B848_COMPUTE_PGM_RSRC1:
1124 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
1125 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
1126 break;
1127 case R_0286CC_SPI_PS_INPUT_ENA:
1128 shader->spi_ps_input_ena = value;
1129 break;
1130 default:
1131 fprintf(stderr, "Warning: Compiler emitted unknown "
1132 "config register: 0x%x\n", reg);
1133 break;
1134 }
1135 }
1136
1137 /* copy new shader */
1138 si_resource_reference(&shader->bo, NULL);
1139 shader->bo = si_resource_create_custom(rctx->context.screen, PIPE_USAGE_IMMUTABLE,
1140 binary.code_size);
1141 if (shader->bo == NULL) {
1142 return -ENOMEM;
1143 }
1144
1145 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1146 if (0 /*R600_BIG_ENDIAN*/) {
1147 for (i = 0; i < binary.code_size / 4; ++i) {
1148 ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
1149 }
1150 } else {
1151 memcpy(ptr, binary.code, binary.code_size);
1152 }
1153 rctx->ws->buffer_unmap(shader->bo->cs_buf);
1154
1155 free(binary.code);
1156 free(binary.config);
1157
1158 return 0;
1159 }
1160
1161 int si_pipe_shader_create(
1162 struct pipe_context *ctx,
1163 struct si_pipe_shader *shader)
1164 {
1165 struct r600_context *rctx = (struct r600_context*)ctx;
1166 struct si_pipe_shader_selector *sel = shader->selector;
1167 struct si_shader_context si_shader_ctx;
1168 struct tgsi_shader_info shader_info;
1169 struct lp_build_tgsi_context * bld_base;
1170 LLVMModuleRef mod;
1171 bool dump;
1172 int r = 0;
1173
1174 dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
1175
1176 assert(shader->shader.noutput == 0);
1177 assert(shader->shader.ninterp == 0);
1178 assert(shader->shader.ninput == 0);
1179
1180 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
1181 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
1182 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
1183
1184 tgsi_scan_shader(sel->tokens, &shader_info);
1185 shader->shader.uses_kill = shader_info.uses_kill;
1186 shader->shader.uses_instanceid = shader_info.uses_instanceid;
1187 bld_base->info = &shader_info;
1188 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
1189 bld_base->emit_epilogue = si_llvm_emit_epilogue;
1190
1191 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1192 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
1193 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
1194 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
1195
1196 si_shader_ctx.radeon_bld.load_input = declare_input;
1197 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
1198 si_shader_ctx.tokens = sel->tokens;
1199 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
1200 si_shader_ctx.shader = shader;
1201 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
1202
1203 create_meta_data(&si_shader_ctx);
1204 create_function(&si_shader_ctx);
1205 preload_constants(&si_shader_ctx);
1206 preload_samplers(&si_shader_ctx);
1207
1208 shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
1209
1210 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
1211 * conversion fails. */
1212 if (dump) {
1213 tgsi_dump(sel->tokens, 0);
1214 }
1215
1216 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
1217 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
1218 FREE(si_shader_ctx.constants);
1219 FREE(si_shader_ctx.resources);
1220 FREE(si_shader_ctx.samplers);
1221 return -EINVAL;
1222 }
1223
1224 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
1225
1226 mod = bld_base->base.gallivm->module;
1227 r = si_compile_llvm(rctx, shader, mod);
1228
1229 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
1230 tgsi_parse_free(&si_shader_ctx.parse);
1231
1232 FREE(si_shader_ctx.constants);
1233 FREE(si_shader_ctx.resources);
1234 FREE(si_shader_ctx.samplers);
1235
1236 return r;
1237 }
1238
1239 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
1240 {
1241 si_resource_reference(&shader->bo, NULL);
1242 }