2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "util/u_format.h"
27 #include "util/u_surface.h"
29 enum si_blitter_op
/* bitmask */
32 SI_SAVE_FRAMEBUFFER
= 2,
33 SI_SAVE_FRAGMENT_STATE
= 4,
34 SI_DISABLE_RENDER_COND
= 8,
36 SI_CLEAR
= SI_SAVE_FRAGMENT_STATE
,
38 SI_CLEAR_SURFACE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
,
40 SI_COPY
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
41 SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
43 SI_BLIT
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
44 SI_SAVE_FRAGMENT_STATE
,
46 SI_DECOMPRESS
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
|
47 SI_DISABLE_RENDER_COND
,
49 SI_COLOR_RESOLVE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
52 static void si_blitter_begin(struct pipe_context
*ctx
, enum si_blitter_op op
)
54 struct si_context
*sctx
= (struct si_context
*)ctx
;
56 util_blitter_save_vertex_buffer_slot(sctx
->blitter
, sctx
->vertex_buffer
);
57 util_blitter_save_vertex_elements(sctx
->blitter
, sctx
->vertex_elements
);
58 util_blitter_save_vertex_shader(sctx
->blitter
, sctx
->vs_shader
.cso
);
59 util_blitter_save_tessctrl_shader(sctx
->blitter
, sctx
->tcs_shader
.cso
);
60 util_blitter_save_tesseval_shader(sctx
->blitter
, sctx
->tes_shader
.cso
);
61 util_blitter_save_geometry_shader(sctx
->blitter
, sctx
->gs_shader
.cso
);
62 util_blitter_save_so_targets(sctx
->blitter
, sctx
->b
.streamout
.num_targets
,
63 (struct pipe_stream_output_target
**)sctx
->b
.streamout
.targets
);
64 util_blitter_save_rasterizer(sctx
->blitter
, sctx
->queued
.named
.rasterizer
);
66 if (op
& SI_SAVE_FRAGMENT_STATE
) {
67 util_blitter_save_blend(sctx
->blitter
, sctx
->queued
.named
.blend
);
68 util_blitter_save_depth_stencil_alpha(sctx
->blitter
, sctx
->queued
.named
.dsa
);
69 util_blitter_save_stencil_ref(sctx
->blitter
, &sctx
->stencil_ref
.state
);
70 util_blitter_save_fragment_shader(sctx
->blitter
, sctx
->ps_shader
.cso
);
71 util_blitter_save_sample_mask(sctx
->blitter
, sctx
->sample_mask
.sample_mask
);
72 util_blitter_save_viewport(sctx
->blitter
, &sctx
->b
.viewports
.states
[0]);
73 util_blitter_save_scissor(sctx
->blitter
, &sctx
->b
.scissors
.states
[0]);
76 if (op
& SI_SAVE_FRAMEBUFFER
)
77 util_blitter_save_framebuffer(sctx
->blitter
, &sctx
->framebuffer
.state
);
79 if (op
& SI_SAVE_TEXTURES
) {
80 util_blitter_save_fragment_sampler_states(
82 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.sampler_states
);
84 util_blitter_save_fragment_sampler_views(sctx
->blitter
, 2,
85 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.views
);
88 if (op
& SI_DISABLE_RENDER_COND
)
89 sctx
->b
.render_cond_force_off
= true;
92 static void si_blitter_end(struct pipe_context
*ctx
)
94 struct si_context
*sctx
= (struct si_context
*)ctx
;
96 sctx
->b
.render_cond_force_off
= false;
99 static unsigned u_max_sample(struct pipe_resource
*r
)
101 return r
->nr_samples
? r
->nr_samples
- 1 : 0;
105 si_blit_dbcb_copy(struct si_context
*sctx
,
106 struct r600_texture
*src
,
107 struct r600_texture
*dst
,
108 unsigned planes
, unsigned level_mask
,
109 unsigned first_layer
, unsigned last_layer
,
110 unsigned first_sample
, unsigned last_sample
)
112 struct pipe_surface surf_tmpl
= {{0}};
113 unsigned layer
, sample
, checked_last_layer
, max_layer
;
114 unsigned fully_copied_levels
= 0;
116 if (planes
& PIPE_MASK_Z
)
117 sctx
->dbcb_depth_copy_enabled
= true;
118 if (planes
& PIPE_MASK_S
)
119 sctx
->dbcb_stencil_copy_enabled
= true;
120 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
122 assert(sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
);
125 unsigned level
= u_bit_scan(&level_mask
);
127 /* The smaller the mipmap level, the less layers there are
128 * as far as 3D textures are concerned. */
129 max_layer
= util_max_layer(&src
->resource
.b
.b
, level
);
130 checked_last_layer
= MIN2(last_layer
, max_layer
);
132 surf_tmpl
.u
.tex
.level
= level
;
134 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
135 struct pipe_surface
*zsurf
, *cbsurf
;
137 surf_tmpl
.format
= src
->resource
.b
.b
.format
;
138 surf_tmpl
.u
.tex
.first_layer
= layer
;
139 surf_tmpl
.u
.tex
.last_layer
= layer
;
141 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &src
->resource
.b
.b
, &surf_tmpl
);
143 surf_tmpl
.format
= dst
->resource
.b
.b
.format
;
144 cbsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &dst
->resource
.b
.b
, &surf_tmpl
);
146 for (sample
= first_sample
; sample
<= last_sample
; sample
++) {
147 if (sample
!= sctx
->dbcb_copy_sample
) {
148 sctx
->dbcb_copy_sample
= sample
;
149 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
152 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
153 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, cbsurf
, 1 << sample
,
154 sctx
->custom_dsa_flush
, 1.0f
);
155 si_blitter_end(&sctx
->b
.b
);
158 pipe_surface_reference(&zsurf
, NULL
);
159 pipe_surface_reference(&cbsurf
, NULL
);
162 if (first_layer
== 0 && last_layer
>= max_layer
&&
163 first_sample
== 0 && last_sample
>= u_max_sample(&src
->resource
.b
.b
))
164 fully_copied_levels
|= 1u << level
;
167 sctx
->dbcb_depth_copy_enabled
= false;
168 sctx
->dbcb_stencil_copy_enabled
= false;
169 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
171 return fully_copied_levels
;
174 static void si_blit_decompress_depth(struct pipe_context
*ctx
,
175 struct r600_texture
*texture
,
176 struct r600_texture
*staging
,
177 unsigned first_level
, unsigned last_level
,
178 unsigned first_layer
, unsigned last_layer
,
179 unsigned first_sample
, unsigned last_sample
)
181 const struct util_format_description
*desc
;
184 assert(staging
!= NULL
&& "use si_blit_decompress_zs_in_place instead");
186 desc
= util_format_description(staging
->resource
.b
.b
.format
);
188 if (util_format_has_depth(desc
))
189 planes
|= PIPE_MASK_Z
;
190 if (util_format_has_stencil(desc
))
191 planes
|= PIPE_MASK_S
;
194 (struct si_context
*)ctx
, texture
, staging
, planes
,
195 u_bit_consecutive(first_level
, last_level
- first_level
+ 1),
196 first_layer
, last_layer
, first_sample
, last_sample
);
199 /* Helper function for si_blit_decompress_zs_in_place.
202 si_blit_decompress_zs_planes_in_place(struct si_context
*sctx
,
203 struct r600_texture
*texture
,
204 unsigned planes
, unsigned level_mask
,
205 unsigned first_layer
, unsigned last_layer
)
207 struct pipe_surface
*zsurf
, surf_tmpl
= {{0}};
208 unsigned layer
, max_layer
, checked_last_layer
;
209 unsigned fully_decompressed_mask
= 0;
214 if (planes
& PIPE_MASK_S
)
215 sctx
->db_flush_stencil_inplace
= true;
216 if (planes
& PIPE_MASK_Z
)
217 sctx
->db_flush_depth_inplace
= true;
218 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
220 surf_tmpl
.format
= texture
->resource
.b
.b
.format
;
223 unsigned level
= u_bit_scan(&level_mask
);
225 surf_tmpl
.u
.tex
.level
= level
;
227 /* The smaller the mipmap level, the less layers there are
228 * as far as 3D textures are concerned. */
229 max_layer
= util_max_layer(&texture
->resource
.b
.b
, level
);
230 checked_last_layer
= MIN2(last_layer
, max_layer
);
232 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
233 surf_tmpl
.u
.tex
.first_layer
= layer
;
234 surf_tmpl
.u
.tex
.last_layer
= layer
;
236 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &texture
->resource
.b
.b
, &surf_tmpl
);
238 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
239 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, NULL
, ~0,
240 sctx
->custom_dsa_flush
,
242 si_blitter_end(&sctx
->b
.b
);
244 pipe_surface_reference(&zsurf
, NULL
);
247 /* The texture will always be dirty if some layers aren't flushed.
248 * I don't think this case occurs often though. */
249 if (first_layer
== 0 && last_layer
>= max_layer
) {
250 fully_decompressed_mask
|= 1u << level
;
254 if (planes
& PIPE_MASK_Z
)
255 texture
->dirty_level_mask
&= ~fully_decompressed_mask
;
256 if (planes
& PIPE_MASK_S
)
257 texture
->stencil_dirty_level_mask
&= ~fully_decompressed_mask
;
259 sctx
->db_flush_depth_inplace
= false;
260 sctx
->db_flush_stencil_inplace
= false;
261 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
264 /* Helper function of si_flush_depth_texture: decompress the given levels
265 * of Z and/or S planes in place.
268 si_blit_decompress_zs_in_place(struct si_context
*sctx
,
269 struct r600_texture
*texture
,
270 unsigned levels_z
, unsigned levels_s
,
271 unsigned first_layer
, unsigned last_layer
)
273 unsigned both
= levels_z
& levels_s
;
275 /* First, do combined Z & S decompresses for levels that need it. */
277 si_blit_decompress_zs_planes_in_place(
278 sctx
, texture
, PIPE_MASK_Z
| PIPE_MASK_S
,
280 first_layer
, last_layer
);
285 /* Now do separate Z and S decompresses. */
287 si_blit_decompress_zs_planes_in_place(
288 sctx
, texture
, PIPE_MASK_Z
,
290 first_layer
, last_layer
);
294 si_blit_decompress_zs_planes_in_place(
295 sctx
, texture
, PIPE_MASK_S
,
297 first_layer
, last_layer
);
302 si_flush_depth_texture(struct si_context
*sctx
,
303 struct r600_texture
*tex
,
304 unsigned required_planes
,
305 unsigned first_level
, unsigned last_level
,
306 unsigned first_layer
, unsigned last_layer
)
308 unsigned inplace_planes
= 0;
309 unsigned copy_planes
= 0;
310 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
311 unsigned levels_z
= 0;
312 unsigned levels_s
= 0;
314 if (required_planes
& PIPE_MASK_Z
) {
315 levels_z
= level_mask
& tex
->dirty_level_mask
;
318 if (r600_can_sample_zs(tex
, false))
319 inplace_planes
|= PIPE_MASK_Z
;
321 copy_planes
|= PIPE_MASK_Z
;
324 if (required_planes
& PIPE_MASK_S
) {
325 levels_s
= level_mask
& tex
->stencil_dirty_level_mask
;
328 if (r600_can_sample_zs(tex
, true))
329 inplace_planes
|= PIPE_MASK_S
;
331 copy_planes
|= PIPE_MASK_S
;
335 /* We may have to allocate the flushed texture here when called from
336 * si_decompress_subresource.
339 (tex
->flushed_depth_texture
||
340 r600_init_flushed_depth_texture(&sctx
->b
.b
, &tex
->resource
.b
.b
, NULL
))) {
341 struct r600_texture
*dst
= tex
->flushed_depth_texture
;
342 unsigned fully_copied_levels
;
345 assert(tex
->flushed_depth_texture
);
347 if (util_format_is_depth_and_stencil(dst
->resource
.b
.b
.format
))
348 copy_planes
= PIPE_MASK_Z
| PIPE_MASK_S
;
350 if (copy_planes
& PIPE_MASK_Z
) {
354 if (copy_planes
& PIPE_MASK_S
) {
359 fully_copied_levels
= si_blit_dbcb_copy(
360 sctx
, tex
, dst
, copy_planes
, levels
,
361 first_layer
, last_layer
,
362 0, u_max_sample(&tex
->resource
.b
.b
));
364 if (copy_planes
& PIPE_MASK_Z
)
365 tex
->dirty_level_mask
&= ~fully_copied_levels
;
366 if (copy_planes
& PIPE_MASK_S
)
367 tex
->stencil_dirty_level_mask
&= ~fully_copied_levels
;
370 if (inplace_planes
) {
371 si_blit_decompress_zs_in_place(
374 first_layer
, last_layer
);
379 si_flush_depth_textures(struct si_context
*sctx
,
380 struct si_textures_info
*textures
)
383 unsigned mask
= textures
->depth_texture_mask
;
386 struct pipe_sampler_view
*view
;
387 struct si_sampler_view
*sview
;
388 struct r600_texture
*tex
;
390 i
= u_bit_scan(&mask
);
392 view
= textures
->views
.views
[i
];
394 sview
= (struct si_sampler_view
*)view
;
396 tex
= (struct r600_texture
*)view
->texture
;
397 assert(tex
->db_compatible
);
399 si_flush_depth_texture(
401 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
402 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
403 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
407 static void si_blit_decompress_color(struct pipe_context
*ctx
,
408 struct r600_texture
*rtex
,
409 unsigned first_level
, unsigned last_level
,
410 unsigned first_layer
, unsigned last_layer
,
411 bool need_dcc_decompress
)
413 struct si_context
*sctx
= (struct si_context
*)ctx
;
415 unsigned layer
, checked_last_layer
, max_layer
;
416 unsigned level_mask
=
417 u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
419 if (!need_dcc_decompress
)
420 level_mask
&= rtex
->dirty_level_mask
;
424 if (rtex
->dcc_offset
&& need_dcc_decompress
) {
425 custom_blend
= sctx
->custom_blend_dcc_decompress
;
427 /* disable levels without DCC */
428 for (int i
= first_level
; i
<= last_level
; i
++) {
429 if (!rtex
->dcc_offset
||
430 !rtex
->surface
.level
[i
].dcc_enabled
)
431 level_mask
&= ~(1 << i
);
433 } else if (rtex
->fmask
.size
) {
434 custom_blend
= sctx
->custom_blend_decompress
;
436 custom_blend
= sctx
->custom_blend_fastclear
;
440 unsigned level
= u_bit_scan(&level_mask
);
442 /* The smaller the mipmap level, the less layers there are
443 * as far as 3D textures are concerned. */
444 max_layer
= util_max_layer(&rtex
->resource
.b
.b
, level
);
445 checked_last_layer
= MIN2(last_layer
, max_layer
);
447 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
448 struct pipe_surface
*cbsurf
, surf_tmpl
;
450 surf_tmpl
.format
= rtex
->resource
.b
.b
.format
;
451 surf_tmpl
.u
.tex
.level
= level
;
452 surf_tmpl
.u
.tex
.first_layer
= layer
;
453 surf_tmpl
.u
.tex
.last_layer
= layer
;
454 cbsurf
= ctx
->create_surface(ctx
, &rtex
->resource
.b
.b
, &surf_tmpl
);
456 si_blitter_begin(ctx
, SI_DECOMPRESS
);
457 util_blitter_custom_color(sctx
->blitter
, cbsurf
, custom_blend
);
460 pipe_surface_reference(&cbsurf
, NULL
);
463 /* The texture will always be dirty if some layers aren't flushed.
464 * I don't think this case occurs often though. */
465 if (first_layer
== 0 && last_layer
>= max_layer
) {
466 rtex
->dirty_level_mask
&= ~(1 << level
);
472 si_decompress_sampler_color_textures(struct si_context
*sctx
,
473 struct si_textures_info
*textures
)
476 unsigned mask
= textures
->compressed_colortex_mask
;
479 struct pipe_sampler_view
*view
;
480 struct r600_texture
*tex
;
482 i
= u_bit_scan(&mask
);
484 view
= textures
->views
.views
[i
];
487 tex
= (struct r600_texture
*)view
->texture
;
488 assert(tex
->cmask
.size
|| tex
->fmask
.size
|| tex
->dcc_offset
);
490 si_blit_decompress_color(&sctx
->b
.b
, tex
,
491 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
492 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
),
498 si_decompress_image_color_textures(struct si_context
*sctx
,
499 struct si_images_info
*images
)
502 unsigned mask
= images
->compressed_colortex_mask
;
505 const struct pipe_image_view
*view
;
506 struct r600_texture
*tex
;
508 i
= u_bit_scan(&mask
);
510 view
= &images
->views
[i
];
511 assert(view
->resource
->target
!= PIPE_BUFFER
);
513 tex
= (struct r600_texture
*)view
->resource
;
514 if (!tex
->cmask
.size
&& !tex
->fmask
.size
&& !tex
->dcc_offset
)
517 si_blit_decompress_color(&sctx
->b
.b
, tex
,
518 view
->u
.tex
.level
, view
->u
.tex
.level
,
519 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.level
),
524 static void si_check_render_feedback_textures(struct si_context
*sctx
,
525 struct si_textures_info
*textures
)
527 uint32_t mask
= textures
->views
.enabled_mask
;
530 const struct pipe_sampler_view
*view
;
531 struct r600_texture
*tex
;
532 bool render_feedback
= false;
534 unsigned i
= u_bit_scan(&mask
);
536 view
= textures
->views
.views
[i
];
537 if(view
->texture
->target
== PIPE_BUFFER
)
540 tex
= (struct r600_texture
*)view
->texture
;
541 if (!tex
->dcc_offset
)
544 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
545 struct r600_surface
* surf
;
547 if (!sctx
->framebuffer
.state
.cbufs
[j
])
550 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
552 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
553 surf
->base
.u
.tex
.level
>= view
->u
.tex
.first_level
&&
554 surf
->base
.u
.tex
.level
<= view
->u
.tex
.last_level
&&
555 surf
->base
.u
.tex
.first_layer
<= view
->u
.tex
.last_layer
&&
556 surf
->base
.u
.tex
.last_layer
>= view
->u
.tex
.first_layer
)
557 render_feedback
= true;
560 if (render_feedback
) {
561 struct si_screen
*screen
= sctx
->screen
;
562 r600_texture_disable_dcc(&screen
->b
, tex
);
567 static void si_check_render_feedback_images(struct si_context
*sctx
,
568 struct si_images_info
*images
)
570 uint32_t mask
= images
->enabled_mask
;
573 const struct pipe_image_view
*view
;
574 struct r600_texture
*tex
;
575 bool render_feedback
= false;
577 unsigned i
= u_bit_scan(&mask
);
579 view
= &images
->views
[i
];
580 if (view
->resource
->target
== PIPE_BUFFER
)
583 tex
= (struct r600_texture
*)view
->resource
;
584 if (!tex
->dcc_offset
)
587 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
588 struct r600_surface
* surf
;
590 if (!sctx
->framebuffer
.state
.cbufs
[j
])
593 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
595 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
596 surf
->base
.u
.tex
.level
== view
->u
.tex
.level
&&
597 surf
->base
.u
.tex
.first_layer
<= view
->u
.tex
.last_layer
&&
598 surf
->base
.u
.tex
.last_layer
>= view
->u
.tex
.first_layer
)
599 render_feedback
= true;
602 if (render_feedback
) {
603 struct si_screen
*screen
= sctx
->screen
;
604 r600_texture_disable_dcc(&screen
->b
, tex
);
609 static void si_check_render_feedback(struct si_context
*sctx
)
612 if (!sctx
->need_check_render_feedback
)
615 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
616 si_check_render_feedback_images(sctx
, &sctx
->images
[i
]);
617 si_check_render_feedback_textures(sctx
, &sctx
->samplers
[i
]);
619 sctx
->need_check_render_feedback
= false;
622 static void si_decompress_textures(struct si_context
*sctx
, int shader_start
,
625 unsigned compressed_colortex_counter
;
627 if (sctx
->blitter
->running
)
630 /* Update the compressed_colortex_mask if necessary. */
631 compressed_colortex_counter
= p_atomic_read(&sctx
->screen
->b
.compressed_colortex_counter
);
632 if (compressed_colortex_counter
!= sctx
->b
.last_compressed_colortex_counter
) {
633 sctx
->b
.last_compressed_colortex_counter
= compressed_colortex_counter
;
634 si_update_compressed_colortex_masks(sctx
);
637 /* Flush depth textures which need to be flushed. */
638 for (int i
= shader_start
; i
< shader_end
; i
++) {
639 if (sctx
->samplers
[i
].depth_texture_mask
) {
640 si_flush_depth_textures(sctx
, &sctx
->samplers
[i
]);
642 if (sctx
->samplers
[i
].compressed_colortex_mask
) {
643 si_decompress_sampler_color_textures(sctx
, &sctx
->samplers
[i
]);
645 if (sctx
->images
[i
].compressed_colortex_mask
) {
646 si_decompress_image_color_textures(sctx
, &sctx
->images
[i
]);
650 si_check_render_feedback(sctx
);
653 void si_decompress_graphics_textures(struct si_context
*sctx
)
655 si_decompress_textures(sctx
, 0, SI_NUM_GRAPHICS_SHADERS
);
658 void si_decompress_compute_textures(struct si_context
*sctx
)
660 si_decompress_textures(sctx
, SI_NUM_GRAPHICS_SHADERS
, SI_NUM_SHADERS
);
663 static void si_clear(struct pipe_context
*ctx
, unsigned buffers
,
664 const union pipe_color_union
*color
,
665 double depth
, unsigned stencil
)
667 struct si_context
*sctx
= (struct si_context
*)ctx
;
668 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
669 struct pipe_surface
*zsbuf
= fb
->zsbuf
;
670 struct r600_texture
*zstex
=
671 zsbuf
? (struct r600_texture
*)zsbuf
->texture
: NULL
;
673 if (buffers
& PIPE_CLEAR_COLOR
) {
674 evergreen_do_fast_color_clear(&sctx
->b
, fb
,
675 &sctx
->framebuffer
.atom
, &buffers
,
676 &sctx
->framebuffer
.dirty_cbufs
,
679 return; /* all buffers have been fast cleared */
682 if (buffers
& PIPE_CLEAR_COLOR
) {
685 /* These buffers cannot use fast clear, make sure to disable expansion. */
686 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
687 struct r600_texture
*tex
;
689 /* If not clearing this buffer, skip. */
690 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
696 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
697 if (tex
->fmask
.size
== 0)
698 tex
->dirty_level_mask
&= ~(1 << fb
->cbufs
[i
]->u
.tex
.level
);
702 if (zstex
&& zstex
->htile_buffer
&&
703 zsbuf
->u
.tex
.level
== 0 &&
704 zsbuf
->u
.tex
.first_layer
== 0 &&
705 zsbuf
->u
.tex
.last_layer
== util_max_layer(&zstex
->resource
.b
.b
, 0)) {
706 if (buffers
& PIPE_CLEAR_DEPTH
) {
707 /* Need to disable EXPCLEAR temporarily if clearing
709 if (!zstex
->depth_cleared
|| zstex
->depth_clear_value
!= depth
) {
710 sctx
->db_depth_disable_expclear
= true;
713 zstex
->depth_clear_value
= depth
;
714 sctx
->framebuffer
.dirty_zsbuf
= true;
715 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_DEPTH_CLEAR */
716 sctx
->db_depth_clear
= true;
717 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
720 if (buffers
& PIPE_CLEAR_STENCIL
) {
723 /* Need to disable EXPCLEAR temporarily if clearing
725 if (!zstex
->stencil_cleared
|| zstex
->stencil_clear_value
!= stencil
) {
726 sctx
->db_stencil_disable_expclear
= true;
729 zstex
->stencil_clear_value
= stencil
;
730 sctx
->framebuffer
.dirty_zsbuf
= true;
731 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_STENCIL_CLEAR */
732 sctx
->db_stencil_clear
= true;
733 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
737 si_blitter_begin(ctx
, SI_CLEAR
);
738 util_blitter_clear(sctx
->blitter
, fb
->width
, fb
->height
,
739 util_framebuffer_get_num_layers(fb
),
740 buffers
, color
, depth
, stencil
);
743 if (sctx
->db_depth_clear
) {
744 sctx
->db_depth_clear
= false;
745 sctx
->db_depth_disable_expclear
= false;
746 zstex
->depth_cleared
= true;
747 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
750 if (sctx
->db_stencil_clear
) {
751 sctx
->db_stencil_clear
= false;
752 sctx
->db_stencil_disable_expclear
= false;
753 zstex
->stencil_cleared
= true;
754 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
758 static void si_clear_render_target(struct pipe_context
*ctx
,
759 struct pipe_surface
*dst
,
760 const union pipe_color_union
*color
,
761 unsigned dstx
, unsigned dsty
,
762 unsigned width
, unsigned height
)
764 struct si_context
*sctx
= (struct si_context
*)ctx
;
766 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
);
767 util_blitter_clear_render_target(sctx
->blitter
, dst
, color
,
768 dstx
, dsty
, width
, height
);
772 static void si_clear_depth_stencil(struct pipe_context
*ctx
,
773 struct pipe_surface
*dst
,
774 unsigned clear_flags
,
777 unsigned dstx
, unsigned dsty
,
778 unsigned width
, unsigned height
)
780 struct si_context
*sctx
= (struct si_context
*)ctx
;
782 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
);
783 util_blitter_clear_depth_stencil(sctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
784 dstx
, dsty
, width
, height
);
788 /* Helper for decompressing a portion of a color or depth resource before
789 * blitting if any decompression is needed.
790 * The driver doesn't decompress resources automatically while u_blitter is
792 static void si_decompress_subresource(struct pipe_context
*ctx
,
793 struct pipe_resource
*tex
,
794 unsigned planes
, unsigned level
,
795 unsigned first_layer
, unsigned last_layer
)
797 struct si_context
*sctx
= (struct si_context
*)ctx
;
798 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
800 if (rtex
->db_compatible
) {
801 planes
&= PIPE_MASK_Z
| PIPE_MASK_S
;
803 if (!(rtex
->surface
.flags
& RADEON_SURF_SBUFFER
))
804 planes
&= ~PIPE_MASK_S
;
806 si_flush_depth_texture(sctx
, rtex
, planes
,
808 first_layer
, last_layer
);
809 } else if (rtex
->fmask
.size
|| rtex
->cmask
.size
|| rtex
->dcc_offset
) {
810 si_blit_decompress_color(ctx
, rtex
, level
, level
,
811 first_layer
, last_layer
, false);
815 struct texture_orig_info
{
825 void si_resource_copy_region(struct pipe_context
*ctx
,
826 struct pipe_resource
*dst
,
828 unsigned dstx
, unsigned dsty
, unsigned dstz
,
829 struct pipe_resource
*src
,
831 const struct pipe_box
*src_box
)
833 struct si_context
*sctx
= (struct si_context
*)ctx
;
834 struct pipe_surface
*dst_view
, dst_templ
;
835 struct pipe_sampler_view src_templ
, *src_view
;
836 unsigned dst_width
, dst_height
, src_width0
, src_height0
;
837 unsigned src_force_level
= 0;
838 struct pipe_box sbox
, dstbox
;
840 /* Handle buffers first. */
841 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
842 si_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
);
846 assert(u_max_sample(dst
) == u_max_sample(src
));
848 /* The driver doesn't decompress resources automatically while
849 * u_blitter is rendering. */
850 si_decompress_subresource(ctx
, src
, PIPE_MASK_RGBAZS
, src_level
,
851 src_box
->z
, src_box
->z
+ src_box
->depth
- 1);
853 dst_width
= u_minify(dst
->width0
, dst_level
);
854 dst_height
= u_minify(dst
->height0
, dst_level
);
855 src_width0
= src
->width0
;
856 src_height0
= src
->height0
;
858 util_blitter_default_dst_texture(&dst_templ
, dst
, dst_level
, dstz
);
859 util_blitter_default_src_texture(&src_templ
, src
, src_level
);
861 if (util_format_is_compressed(src
->format
) ||
862 util_format_is_compressed(dst
->format
)) {
863 unsigned blocksize
= util_format_get_blocksize(src
->format
);
866 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; /* 64-bit block */
868 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; /* 128-bit block */
869 dst_templ
.format
= src_templ
.format
;
871 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
872 dst_height
= util_format_get_nblocksy(dst
->format
, dst_height
);
873 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
874 src_height0
= util_format_get_nblocksy(src
->format
, src_height0
);
876 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
877 dsty
= util_format_get_nblocksy(dst
->format
, dsty
);
879 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
880 sbox
.y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
882 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
883 sbox
.height
= util_format_get_nblocksy(src
->format
, src_box
->height
);
884 sbox
.depth
= src_box
->depth
;
887 src_force_level
= src_level
;
888 } else if (!util_blitter_is_copy_supported(sctx
->blitter
, dst
, src
) ||
889 /* also *8_SNORM has precision issues, use UNORM instead */
890 util_format_is_snorm8(src
->format
)) {
891 if (util_format_is_subsampled_422(src
->format
)) {
892 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
893 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
895 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
896 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
898 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
901 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
902 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
905 unsigned blocksize
= util_format_get_blocksize(src
->format
);
909 dst_templ
.format
= PIPE_FORMAT_R8_UNORM
;
910 src_templ
.format
= PIPE_FORMAT_R8_UNORM
;
913 dst_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
914 src_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
917 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
918 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
921 dst_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
922 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
925 dst_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
926 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
929 fprintf(stderr
, "Unhandled format %s with blocksize %u\n",
930 util_format_short_name(src
->format
), blocksize
);
936 /* Initialize the surface. */
937 dst_view
= r600_create_surface_custom(ctx
, dst
, &dst_templ
,
938 dst_width
, dst_height
);
940 /* Initialize the sampler view. */
941 src_view
= si_create_sampler_view_custom(ctx
, src
, &src_templ
,
942 src_width0
, src_height0
,
945 u_box_3d(dstx
, dsty
, dstz
, abs(src_box
->width
), abs(src_box
->height
),
946 abs(src_box
->depth
), &dstbox
);
949 si_blitter_begin(ctx
, SI_COPY
);
950 util_blitter_blit_generic(sctx
->blitter
, dst_view
, &dstbox
,
951 src_view
, src_box
, src_width0
, src_height0
,
952 PIPE_MASK_RGBAZS
, PIPE_TEX_FILTER_NEAREST
, NULL
,
956 pipe_surface_reference(&dst_view
, NULL
);
957 pipe_sampler_view_reference(&src_view
, NULL
);
960 static bool do_hardware_msaa_resolve(struct pipe_context
*ctx
,
961 const struct pipe_blit_info
*info
)
963 struct si_context
*sctx
= (struct si_context
*)ctx
;
964 struct r600_texture
*src
= (struct r600_texture
*)info
->src
.resource
;
965 struct r600_texture
*dst
= (struct r600_texture
*)info
->dst
.resource
;
966 unsigned dst_width
= u_minify(info
->dst
.resource
->width0
, info
->dst
.level
);
967 unsigned dst_height
= u_minify(info
->dst
.resource
->height0
, info
->dst
.level
);
968 enum pipe_format format
= info
->src
.format
;
969 unsigned sample_mask
= ~0;
970 struct pipe_resource
*tmp
, templ
;
971 struct pipe_blit_info blit
;
973 /* Check basic requirements for hw resolve. */
974 if (!(info
->src
.resource
->nr_samples
> 1 &&
975 info
->dst
.resource
->nr_samples
<= 1 &&
976 !util_format_is_pure_integer(format
) &&
977 !util_format_is_depth_or_stencil(format
) &&
978 util_max_layer(info
->src
.resource
, 0) == 0))
981 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
982 * the format is R16G16. Use R16A16, which does work.
984 if (format
== PIPE_FORMAT_R16G16_UNORM
)
985 format
= PIPE_FORMAT_R16A16_UNORM
;
986 if (format
== PIPE_FORMAT_R16G16_SNORM
)
987 format
= PIPE_FORMAT_R16A16_SNORM
;
989 /* Check the remaining requirements for hw resolve. */
990 if (util_max_layer(info
->dst
.resource
, info
->dst
.level
) == 0 &&
991 !info
->scissor_enable
&&
992 (info
->mask
& PIPE_MASK_RGBA
) == PIPE_MASK_RGBA
&&
993 util_is_format_compatible(util_format_description(info
->src
.format
),
994 util_format_description(info
->dst
.format
)) &&
995 dst_width
== info
->src
.resource
->width0
&&
996 dst_height
== info
->src
.resource
->height0
&&
997 info
->dst
.box
.x
== 0 &&
998 info
->dst
.box
.y
== 0 &&
999 info
->dst
.box
.width
== dst_width
&&
1000 info
->dst
.box
.height
== dst_height
&&
1001 info
->dst
.box
.depth
== 1 &&
1002 info
->src
.box
.x
== 0 &&
1003 info
->src
.box
.y
== 0 &&
1004 info
->src
.box
.width
== dst_width
&&
1005 info
->src
.box
.height
== dst_height
&&
1006 info
->src
.box
.depth
== 1 &&
1007 dst
->surface
.level
[info
->dst
.level
].mode
>= RADEON_SURF_MODE_1D
&&
1008 (!dst
->cmask
.size
|| !dst
->dirty_level_mask
)) { /* dst cannot be fast-cleared */
1009 /* Check the last constraint. */
1010 if (src
->surface
.micro_tile_mode
!= dst
->surface
.micro_tile_mode
) {
1011 /* The next fast clear will switch to this mode to
1012 * get direct hw resolve next time if the mode is
1015 src
->last_msaa_resolve_target_micro_mode
=
1016 dst
->surface
.micro_tile_mode
;
1017 goto resolve_to_temp
;
1020 /* Resolving into a surface with DCC is unsupported. Since
1021 * it's being overwritten anyway, clear it to uncompressed.
1022 * This is still the fastest codepath even with this clear.
1024 if (dst
->dcc_offset
&&
1025 dst
->surface
.level
[info
->dst
.level
].dcc_enabled
) {
1026 vi_dcc_clear_level(&sctx
->b
, dst
, info
->dst
.level
,
1028 dst
->dirty_level_mask
&= ~(1 << info
->dst
.level
);
1031 /* Resolve directly from src to dst. */
1032 si_blitter_begin(ctx
, SI_COLOR_RESOLVE
|
1033 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1034 util_blitter_custom_resolve_color(sctx
->blitter
,
1035 info
->dst
.resource
, info
->dst
.level
,
1037 info
->src
.resource
, info
->src
.box
.z
,
1038 sample_mask
, sctx
->custom_blend_resolve
,
1040 si_blitter_end(ctx
);
1045 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1046 * a temporary texture and blit.
1048 memset(&templ
, 0, sizeof(templ
));
1049 templ
.target
= PIPE_TEXTURE_2D
;
1050 templ
.format
= info
->src
.resource
->format
;
1051 templ
.width0
= info
->src
.resource
->width0
;
1052 templ
.height0
= info
->src
.resource
->height0
;
1054 templ
.array_size
= 1;
1055 templ
.usage
= PIPE_USAGE_DEFAULT
;
1056 templ
.flags
= R600_RESOURCE_FLAG_FORCE_TILING
|
1057 R600_RESOURCE_FLAG_DISABLE_DCC
;
1059 /* The src and dst microtile modes must be the same. */
1060 if (src
->surface
.micro_tile_mode
== V_009910_ADDR_SURF_DISPLAY_MICRO_TILING
)
1061 templ
.bind
= PIPE_BIND_SCANOUT
;
1065 tmp
= ctx
->screen
->resource_create(ctx
->screen
, &templ
);
1069 assert(src
->surface
.micro_tile_mode
==
1070 ((struct r600_texture
*)tmp
)->surface
.micro_tile_mode
);
1073 si_blitter_begin(ctx
, SI_COLOR_RESOLVE
|
1074 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1075 util_blitter_custom_resolve_color(sctx
->blitter
, tmp
, 0, 0,
1076 info
->src
.resource
, info
->src
.box
.z
,
1077 sample_mask
, sctx
->custom_blend_resolve
,
1079 si_blitter_end(ctx
);
1083 blit
.src
.resource
= tmp
;
1086 si_blitter_begin(ctx
, SI_BLIT
|
1087 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1088 util_blitter_blit(sctx
->blitter
, &blit
);
1089 si_blitter_end(ctx
);
1091 pipe_resource_reference(&tmp
, NULL
);
1095 static void si_blit(struct pipe_context
*ctx
,
1096 const struct pipe_blit_info
*info
)
1098 struct si_context
*sctx
= (struct si_context
*)ctx
;
1100 if (do_hardware_msaa_resolve(ctx
, info
)) {
1104 assert(util_blitter_is_blit_supported(sctx
->blitter
, info
));
1106 /* The driver doesn't decompress resources automatically while
1107 * u_blitter is rendering. */
1108 si_decompress_subresource(ctx
, info
->src
.resource
, info
->mask
,
1111 info
->src
.box
.z
+ info
->src
.box
.depth
- 1);
1113 if (sctx
->screen
->b
.debug_flags
& DBG_FORCE_DMA
&&
1114 util_try_blit_via_copy_region(ctx
, info
))
1117 si_blitter_begin(ctx
, SI_BLIT
|
1118 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1119 util_blitter_blit(sctx
->blitter
, info
);
1120 si_blitter_end(ctx
);
1123 static boolean
si_generate_mipmap(struct pipe_context
*ctx
,
1124 struct pipe_resource
*tex
,
1125 enum pipe_format format
,
1126 unsigned base_level
, unsigned last_level
,
1127 unsigned first_layer
, unsigned last_layer
)
1129 struct si_context
*sctx
= (struct si_context
*)ctx
;
1130 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1132 if (!util_blitter_is_copy_supported(sctx
->blitter
, tex
, tex
))
1135 /* The driver doesn't decompress resources automatically while
1136 * u_blitter is rendering. */
1137 si_decompress_subresource(ctx
, tex
, PIPE_MASK_RGBAZS
,
1138 base_level
, first_layer
, last_layer
);
1140 /* Clear dirty_level_mask for the levels that will be overwritten. */
1141 assert(base_level
< last_level
);
1142 rtex
->dirty_level_mask
&= ~u_bit_consecutive(base_level
+ 1,
1143 last_level
- base_level
);
1145 si_blitter_begin(ctx
, SI_BLIT
| SI_DISABLE_RENDER_COND
);
1146 util_blitter_generate_mipmap(sctx
->blitter
, tex
, format
,
1147 base_level
, last_level
,
1148 first_layer
, last_layer
);
1149 si_blitter_end(ctx
);
1153 static void si_flush_resource(struct pipe_context
*ctx
,
1154 struct pipe_resource
*res
)
1156 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
1158 assert(res
->target
!= PIPE_BUFFER
);
1159 assert(!rtex
->dcc_separate_buffer
|| rtex
->dcc_gather_statistics
);
1161 /* st/dri calls flush twice per frame (not a bug), this prevents double
1163 if (rtex
->dcc_separate_buffer
&& !rtex
->separate_dcc_dirty
)
1166 if (!rtex
->is_depth
&& (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
1167 si_blit_decompress_color(ctx
, rtex
, 0, res
->last_level
,
1168 0, util_max_layer(res
, 0),
1169 rtex
->dcc_separate_buffer
!= NULL
);
1172 /* Always do the analysis even if DCC is disabled at the moment. */
1173 if (rtex
->dcc_gather_statistics
&& rtex
->separate_dcc_dirty
) {
1174 rtex
->separate_dcc_dirty
= false;
1175 vi_separate_dcc_process_and_reset_stats(ctx
, rtex
);
1179 static void si_decompress_dcc(struct pipe_context
*ctx
,
1180 struct r600_texture
*rtex
)
1182 if (!rtex
->dcc_offset
)
1185 si_blit_decompress_color(ctx
, rtex
, 0, rtex
->resource
.b
.b
.last_level
,
1186 0, util_max_layer(&rtex
->resource
.b
.b
, 0),
1190 static void si_pipe_clear_buffer(struct pipe_context
*ctx
,
1191 struct pipe_resource
*dst
,
1192 unsigned offset
, unsigned size
,
1193 const void *clear_value_ptr
,
1194 int clear_value_size
)
1196 struct si_context
*sctx
= (struct si_context
*)ctx
;
1197 uint32_t dword_value
;
1200 assert(offset
% clear_value_size
== 0);
1201 assert(size
% clear_value_size
== 0);
1203 if (clear_value_size
> 4) {
1204 const uint32_t *u32
= clear_value_ptr
;
1205 bool clear_dword_duplicated
= true;
1207 /* See if we can lower large fills to dword fills. */
1208 for (i
= 1; i
< clear_value_size
/ 4; i
++)
1209 if (u32
[0] != u32
[i
]) {
1210 clear_dword_duplicated
= false;
1214 if (!clear_dword_duplicated
) {
1215 /* Use transform feedback for 64-bit, 96-bit, and
1218 union pipe_color_union clear_value
;
1220 memcpy(&clear_value
, clear_value_ptr
, clear_value_size
);
1221 si_blitter_begin(ctx
, SI_DISABLE_RENDER_COND
);
1222 util_blitter_clear_buffer(sctx
->blitter
, dst
, offset
,
1223 size
, clear_value_size
/ 4,
1225 si_blitter_end(ctx
);
1230 /* Expand the clear value to a dword. */
1231 switch (clear_value_size
) {
1233 dword_value
= *(uint8_t*)clear_value_ptr
;
1234 dword_value
|= (dword_value
<< 8) |
1235 (dword_value
<< 16) |
1236 (dword_value
<< 24);
1239 dword_value
= *(uint16_t*)clear_value_ptr
;
1240 dword_value
|= dword_value
<< 16;
1243 dword_value
= *(uint32_t*)clear_value_ptr
;
1246 sctx
->b
.clear_buffer(ctx
, dst
, offset
, size
, dword_value
,
1247 R600_COHERENCY_SHADER
);
1250 void si_init_blit_functions(struct si_context
*sctx
)
1252 sctx
->b
.b
.clear
= si_clear
;
1253 sctx
->b
.b
.clear_buffer
= si_pipe_clear_buffer
;
1254 sctx
->b
.b
.clear_render_target
= si_clear_render_target
;
1255 sctx
->b
.b
.clear_depth_stencil
= si_clear_depth_stencil
;
1256 sctx
->b
.b
.resource_copy_region
= si_resource_copy_region
;
1257 sctx
->b
.b
.blit
= si_blit
;
1258 sctx
->b
.b
.flush_resource
= si_flush_resource
;
1259 sctx
->b
.b
.generate_mipmap
= si_generate_mipmap
;
1260 sctx
->b
.blit_decompress_depth
= si_blit_decompress_depth
;
1261 sctx
->b
.decompress_dcc
= si_decompress_dcc
;