2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_surface.h"
30 enum si_blitter_op
/* bitmask */
33 SI_SAVE_FRAMEBUFFER
= 2,
34 SI_SAVE_FRAGMENT_STATE
= 4,
35 SI_DISABLE_RENDER_COND
= 8,
37 SI_CLEAR
= SI_SAVE_FRAGMENT_STATE
,
39 SI_CLEAR_SURFACE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
,
41 SI_COPY
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
42 SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
44 SI_BLIT
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
45 SI_SAVE_FRAGMENT_STATE
,
47 SI_DECOMPRESS
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
|
48 SI_DISABLE_RENDER_COND
,
50 SI_COLOR_RESOLVE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
53 static void si_blitter_begin(struct pipe_context
*ctx
, enum si_blitter_op op
)
55 struct si_context
*sctx
= (struct si_context
*)ctx
;
57 util_blitter_save_vertex_shader(sctx
->blitter
, sctx
->vs_shader
.cso
);
58 util_blitter_save_tessctrl_shader(sctx
->blitter
, sctx
->tcs_shader
.cso
);
59 util_blitter_save_tesseval_shader(sctx
->blitter
, sctx
->tes_shader
.cso
);
60 util_blitter_save_geometry_shader(sctx
->blitter
, sctx
->gs_shader
.cso
);
61 util_blitter_save_so_targets(sctx
->blitter
, sctx
->b
.streamout
.num_targets
,
62 (struct pipe_stream_output_target
**)sctx
->b
.streamout
.targets
);
63 util_blitter_save_rasterizer(sctx
->blitter
, sctx
->queued
.named
.rasterizer
);
65 if (op
& SI_SAVE_FRAGMENT_STATE
) {
66 util_blitter_save_blend(sctx
->blitter
, sctx
->queued
.named
.blend
);
67 util_blitter_save_depth_stencil_alpha(sctx
->blitter
, sctx
->queued
.named
.dsa
);
68 util_blitter_save_stencil_ref(sctx
->blitter
, &sctx
->stencil_ref
.state
);
69 util_blitter_save_fragment_shader(sctx
->blitter
, sctx
->ps_shader
.cso
);
70 util_blitter_save_sample_mask(sctx
->blitter
, sctx
->sample_mask
.sample_mask
);
71 util_blitter_save_scissor(sctx
->blitter
, &sctx
->scissors
.states
[0]);
74 if (op
& SI_SAVE_FRAMEBUFFER
)
75 util_blitter_save_framebuffer(sctx
->blitter
, &sctx
->framebuffer
.state
);
77 if (op
& SI_SAVE_TEXTURES
) {
78 util_blitter_save_fragment_sampler_states(
80 (void**)sctx
->samplers
[PIPE_SHADER_FRAGMENT
].sampler_states
);
82 util_blitter_save_fragment_sampler_views(sctx
->blitter
, 2,
83 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
);
86 if (op
& SI_DISABLE_RENDER_COND
)
87 sctx
->b
.render_cond_force_off
= true;
90 static void si_blitter_end(struct pipe_context
*ctx
)
92 struct si_context
*sctx
= (struct si_context
*)ctx
;
94 sctx
->b
.render_cond_force_off
= false;
96 /* Restore shader pointers because the VS blit shader changed all
97 * non-global VS user SGPRs. */
98 sctx
->shader_pointers_dirty
|= SI_VS_SHADER_POINTER_MASK
;
99 sctx
->vertex_buffer_pointer_dirty
= true;
100 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
103 static unsigned u_max_sample(struct pipe_resource
*r
)
105 return r
->nr_samples
? r
->nr_samples
- 1 : 0;
109 si_blit_dbcb_copy(struct si_context
*sctx
,
110 struct r600_texture
*src
,
111 struct r600_texture
*dst
,
112 unsigned planes
, unsigned level_mask
,
113 unsigned first_layer
, unsigned last_layer
,
114 unsigned first_sample
, unsigned last_sample
)
116 struct pipe_surface surf_tmpl
= {{0}};
117 unsigned layer
, sample
, checked_last_layer
, max_layer
;
118 unsigned fully_copied_levels
= 0;
120 if (planes
& PIPE_MASK_Z
)
121 sctx
->dbcb_depth_copy_enabled
= true;
122 if (planes
& PIPE_MASK_S
)
123 sctx
->dbcb_stencil_copy_enabled
= true;
124 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
126 assert(sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
);
128 sctx
->decompression_enabled
= true;
131 unsigned level
= u_bit_scan(&level_mask
);
133 /* The smaller the mipmap level, the less layers there are
134 * as far as 3D textures are concerned. */
135 max_layer
= util_max_layer(&src
->resource
.b
.b
, level
);
136 checked_last_layer
= MIN2(last_layer
, max_layer
);
138 surf_tmpl
.u
.tex
.level
= level
;
140 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
141 struct pipe_surface
*zsurf
, *cbsurf
;
143 surf_tmpl
.format
= src
->resource
.b
.b
.format
;
144 surf_tmpl
.u
.tex
.first_layer
= layer
;
145 surf_tmpl
.u
.tex
.last_layer
= layer
;
147 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &src
->resource
.b
.b
, &surf_tmpl
);
149 surf_tmpl
.format
= dst
->resource
.b
.b
.format
;
150 cbsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &dst
->resource
.b
.b
, &surf_tmpl
);
152 for (sample
= first_sample
; sample
<= last_sample
; sample
++) {
153 if (sample
!= sctx
->dbcb_copy_sample
) {
154 sctx
->dbcb_copy_sample
= sample
;
155 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
158 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
159 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, cbsurf
, 1 << sample
,
160 sctx
->custom_dsa_flush
, 1.0f
);
161 si_blitter_end(&sctx
->b
.b
);
164 pipe_surface_reference(&zsurf
, NULL
);
165 pipe_surface_reference(&cbsurf
, NULL
);
168 if (first_layer
== 0 && last_layer
>= max_layer
&&
169 first_sample
== 0 && last_sample
>= u_max_sample(&src
->resource
.b
.b
))
170 fully_copied_levels
|= 1u << level
;
173 sctx
->decompression_enabled
= false;
174 sctx
->dbcb_depth_copy_enabled
= false;
175 sctx
->dbcb_stencil_copy_enabled
= false;
176 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
178 return fully_copied_levels
;
181 static void si_blit_decompress_depth(struct pipe_context
*ctx
,
182 struct r600_texture
*texture
,
183 struct r600_texture
*staging
,
184 unsigned first_level
, unsigned last_level
,
185 unsigned first_layer
, unsigned last_layer
,
186 unsigned first_sample
, unsigned last_sample
)
188 const struct util_format_description
*desc
;
191 assert(staging
!= NULL
&& "use si_blit_decompress_zs_in_place instead");
193 desc
= util_format_description(staging
->resource
.b
.b
.format
);
195 if (util_format_has_depth(desc
))
196 planes
|= PIPE_MASK_Z
;
197 if (util_format_has_stencil(desc
))
198 planes
|= PIPE_MASK_S
;
201 (struct si_context
*)ctx
, texture
, staging
, planes
,
202 u_bit_consecutive(first_level
, last_level
- first_level
+ 1),
203 first_layer
, last_layer
, first_sample
, last_sample
);
206 /* Helper function for si_blit_decompress_zs_in_place.
209 si_blit_decompress_zs_planes_in_place(struct si_context
*sctx
,
210 struct r600_texture
*texture
,
211 unsigned planes
, unsigned level_mask
,
212 unsigned first_layer
, unsigned last_layer
)
214 struct pipe_surface
*zsurf
, surf_tmpl
= {{0}};
215 unsigned layer
, max_layer
, checked_last_layer
;
216 unsigned fully_decompressed_mask
= 0;
221 if (planes
& PIPE_MASK_S
)
222 sctx
->db_flush_stencil_inplace
= true;
223 if (planes
& PIPE_MASK_Z
)
224 sctx
->db_flush_depth_inplace
= true;
225 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
227 surf_tmpl
.format
= texture
->resource
.b
.b
.format
;
229 sctx
->decompression_enabled
= true;
232 unsigned level
= u_bit_scan(&level_mask
);
234 surf_tmpl
.u
.tex
.level
= level
;
236 /* The smaller the mipmap level, the less layers there are
237 * as far as 3D textures are concerned. */
238 max_layer
= util_max_layer(&texture
->resource
.b
.b
, level
);
239 checked_last_layer
= MIN2(last_layer
, max_layer
);
241 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
242 surf_tmpl
.u
.tex
.first_layer
= layer
;
243 surf_tmpl
.u
.tex
.last_layer
= layer
;
245 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &texture
->resource
.b
.b
, &surf_tmpl
);
247 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
248 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, NULL
, ~0,
249 sctx
->custom_dsa_flush
,
251 si_blitter_end(&sctx
->b
.b
);
253 pipe_surface_reference(&zsurf
, NULL
);
256 /* The texture will always be dirty if some layers aren't flushed.
257 * I don't think this case occurs often though. */
258 if (first_layer
== 0 && last_layer
>= max_layer
) {
259 fully_decompressed_mask
|= 1u << level
;
263 if (planes
& PIPE_MASK_Z
)
264 texture
->dirty_level_mask
&= ~fully_decompressed_mask
;
265 if (planes
& PIPE_MASK_S
)
266 texture
->stencil_dirty_level_mask
&= ~fully_decompressed_mask
;
268 sctx
->decompression_enabled
= false;
269 sctx
->db_flush_depth_inplace
= false;
270 sctx
->db_flush_stencil_inplace
= false;
271 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
274 /* Helper function of si_flush_depth_texture: decompress the given levels
275 * of Z and/or S planes in place.
278 si_blit_decompress_zs_in_place(struct si_context
*sctx
,
279 struct r600_texture
*texture
,
280 unsigned levels_z
, unsigned levels_s
,
281 unsigned first_layer
, unsigned last_layer
)
283 unsigned both
= levels_z
& levels_s
;
285 /* First, do combined Z & S decompresses for levels that need it. */
287 si_blit_decompress_zs_planes_in_place(
288 sctx
, texture
, PIPE_MASK_Z
| PIPE_MASK_S
,
290 first_layer
, last_layer
);
295 /* Now do separate Z and S decompresses. */
297 si_blit_decompress_zs_planes_in_place(
298 sctx
, texture
, PIPE_MASK_Z
,
300 first_layer
, last_layer
);
304 si_blit_decompress_zs_planes_in_place(
305 sctx
, texture
, PIPE_MASK_S
,
307 first_layer
, last_layer
);
312 si_decompress_depth(struct si_context
*sctx
,
313 struct r600_texture
*tex
,
314 unsigned required_planes
,
315 unsigned first_level
, unsigned last_level
,
316 unsigned first_layer
, unsigned last_layer
)
318 unsigned inplace_planes
= 0;
319 unsigned copy_planes
= 0;
320 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
321 unsigned levels_z
= 0;
322 unsigned levels_s
= 0;
324 if (required_planes
& PIPE_MASK_Z
) {
325 levels_z
= level_mask
& tex
->dirty_level_mask
;
328 if (r600_can_sample_zs(tex
, false))
329 inplace_planes
|= PIPE_MASK_Z
;
331 copy_planes
|= PIPE_MASK_Z
;
334 if (required_planes
& PIPE_MASK_S
) {
335 levels_s
= level_mask
& tex
->stencil_dirty_level_mask
;
338 if (r600_can_sample_zs(tex
, true))
339 inplace_planes
|= PIPE_MASK_S
;
341 copy_planes
|= PIPE_MASK_S
;
345 if (unlikely(sctx
->b
.log
))
346 u_log_printf(sctx
->b
.log
,
347 "\n------------------------------------------------\n"
348 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
349 first_level
, last_level
, levels_z
, levels_s
);
351 /* We may have to allocate the flushed texture here when called from
352 * si_decompress_subresource.
355 (tex
->flushed_depth_texture
||
356 si_init_flushed_depth_texture(&sctx
->b
.b
, &tex
->resource
.b
.b
, NULL
))) {
357 struct r600_texture
*dst
= tex
->flushed_depth_texture
;
358 unsigned fully_copied_levels
;
361 assert(tex
->flushed_depth_texture
);
363 if (util_format_is_depth_and_stencil(dst
->resource
.b
.b
.format
))
364 copy_planes
= PIPE_MASK_Z
| PIPE_MASK_S
;
366 if (copy_planes
& PIPE_MASK_Z
) {
370 if (copy_planes
& PIPE_MASK_S
) {
375 fully_copied_levels
= si_blit_dbcb_copy(
376 sctx
, tex
, dst
, copy_planes
, levels
,
377 first_layer
, last_layer
,
378 0, u_max_sample(&tex
->resource
.b
.b
));
380 if (copy_planes
& PIPE_MASK_Z
)
381 tex
->dirty_level_mask
&= ~fully_copied_levels
;
382 if (copy_planes
& PIPE_MASK_S
)
383 tex
->stencil_dirty_level_mask
&= ~fully_copied_levels
;
386 if (inplace_planes
) {
387 bool has_htile
= r600_htile_enabled(tex
, first_level
);
388 bool tc_compat_htile
= vi_tc_compat_htile_enabled(tex
, first_level
);
390 /* Don't decompress if there is no HTILE or when HTILE is
392 if (has_htile
&& !tc_compat_htile
) {
393 si_blit_decompress_zs_in_place(
396 first_layer
, last_layer
);
398 /* This is only a cache flush.
400 * Only clear the mask that we are flushing, because
401 * si_make_DB_shader_coherent() treats different levels
402 * and depth and stencil differently.
404 if (inplace_planes
& PIPE_MASK_Z
)
405 tex
->dirty_level_mask
&= ~levels_z
;
406 if (inplace_planes
& PIPE_MASK_S
)
407 tex
->stencil_dirty_level_mask
&= ~levels_s
;
410 /* Only in-place decompression needs to flush DB caches, or
411 * when we don't decompress but TC-compatible planes are dirty.
413 si_make_DB_shader_coherent(sctx
, tex
->resource
.b
.b
.nr_samples
,
414 inplace_planes
& PIPE_MASK_S
,
417 /* set_framebuffer_state takes care of coherency for single-sample.
418 * The DB->CB copy uses CB for the final writes.
420 if (copy_planes
&& tex
->resource
.b
.b
.nr_samples
> 1)
421 si_make_CB_shader_coherent(sctx
, tex
->resource
.b
.b
.nr_samples
,
426 si_decompress_sampler_depth_textures(struct si_context
*sctx
,
427 struct si_samplers
*textures
)
430 unsigned mask
= textures
->needs_depth_decompress_mask
;
433 struct pipe_sampler_view
*view
;
434 struct si_sampler_view
*sview
;
435 struct r600_texture
*tex
;
437 i
= u_bit_scan(&mask
);
439 view
= textures
->views
[i
];
441 sview
= (struct si_sampler_view
*)view
;
443 tex
= (struct r600_texture
*)view
->texture
;
444 assert(tex
->db_compatible
);
446 si_decompress_depth(sctx
, tex
,
447 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
448 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
449 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
453 static void si_blit_decompress_color(struct pipe_context
*ctx
,
454 struct r600_texture
*rtex
,
455 unsigned first_level
, unsigned last_level
,
456 unsigned first_layer
, unsigned last_layer
,
457 bool need_dcc_decompress
)
459 struct si_context
*sctx
= (struct si_context
*)ctx
;
461 unsigned layer
, checked_last_layer
, max_layer
;
462 unsigned level_mask
=
463 u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
465 if (!need_dcc_decompress
)
466 level_mask
&= rtex
->dirty_level_mask
;
470 if (unlikely(sctx
->b
.log
))
471 u_log_printf(sctx
->b
.log
,
472 "\n------------------------------------------------\n"
473 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
474 first_level
, last_level
, level_mask
);
476 if (need_dcc_decompress
) {
477 custom_blend
= sctx
->custom_blend_dcc_decompress
;
479 assert(rtex
->dcc_offset
);
481 /* disable levels without DCC */
482 for (int i
= first_level
; i
<= last_level
; i
++) {
483 if (!vi_dcc_enabled(rtex
, i
))
484 level_mask
&= ~(1 << i
);
486 } else if (rtex
->fmask
.size
) {
487 custom_blend
= sctx
->custom_blend_fmask_decompress
;
489 custom_blend
= sctx
->custom_blend_eliminate_fastclear
;
492 sctx
->decompression_enabled
= true;
495 unsigned level
= u_bit_scan(&level_mask
);
497 /* The smaller the mipmap level, the less layers there are
498 * as far as 3D textures are concerned. */
499 max_layer
= util_max_layer(&rtex
->resource
.b
.b
, level
);
500 checked_last_layer
= MIN2(last_layer
, max_layer
);
502 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
503 struct pipe_surface
*cbsurf
, surf_tmpl
;
505 surf_tmpl
.format
= rtex
->resource
.b
.b
.format
;
506 surf_tmpl
.u
.tex
.level
= level
;
507 surf_tmpl
.u
.tex
.first_layer
= layer
;
508 surf_tmpl
.u
.tex
.last_layer
= layer
;
509 cbsurf
= ctx
->create_surface(ctx
, &rtex
->resource
.b
.b
, &surf_tmpl
);
511 /* Required before and after FMASK and DCC_DECOMPRESS. */
512 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
513 custom_blend
== sctx
->custom_blend_dcc_decompress
)
514 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
516 si_blitter_begin(ctx
, SI_DECOMPRESS
);
517 util_blitter_custom_color(sctx
->blitter
, cbsurf
, custom_blend
);
520 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
521 custom_blend
== sctx
->custom_blend_dcc_decompress
)
522 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
524 pipe_surface_reference(&cbsurf
, NULL
);
527 /* The texture will always be dirty if some layers aren't flushed.
528 * I don't think this case occurs often though. */
529 if (first_layer
== 0 && last_layer
>= max_layer
) {
530 rtex
->dirty_level_mask
&= ~(1 << level
);
534 sctx
->decompression_enabled
= false;
535 si_make_CB_shader_coherent(sctx
, rtex
->resource
.b
.b
.nr_samples
,
536 vi_dcc_enabled(rtex
, first_level
));
540 si_decompress_color_texture(struct si_context
*sctx
, struct r600_texture
*tex
,
541 unsigned first_level
, unsigned last_level
)
543 /* CMASK or DCC can be discarded and we can still end up here. */
544 if (!tex
->cmask
.size
&& !tex
->fmask
.size
&& !tex
->dcc_offset
)
547 si_blit_decompress_color(&sctx
->b
.b
, tex
, first_level
, last_level
, 0,
548 util_max_layer(&tex
->resource
.b
.b
, first_level
),
553 si_decompress_sampler_color_textures(struct si_context
*sctx
,
554 struct si_samplers
*textures
)
557 unsigned mask
= textures
->needs_color_decompress_mask
;
560 struct pipe_sampler_view
*view
;
561 struct r600_texture
*tex
;
563 i
= u_bit_scan(&mask
);
565 view
= textures
->views
[i
];
568 tex
= (struct r600_texture
*)view
->texture
;
570 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
,
571 view
->u
.tex
.last_level
);
576 si_decompress_image_color_textures(struct si_context
*sctx
,
577 struct si_images
*images
)
580 unsigned mask
= images
->needs_color_decompress_mask
;
583 const struct pipe_image_view
*view
;
584 struct r600_texture
*tex
;
586 i
= u_bit_scan(&mask
);
588 view
= &images
->views
[i
];
589 assert(view
->resource
->target
!= PIPE_BUFFER
);
591 tex
= (struct r600_texture
*)view
->resource
;
593 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
,
598 static void si_check_render_feedback_texture(struct si_context
*sctx
,
599 struct r600_texture
*tex
,
600 unsigned first_level
,
602 unsigned first_layer
,
605 bool render_feedback
= false;
607 if (!tex
->dcc_offset
)
610 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
611 struct r600_surface
* surf
;
613 if (!sctx
->framebuffer
.state
.cbufs
[j
])
616 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
618 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
619 surf
->base
.u
.tex
.level
>= first_level
&&
620 surf
->base
.u
.tex
.level
<= last_level
&&
621 surf
->base
.u
.tex
.first_layer
<= last_layer
&&
622 surf
->base
.u
.tex
.last_layer
>= first_layer
) {
623 render_feedback
= true;
629 si_texture_disable_dcc(&sctx
->b
, tex
);
632 static void si_check_render_feedback_textures(struct si_context
*sctx
,
633 struct si_samplers
*textures
)
635 uint32_t mask
= textures
->enabled_mask
;
638 const struct pipe_sampler_view
*view
;
639 struct r600_texture
*tex
;
641 unsigned i
= u_bit_scan(&mask
);
643 view
= textures
->views
[i
];
644 if(view
->texture
->target
== PIPE_BUFFER
)
647 tex
= (struct r600_texture
*)view
->texture
;
649 si_check_render_feedback_texture(sctx
, tex
,
650 view
->u
.tex
.first_level
,
651 view
->u
.tex
.last_level
,
652 view
->u
.tex
.first_layer
,
653 view
->u
.tex
.last_layer
);
657 static void si_check_render_feedback_images(struct si_context
*sctx
,
658 struct si_images
*images
)
660 uint32_t mask
= images
->enabled_mask
;
663 const struct pipe_image_view
*view
;
664 struct r600_texture
*tex
;
666 unsigned i
= u_bit_scan(&mask
);
668 view
= &images
->views
[i
];
669 if (view
->resource
->target
== PIPE_BUFFER
)
672 tex
= (struct r600_texture
*)view
->resource
;
674 si_check_render_feedback_texture(sctx
, tex
,
677 view
->u
.tex
.first_layer
,
678 view
->u
.tex
.last_layer
);
682 static void si_check_render_feedback_resident_textures(struct si_context
*sctx
)
684 util_dynarray_foreach(&sctx
->resident_tex_handles
,
685 struct si_texture_handle
*, tex_handle
) {
686 struct pipe_sampler_view
*view
;
687 struct r600_texture
*tex
;
689 view
= (*tex_handle
)->view
;
690 if (view
->texture
->target
== PIPE_BUFFER
)
693 tex
= (struct r600_texture
*)view
->texture
;
695 si_check_render_feedback_texture(sctx
, tex
,
696 view
->u
.tex
.first_level
,
697 view
->u
.tex
.last_level
,
698 view
->u
.tex
.first_layer
,
699 view
->u
.tex
.last_layer
);
703 static void si_check_render_feedback_resident_images(struct si_context
*sctx
)
705 util_dynarray_foreach(&sctx
->resident_img_handles
,
706 struct si_image_handle
*, img_handle
) {
707 struct pipe_image_view
*view
;
708 struct r600_texture
*tex
;
710 view
= &(*img_handle
)->view
;
711 if (view
->resource
->target
== PIPE_BUFFER
)
714 tex
= (struct r600_texture
*)view
->resource
;
716 si_check_render_feedback_texture(sctx
, tex
,
719 view
->u
.tex
.first_layer
,
720 view
->u
.tex
.last_layer
);
724 static void si_check_render_feedback(struct si_context
*sctx
)
727 if (!sctx
->need_check_render_feedback
)
730 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
731 si_check_render_feedback_images(sctx
, &sctx
->images
[i
]);
732 si_check_render_feedback_textures(sctx
, &sctx
->samplers
[i
]);
735 si_check_render_feedback_resident_images(sctx
);
736 si_check_render_feedback_resident_textures(sctx
);
738 sctx
->need_check_render_feedback
= false;
741 static void si_decompress_resident_textures(struct si_context
*sctx
)
743 util_dynarray_foreach(&sctx
->resident_tex_needs_color_decompress
,
744 struct si_texture_handle
*, tex_handle
) {
745 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
746 struct r600_texture
*tex
= (struct r600_texture
*)view
->texture
;
748 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
,
749 view
->u
.tex
.last_level
);
752 util_dynarray_foreach(&sctx
->resident_tex_needs_depth_decompress
,
753 struct si_texture_handle
*, tex_handle
) {
754 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
755 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
756 struct r600_texture
*tex
= (struct r600_texture
*)view
->texture
;
758 si_decompress_depth(sctx
, tex
,
759 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
760 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
761 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
765 static void si_decompress_resident_images(struct si_context
*sctx
)
767 util_dynarray_foreach(&sctx
->resident_img_needs_color_decompress
,
768 struct si_image_handle
*, img_handle
) {
769 struct pipe_image_view
*view
= &(*img_handle
)->view
;
770 struct r600_texture
*tex
= (struct r600_texture
*)view
->resource
;
772 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
,
777 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
)
779 unsigned compressed_colortex_counter
, mask
;
781 if (sctx
->blitter
->running
)
784 /* Update the compressed_colortex_mask if necessary. */
785 compressed_colortex_counter
= p_atomic_read(&sctx
->screen
->b
.compressed_colortex_counter
);
786 if (compressed_colortex_counter
!= sctx
->b
.last_compressed_colortex_counter
) {
787 sctx
->b
.last_compressed_colortex_counter
= compressed_colortex_counter
;
788 si_update_needs_color_decompress_masks(sctx
);
791 /* Decompress color & depth textures if needed. */
792 mask
= sctx
->shader_needs_decompress_mask
& shader_mask
;
794 unsigned i
= u_bit_scan(&mask
);
796 if (sctx
->samplers
[i
].needs_depth_decompress_mask
) {
797 si_decompress_sampler_depth_textures(sctx
, &sctx
->samplers
[i
]);
799 if (sctx
->samplers
[i
].needs_color_decompress_mask
) {
800 si_decompress_sampler_color_textures(sctx
, &sctx
->samplers
[i
]);
802 if (sctx
->images
[i
].needs_color_decompress_mask
) {
803 si_decompress_image_color_textures(sctx
, &sctx
->images
[i
]);
807 if (shader_mask
& u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
)) {
808 if (sctx
->uses_bindless_samplers
)
809 si_decompress_resident_textures(sctx
);
810 if (sctx
->uses_bindless_images
)
811 si_decompress_resident_images(sctx
);
812 } else if (shader_mask
& (1 << PIPE_SHADER_COMPUTE
)) {
813 if (sctx
->cs_shader_state
.program
->uses_bindless_samplers
)
814 si_decompress_resident_textures(sctx
);
815 if (sctx
->cs_shader_state
.program
->uses_bindless_images
)
816 si_decompress_resident_images(sctx
);
819 si_check_render_feedback(sctx
);
822 static void si_clear(struct pipe_context
*ctx
, unsigned buffers
,
823 const union pipe_color_union
*color
,
824 double depth
, unsigned stencil
)
826 struct si_context
*sctx
= (struct si_context
*)ctx
;
827 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
828 struct pipe_surface
*zsbuf
= fb
->zsbuf
;
829 struct r600_texture
*zstex
=
830 zsbuf
? (struct r600_texture
*)zsbuf
->texture
: NULL
;
832 if (buffers
& PIPE_CLEAR_COLOR
) {
833 si_do_fast_color_clear(&sctx
->b
, fb
,
834 &sctx
->framebuffer
.atom
, &buffers
,
835 &sctx
->framebuffer
.dirty_cbufs
,
838 return; /* all buffers have been fast cleared */
841 if (buffers
& PIPE_CLEAR_COLOR
) {
844 /* These buffers cannot use fast clear, make sure to disable expansion. */
845 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
846 struct r600_texture
*tex
;
848 /* If not clearing this buffer, skip. */
849 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
855 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
856 if (tex
->fmask
.size
== 0)
857 tex
->dirty_level_mask
&= ~(1 << fb
->cbufs
[i
]->u
.tex
.level
);
862 r600_htile_enabled(zstex
, zsbuf
->u
.tex
.level
) &&
863 zsbuf
->u
.tex
.first_layer
== 0 &&
864 zsbuf
->u
.tex
.last_layer
== util_max_layer(&zstex
->resource
.b
.b
, 0)) {
865 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
866 if (buffers
& PIPE_CLEAR_DEPTH
&&
867 (!zstex
->tc_compatible_htile
||
868 depth
== 0 || depth
== 1)) {
869 /* Need to disable EXPCLEAR temporarily if clearing
871 if (!zstex
->depth_cleared
|| zstex
->depth_clear_value
!= depth
) {
872 sctx
->db_depth_disable_expclear
= true;
875 zstex
->depth_clear_value
= depth
;
876 sctx
->framebuffer
.dirty_zsbuf
= true;
877 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_DEPTH_CLEAR */
878 sctx
->db_depth_clear
= true;
879 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
882 /* TC-compatible HTILE only supports stencil clears to 0. */
883 if (buffers
& PIPE_CLEAR_STENCIL
&&
884 (!zstex
->tc_compatible_htile
|| stencil
== 0)) {
887 /* Need to disable EXPCLEAR temporarily if clearing
889 if (!zstex
->stencil_cleared
|| zstex
->stencil_clear_value
!= stencil
) {
890 sctx
->db_stencil_disable_expclear
= true;
893 zstex
->stencil_clear_value
= stencil
;
894 sctx
->framebuffer
.dirty_zsbuf
= true;
895 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_STENCIL_CLEAR */
896 sctx
->db_stencil_clear
= true;
897 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
900 /* TODO: Find out what's wrong here. Fast depth clear leads to
901 * corruption in ARK: Survival Evolved, but that may just be
902 * a coincidence and the root cause is elsewhere.
904 * The corruption can be fixed by putting the DB metadata flush
905 * before or after the depth clear. (suprisingly)
907 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
909 * This hack decreases back-to-back ClearDepth performance.
911 if (sctx
->screen
->clear_db_meta_before_clear
)
912 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
|
913 SI_CONTEXT_PS_PARTIAL_FLUSH
;
916 si_blitter_begin(ctx
, SI_CLEAR
);
917 util_blitter_clear(sctx
->blitter
, fb
->width
, fb
->height
,
918 util_framebuffer_get_num_layers(fb
),
919 buffers
, color
, depth
, stencil
);
922 if (sctx
->db_depth_clear
) {
923 sctx
->db_depth_clear
= false;
924 sctx
->db_depth_disable_expclear
= false;
925 zstex
->depth_cleared
= true;
926 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
929 if (sctx
->db_stencil_clear
) {
930 sctx
->db_stencil_clear
= false;
931 sctx
->db_stencil_disable_expclear
= false;
932 zstex
->stencil_cleared
= true;
933 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
937 static void si_clear_render_target(struct pipe_context
*ctx
,
938 struct pipe_surface
*dst
,
939 const union pipe_color_union
*color
,
940 unsigned dstx
, unsigned dsty
,
941 unsigned width
, unsigned height
,
942 bool render_condition_enabled
)
944 struct si_context
*sctx
= (struct si_context
*)ctx
;
946 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
|
947 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
948 util_blitter_clear_render_target(sctx
->blitter
, dst
, color
,
949 dstx
, dsty
, width
, height
);
953 static void si_clear_depth_stencil(struct pipe_context
*ctx
,
954 struct pipe_surface
*dst
,
955 unsigned clear_flags
,
958 unsigned dstx
, unsigned dsty
,
959 unsigned width
, unsigned height
,
960 bool render_condition_enabled
)
962 struct si_context
*sctx
= (struct si_context
*)ctx
;
964 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
|
965 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
966 util_blitter_clear_depth_stencil(sctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
967 dstx
, dsty
, width
, height
);
971 /* Helper for decompressing a portion of a color or depth resource before
972 * blitting if any decompression is needed.
973 * The driver doesn't decompress resources automatically while u_blitter is
975 static void si_decompress_subresource(struct pipe_context
*ctx
,
976 struct pipe_resource
*tex
,
977 unsigned planes
, unsigned level
,
978 unsigned first_layer
, unsigned last_layer
)
980 struct si_context
*sctx
= (struct si_context
*)ctx
;
981 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
983 if (rtex
->db_compatible
) {
984 planes
&= PIPE_MASK_Z
| PIPE_MASK_S
;
986 if (!rtex
->surface
.has_stencil
)
987 planes
&= ~PIPE_MASK_S
;
989 /* If we've rendered into the framebuffer and it's a blitting
990 * source, make sure the decompression pass is invoked
991 * by dirtying the framebuffer.
993 if (sctx
->framebuffer
.state
.zsbuf
&&
994 sctx
->framebuffer
.state
.zsbuf
->u
.tex
.level
== level
&&
995 sctx
->framebuffer
.state
.zsbuf
->texture
== tex
)
996 si_update_fb_dirtiness_after_rendering(sctx
);
998 si_decompress_depth(sctx
, rtex
, planes
,
1000 first_layer
, last_layer
);
1001 } else if (rtex
->fmask
.size
|| rtex
->cmask
.size
|| rtex
->dcc_offset
) {
1002 /* If we've rendered into the framebuffer and it's a blitting
1003 * source, make sure the decompression pass is invoked
1004 * by dirtying the framebuffer.
1006 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
1007 if (sctx
->framebuffer
.state
.cbufs
[i
] &&
1008 sctx
->framebuffer
.state
.cbufs
[i
]->u
.tex
.level
== level
&&
1009 sctx
->framebuffer
.state
.cbufs
[i
]->texture
== tex
) {
1010 si_update_fb_dirtiness_after_rendering(sctx
);
1015 si_blit_decompress_color(ctx
, rtex
, level
, level
,
1016 first_layer
, last_layer
, false);
1020 struct texture_orig_info
{
1030 void si_resource_copy_region(struct pipe_context
*ctx
,
1031 struct pipe_resource
*dst
,
1033 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1034 struct pipe_resource
*src
,
1036 const struct pipe_box
*src_box
)
1038 struct si_context
*sctx
= (struct si_context
*)ctx
;
1039 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
1040 struct pipe_surface
*dst_view
, dst_templ
;
1041 struct pipe_sampler_view src_templ
, *src_view
;
1042 unsigned dst_width
, dst_height
, src_width0
, src_height0
;
1043 unsigned dst_width0
, dst_height0
, src_force_level
= 0;
1044 struct pipe_box sbox
, dstbox
;
1046 /* Handle buffers first. */
1047 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
1048 si_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
, 0);
1052 assert(u_max_sample(dst
) == u_max_sample(src
));
1054 /* The driver doesn't decompress resources automatically while
1055 * u_blitter is rendering. */
1056 si_decompress_subresource(ctx
, src
, PIPE_MASK_RGBAZS
, src_level
,
1057 src_box
->z
, src_box
->z
+ src_box
->depth
- 1);
1059 dst_width
= u_minify(dst
->width0
, dst_level
);
1060 dst_height
= u_minify(dst
->height0
, dst_level
);
1061 dst_width0
= dst
->width0
;
1062 dst_height0
= dst
->height0
;
1063 src_width0
= src
->width0
;
1064 src_height0
= src
->height0
;
1066 util_blitter_default_dst_texture(&dst_templ
, dst
, dst_level
, dstz
);
1067 util_blitter_default_src_texture(sctx
->blitter
, &src_templ
, src
, src_level
);
1069 if (util_format_is_compressed(src
->format
) ||
1070 util_format_is_compressed(dst
->format
)) {
1071 unsigned blocksize
= rsrc
->surface
.bpe
;
1074 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; /* 64-bit block */
1076 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; /* 128-bit block */
1077 dst_templ
.format
= src_templ
.format
;
1079 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
1080 dst_height
= util_format_get_nblocksy(dst
->format
, dst_height
);
1081 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
1082 dst_height0
= util_format_get_nblocksy(dst
->format
, dst_height0
);
1083 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
1084 src_height0
= util_format_get_nblocksy(src
->format
, src_height0
);
1086 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
1087 dsty
= util_format_get_nblocksy(dst
->format
, dsty
);
1089 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
1090 sbox
.y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
1091 sbox
.z
= src_box
->z
;
1092 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
1093 sbox
.height
= util_format_get_nblocksy(src
->format
, src_box
->height
);
1094 sbox
.depth
= src_box
->depth
;
1097 src_force_level
= src_level
;
1098 } else if (!util_blitter_is_copy_supported(sctx
->blitter
, dst
, src
)) {
1099 if (util_format_is_subsampled_422(src
->format
)) {
1100 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
1101 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
1103 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
1104 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
1105 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
1107 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
1110 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
1111 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
1114 unsigned blocksize
= rsrc
->surface
.bpe
;
1116 switch (blocksize
) {
1118 dst_templ
.format
= PIPE_FORMAT_R8_UNORM
;
1119 src_templ
.format
= PIPE_FORMAT_R8_UNORM
;
1122 dst_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
1123 src_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
1126 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
1127 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
1130 dst_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1131 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1134 dst_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1135 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1138 fprintf(stderr
, "Unhandled format %s with blocksize %u\n",
1139 util_format_short_name(src
->format
), blocksize
);
1145 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1146 * equivalent instead, which doesn't force DCC decompression.
1147 * Note that some chips avoid this issue by using SDMA.
1149 if (util_format_is_snorm8(dst_templ
.format
)) {
1150 switch (dst_templ
.format
) {
1151 case PIPE_FORMAT_R8_SNORM
:
1152 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8_SINT
;
1154 case PIPE_FORMAT_R8G8_SNORM
:
1155 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8_SINT
;
1157 case PIPE_FORMAT_R8G8B8X8_SNORM
:
1158 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8B8X8_SINT
;
1160 case PIPE_FORMAT_R8G8B8A8_SNORM
:
1161 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1162 case PIPE_FORMAT_A8B8G8R8_SNORM
:
1163 case PIPE_FORMAT_X8B8G8R8_SNORM
:
1164 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8B8A8_SINT
;
1166 case PIPE_FORMAT_A8_SNORM
:
1167 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_A8_SINT
;
1169 case PIPE_FORMAT_L8_SNORM
:
1170 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_L8_SINT
;
1172 case PIPE_FORMAT_L8A8_SNORM
:
1173 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_L8A8_SINT
;
1175 case PIPE_FORMAT_I8_SNORM
:
1176 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_I8_SINT
;
1178 default:; /* fall through */
1182 vi_disable_dcc_if_incompatible_format(&sctx
->b
, dst
, dst_level
,
1184 vi_disable_dcc_if_incompatible_format(&sctx
->b
, src
, src_level
,
1187 /* Initialize the surface. */
1188 dst_view
= si_create_surface_custom(ctx
, dst
, &dst_templ
,
1189 dst_width0
, dst_height0
,
1190 dst_width
, dst_height
);
1192 /* Initialize the sampler view. */
1193 src_view
= si_create_sampler_view_custom(ctx
, src
, &src_templ
,
1194 src_width0
, src_height0
,
1197 u_box_3d(dstx
, dsty
, dstz
, abs(src_box
->width
), abs(src_box
->height
),
1198 abs(src_box
->depth
), &dstbox
);
1201 si_blitter_begin(ctx
, SI_COPY
);
1202 util_blitter_blit_generic(sctx
->blitter
, dst_view
, &dstbox
,
1203 src_view
, src_box
, src_width0
, src_height0
,
1204 PIPE_MASK_RGBAZS
, PIPE_TEX_FILTER_NEAREST
, NULL
,
1206 si_blitter_end(ctx
);
1208 pipe_surface_reference(&dst_view
, NULL
);
1209 pipe_sampler_view_reference(&src_view
, NULL
);
1212 static void si_do_CB_resolve(struct si_context
*sctx
,
1213 const struct pipe_blit_info
*info
,
1214 struct pipe_resource
*dst
,
1215 unsigned dst_level
, unsigned dst_z
,
1216 enum pipe_format format
)
1218 /* Required before and after CB_RESOLVE. */
1219 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
1221 si_blitter_begin(&sctx
->b
.b
, SI_COLOR_RESOLVE
|
1222 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1223 util_blitter_custom_resolve_color(sctx
->blitter
, dst
, dst_level
, dst_z
,
1224 info
->src
.resource
, info
->src
.box
.z
,
1225 ~0, sctx
->custom_blend_resolve
,
1227 si_blitter_end(&sctx
->b
.b
);
1229 /* Flush caches for possible texturing. */
1230 si_make_CB_shader_coherent(sctx
, 1, false);
1233 static bool do_hardware_msaa_resolve(struct pipe_context
*ctx
,
1234 const struct pipe_blit_info
*info
)
1236 struct si_context
*sctx
= (struct si_context
*)ctx
;
1237 struct r600_texture
*src
= (struct r600_texture
*)info
->src
.resource
;
1238 struct r600_texture
*dst
= (struct r600_texture
*)info
->dst
.resource
;
1239 MAYBE_UNUSED
struct r600_texture
*rtmp
;
1240 unsigned dst_width
= u_minify(info
->dst
.resource
->width0
, info
->dst
.level
);
1241 unsigned dst_height
= u_minify(info
->dst
.resource
->height0
, info
->dst
.level
);
1242 enum pipe_format format
= info
->src
.format
;
1243 struct pipe_resource
*tmp
, templ
;
1244 struct pipe_blit_info blit
;
1246 /* Check basic requirements for hw resolve. */
1247 if (!(info
->src
.resource
->nr_samples
> 1 &&
1248 info
->dst
.resource
->nr_samples
<= 1 &&
1249 !util_format_is_pure_integer(format
) &&
1250 !util_format_is_depth_or_stencil(format
) &&
1251 util_max_layer(info
->src
.resource
, 0) == 0))
1254 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1255 * the format is R16G16. Use R16A16, which does work.
1257 if (format
== PIPE_FORMAT_R16G16_UNORM
)
1258 format
= PIPE_FORMAT_R16A16_UNORM
;
1259 if (format
== PIPE_FORMAT_R16G16_SNORM
)
1260 format
= PIPE_FORMAT_R16A16_SNORM
;
1262 /* Check the remaining requirements for hw resolve. */
1263 if (util_max_layer(info
->dst
.resource
, info
->dst
.level
) == 0 &&
1264 !info
->scissor_enable
&&
1265 (info
->mask
& PIPE_MASK_RGBA
) == PIPE_MASK_RGBA
&&
1266 util_is_format_compatible(util_format_description(info
->src
.format
),
1267 util_format_description(info
->dst
.format
)) &&
1268 dst_width
== info
->src
.resource
->width0
&&
1269 dst_height
== info
->src
.resource
->height0
&&
1270 info
->dst
.box
.x
== 0 &&
1271 info
->dst
.box
.y
== 0 &&
1272 info
->dst
.box
.width
== dst_width
&&
1273 info
->dst
.box
.height
== dst_height
&&
1274 info
->dst
.box
.depth
== 1 &&
1275 info
->src
.box
.x
== 0 &&
1276 info
->src
.box
.y
== 0 &&
1277 info
->src
.box
.width
== dst_width
&&
1278 info
->src
.box
.height
== dst_height
&&
1279 info
->src
.box
.depth
== 1 &&
1280 !dst
->surface
.is_linear
&&
1281 (!dst
->cmask
.size
|| !dst
->dirty_level_mask
)) { /* dst cannot be fast-cleared */
1282 /* Check the last constraint. */
1283 if (src
->surface
.micro_tile_mode
!= dst
->surface
.micro_tile_mode
) {
1284 /* The next fast clear will switch to this mode to
1285 * get direct hw resolve next time if the mode is
1288 src
->last_msaa_resolve_target_micro_mode
=
1289 dst
->surface
.micro_tile_mode
;
1290 goto resolve_to_temp
;
1293 /* Resolving into a surface with DCC is unsupported. Since
1294 * it's being overwritten anyway, clear it to uncompressed.
1295 * This is still the fastest codepath even with this clear.
1297 if (vi_dcc_enabled(dst
, info
->dst
.level
)) {
1298 /* TODO: Implement per-level DCC clears for GFX9. */
1299 if (sctx
->b
.chip_class
>= GFX9
&&
1300 info
->dst
.resource
->last_level
!= 0)
1301 goto resolve_to_temp
;
1303 vi_dcc_clear_level(&sctx
->b
, dst
, info
->dst
.level
,
1305 dst
->dirty_level_mask
&= ~(1 << info
->dst
.level
);
1308 /* Resolve directly from src to dst. */
1309 si_do_CB_resolve(sctx
, info
, info
->dst
.resource
,
1310 info
->dst
.level
, info
->dst
.box
.z
, format
);
1315 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1316 * a temporary texture and blit.
1318 memset(&templ
, 0, sizeof(templ
));
1319 templ
.target
= PIPE_TEXTURE_2D
;
1320 templ
.format
= info
->src
.resource
->format
;
1321 templ
.width0
= info
->src
.resource
->width0
;
1322 templ
.height0
= info
->src
.resource
->height0
;
1324 templ
.array_size
= 1;
1325 templ
.usage
= PIPE_USAGE_DEFAULT
;
1326 templ
.flags
= R600_RESOURCE_FLAG_FORCE_TILING
|
1327 R600_RESOURCE_FLAG_DISABLE_DCC
;
1329 /* The src and dst microtile modes must be the same. */
1330 if (src
->surface
.micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
)
1331 templ
.bind
= PIPE_BIND_SCANOUT
;
1335 tmp
= ctx
->screen
->resource_create(ctx
->screen
, &templ
);
1338 rtmp
= (struct r600_texture
*)tmp
;
1340 assert(!rtmp
->surface
.is_linear
);
1341 assert(src
->surface
.micro_tile_mode
== rtmp
->surface
.micro_tile_mode
);
1344 si_do_CB_resolve(sctx
, info
, tmp
, 0, 0, format
);
1348 blit
.src
.resource
= tmp
;
1351 si_blitter_begin(ctx
, SI_BLIT
|
1352 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1353 util_blitter_blit(sctx
->blitter
, &blit
);
1354 si_blitter_end(ctx
);
1356 pipe_resource_reference(&tmp
, NULL
);
1360 static void si_blit(struct pipe_context
*ctx
,
1361 const struct pipe_blit_info
*info
)
1363 struct si_context
*sctx
= (struct si_context
*)ctx
;
1364 struct r600_texture
*rdst
= (struct r600_texture
*)info
->dst
.resource
;
1366 if (do_hardware_msaa_resolve(ctx
, info
)) {
1370 /* Using SDMA for copying to a linear texture in GTT is much faster.
1371 * This improves DRI PRIME performance.
1373 * resource_copy_region can't do this yet, because dma_copy calls it
1374 * on failure (recursion).
1376 if (rdst
->surface
.is_linear
&&
1378 util_can_blit_via_copy_region(info
, false)) {
1379 sctx
->b
.dma_copy(ctx
, info
->dst
.resource
, info
->dst
.level
,
1380 info
->dst
.box
.x
, info
->dst
.box
.y
,
1382 info
->src
.resource
, info
->src
.level
,
1387 assert(util_blitter_is_blit_supported(sctx
->blitter
, info
));
1389 /* The driver doesn't decompress resources automatically while
1390 * u_blitter is rendering. */
1391 vi_disable_dcc_if_incompatible_format(&sctx
->b
, info
->src
.resource
,
1394 vi_disable_dcc_if_incompatible_format(&sctx
->b
, info
->dst
.resource
,
1397 si_decompress_subresource(ctx
, info
->src
.resource
, info
->mask
,
1400 info
->src
.box
.z
+ info
->src
.box
.depth
- 1);
1402 if (sctx
->screen
->b
.debug_flags
& DBG(FORCE_DMA
) &&
1403 util_try_blit_via_copy_region(ctx
, info
))
1406 si_blitter_begin(ctx
, SI_BLIT
|
1407 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1408 util_blitter_blit(sctx
->blitter
, info
);
1409 si_blitter_end(ctx
);
1412 static boolean
si_generate_mipmap(struct pipe_context
*ctx
,
1413 struct pipe_resource
*tex
,
1414 enum pipe_format format
,
1415 unsigned base_level
, unsigned last_level
,
1416 unsigned first_layer
, unsigned last_layer
)
1418 struct si_context
*sctx
= (struct si_context
*)ctx
;
1419 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1421 if (!util_blitter_is_copy_supported(sctx
->blitter
, tex
, tex
))
1424 /* The driver doesn't decompress resources automatically while
1425 * u_blitter is rendering. */
1426 vi_disable_dcc_if_incompatible_format(&sctx
->b
, tex
, base_level
,
1428 si_decompress_subresource(ctx
, tex
, PIPE_MASK_RGBAZS
,
1429 base_level
, first_layer
, last_layer
);
1431 /* Clear dirty_level_mask for the levels that will be overwritten. */
1432 assert(base_level
< last_level
);
1433 rtex
->dirty_level_mask
&= ~u_bit_consecutive(base_level
+ 1,
1434 last_level
- base_level
);
1436 sctx
->generate_mipmap_for_depth
= rtex
->is_depth
;
1438 si_blitter_begin(ctx
, SI_BLIT
| SI_DISABLE_RENDER_COND
);
1439 util_blitter_generate_mipmap(sctx
->blitter
, tex
, format
,
1440 base_level
, last_level
,
1441 first_layer
, last_layer
);
1442 si_blitter_end(ctx
);
1444 sctx
->generate_mipmap_for_depth
= false;
1448 static void si_flush_resource(struct pipe_context
*ctx
,
1449 struct pipe_resource
*res
)
1451 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
1453 assert(res
->target
!= PIPE_BUFFER
);
1454 assert(!rtex
->dcc_separate_buffer
|| rtex
->dcc_gather_statistics
);
1456 /* st/dri calls flush twice per frame (not a bug), this prevents double
1458 if (rtex
->dcc_separate_buffer
&& !rtex
->separate_dcc_dirty
)
1461 if (!rtex
->is_depth
&& (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
1462 si_blit_decompress_color(ctx
, rtex
, 0, res
->last_level
,
1463 0, util_max_layer(res
, 0),
1464 rtex
->dcc_separate_buffer
!= NULL
);
1467 /* Always do the analysis even if DCC is disabled at the moment. */
1468 if (rtex
->dcc_gather_statistics
&& rtex
->separate_dcc_dirty
) {
1469 rtex
->separate_dcc_dirty
= false;
1470 vi_separate_dcc_process_and_reset_stats(ctx
, rtex
);
1474 static void si_decompress_dcc(struct pipe_context
*ctx
,
1475 struct r600_texture
*rtex
)
1477 if (!rtex
->dcc_offset
)
1480 si_blit_decompress_color(ctx
, rtex
, 0, rtex
->resource
.b
.b
.last_level
,
1481 0, util_max_layer(&rtex
->resource
.b
.b
, 0),
1485 static void si_pipe_clear_buffer(struct pipe_context
*ctx
,
1486 struct pipe_resource
*dst
,
1487 unsigned offset
, unsigned size
,
1488 const void *clear_value_ptr
,
1489 int clear_value_size
)
1491 struct si_context
*sctx
= (struct si_context
*)ctx
;
1492 uint32_t dword_value
;
1495 assert(offset
% clear_value_size
== 0);
1496 assert(size
% clear_value_size
== 0);
1498 if (clear_value_size
> 4) {
1499 const uint32_t *u32
= clear_value_ptr
;
1500 bool clear_dword_duplicated
= true;
1502 /* See if we can lower large fills to dword fills. */
1503 for (i
= 1; i
< clear_value_size
/ 4; i
++)
1504 if (u32
[0] != u32
[i
]) {
1505 clear_dword_duplicated
= false;
1509 if (!clear_dword_duplicated
) {
1510 /* Use transform feedback for 64-bit, 96-bit, and
1513 union pipe_color_union clear_value
;
1515 memcpy(&clear_value
, clear_value_ptr
, clear_value_size
);
1516 si_blitter_begin(ctx
, SI_DISABLE_RENDER_COND
);
1517 util_blitter_clear_buffer(sctx
->blitter
, dst
, offset
,
1518 size
, clear_value_size
/ 4,
1520 si_blitter_end(ctx
);
1525 /* Expand the clear value to a dword. */
1526 switch (clear_value_size
) {
1528 dword_value
= *(uint8_t*)clear_value_ptr
;
1529 dword_value
|= (dword_value
<< 8) |
1530 (dword_value
<< 16) |
1531 (dword_value
<< 24);
1534 dword_value
= *(uint16_t*)clear_value_ptr
;
1535 dword_value
|= dword_value
<< 16;
1538 dword_value
= *(uint32_t*)clear_value_ptr
;
1541 sctx
->b
.clear_buffer(ctx
, dst
, offset
, size
, dword_value
,
1542 R600_COHERENCY_SHADER
);
1545 void si_init_blit_functions(struct si_context
*sctx
)
1547 sctx
->b
.b
.clear
= si_clear
;
1548 sctx
->b
.b
.clear_buffer
= si_pipe_clear_buffer
;
1549 sctx
->b
.b
.clear_render_target
= si_clear_render_target
;
1550 sctx
->b
.b
.clear_depth_stencil
= si_clear_depth_stencil
;
1551 sctx
->b
.b
.resource_copy_region
= si_resource_copy_region
;
1552 sctx
->b
.b
.blit
= si_blit
;
1553 sctx
->b
.b
.flush_resource
= si_flush_resource
;
1554 sctx
->b
.b
.generate_mipmap
= si_generate_mipmap
;
1555 sctx
->b
.blit_decompress_depth
= si_blit_decompress_depth
;
1556 sctx
->b
.decompress_dcc
= si_decompress_dcc
;