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gallium: add render_condition_enable param to clear_render_target/depth_stencil
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "util/u_format.h"
27 #include "util/u_surface.h"
28
29 enum si_blitter_op /* bitmask */
30 {
31 SI_SAVE_TEXTURES = 1,
32 SI_SAVE_FRAMEBUFFER = 2,
33 SI_SAVE_FRAGMENT_STATE = 4,
34 SI_DISABLE_RENDER_COND = 8,
35
36 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
37
38 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
39
40 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
41 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
42
43 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
44 SI_SAVE_FRAGMENT_STATE,
45
46 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
47 SI_DISABLE_RENDER_COND,
48
49 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
50 };
51
52 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
53 {
54 struct si_context *sctx = (struct si_context *)ctx;
55
56 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
57 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
58 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
59 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
60 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
61 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
62 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
63 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
64 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
65
66 if (op & SI_SAVE_FRAGMENT_STATE) {
67 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
68 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
69 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
70 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
71 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
72 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
73 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
74 }
75
76 if (op & SI_SAVE_FRAMEBUFFER)
77 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
78
79 if (op & SI_SAVE_TEXTURES) {
80 util_blitter_save_fragment_sampler_states(
81 sctx->blitter, 2,
82 sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
83
84 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
85 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
86 }
87
88 if (op & SI_DISABLE_RENDER_COND)
89 sctx->b.render_cond_force_off = true;
90 }
91
92 static void si_blitter_end(struct pipe_context *ctx)
93 {
94 struct si_context *sctx = (struct si_context *)ctx;
95
96 sctx->b.render_cond_force_off = false;
97 }
98
99 static unsigned u_max_sample(struct pipe_resource *r)
100 {
101 return r->nr_samples ? r->nr_samples - 1 : 0;
102 }
103
104 static unsigned
105 si_blit_dbcb_copy(struct si_context *sctx,
106 struct r600_texture *src,
107 struct r600_texture *dst,
108 unsigned planes, unsigned level_mask,
109 unsigned first_layer, unsigned last_layer,
110 unsigned first_sample, unsigned last_sample)
111 {
112 struct pipe_surface surf_tmpl = {{0}};
113 unsigned layer, sample, checked_last_layer, max_layer;
114 unsigned fully_copied_levels = 0;
115
116 if (planes & PIPE_MASK_Z)
117 sctx->dbcb_depth_copy_enabled = true;
118 if (planes & PIPE_MASK_S)
119 sctx->dbcb_stencil_copy_enabled = true;
120 si_mark_atom_dirty(sctx, &sctx->db_render_state);
121
122 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
123
124 while (level_mask) {
125 unsigned level = u_bit_scan(&level_mask);
126
127 /* The smaller the mipmap level, the less layers there are
128 * as far as 3D textures are concerned. */
129 max_layer = util_max_layer(&src->resource.b.b, level);
130 checked_last_layer = MIN2(last_layer, max_layer);
131
132 surf_tmpl.u.tex.level = level;
133
134 for (layer = first_layer; layer <= checked_last_layer; layer++) {
135 struct pipe_surface *zsurf, *cbsurf;
136
137 surf_tmpl.format = src->resource.b.b.format;
138 surf_tmpl.u.tex.first_layer = layer;
139 surf_tmpl.u.tex.last_layer = layer;
140
141 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
142
143 surf_tmpl.format = dst->resource.b.b.format;
144 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
145
146 for (sample = first_sample; sample <= last_sample; sample++) {
147 if (sample != sctx->dbcb_copy_sample) {
148 sctx->dbcb_copy_sample = sample;
149 si_mark_atom_dirty(sctx, &sctx->db_render_state);
150 }
151
152 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
153 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
154 sctx->custom_dsa_flush, 1.0f);
155 si_blitter_end(&sctx->b.b);
156 }
157
158 pipe_surface_reference(&zsurf, NULL);
159 pipe_surface_reference(&cbsurf, NULL);
160 }
161
162 if (first_layer == 0 && last_layer >= max_layer &&
163 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
164 fully_copied_levels |= 1u << level;
165 }
166
167 sctx->dbcb_depth_copy_enabled = false;
168 sctx->dbcb_stencil_copy_enabled = false;
169 si_mark_atom_dirty(sctx, &sctx->db_render_state);
170
171 return fully_copied_levels;
172 }
173
174 static void si_blit_decompress_depth(struct pipe_context *ctx,
175 struct r600_texture *texture,
176 struct r600_texture *staging,
177 unsigned first_level, unsigned last_level,
178 unsigned first_layer, unsigned last_layer,
179 unsigned first_sample, unsigned last_sample)
180 {
181 const struct util_format_description *desc;
182 unsigned planes = 0;
183
184 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
185
186 desc = util_format_description(staging->resource.b.b.format);
187
188 if (util_format_has_depth(desc))
189 planes |= PIPE_MASK_Z;
190 if (util_format_has_stencil(desc))
191 planes |= PIPE_MASK_S;
192
193 si_blit_dbcb_copy(
194 (struct si_context *)ctx, texture, staging, planes,
195 u_bit_consecutive(first_level, last_level - first_level + 1),
196 first_layer, last_layer, first_sample, last_sample);
197 }
198
199 /* Helper function for si_blit_decompress_zs_in_place.
200 */
201 static void
202 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
203 struct r600_texture *texture,
204 unsigned planes, unsigned level_mask,
205 unsigned first_layer, unsigned last_layer)
206 {
207 struct pipe_surface *zsurf, surf_tmpl = {{0}};
208 unsigned layer, max_layer, checked_last_layer;
209 unsigned fully_decompressed_mask = 0;
210
211 if (!level_mask)
212 return;
213
214 if (planes & PIPE_MASK_S)
215 sctx->db_flush_stencil_inplace = true;
216 if (planes & PIPE_MASK_Z)
217 sctx->db_flush_depth_inplace = true;
218 si_mark_atom_dirty(sctx, &sctx->db_render_state);
219
220 surf_tmpl.format = texture->resource.b.b.format;
221
222 while (level_mask) {
223 unsigned level = u_bit_scan(&level_mask);
224
225 surf_tmpl.u.tex.level = level;
226
227 /* The smaller the mipmap level, the less layers there are
228 * as far as 3D textures are concerned. */
229 max_layer = util_max_layer(&texture->resource.b.b, level);
230 checked_last_layer = MIN2(last_layer, max_layer);
231
232 for (layer = first_layer; layer <= checked_last_layer; layer++) {
233 surf_tmpl.u.tex.first_layer = layer;
234 surf_tmpl.u.tex.last_layer = layer;
235
236 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
237
238 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
239 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
240 sctx->custom_dsa_flush,
241 1.0f);
242 si_blitter_end(&sctx->b.b);
243
244 pipe_surface_reference(&zsurf, NULL);
245 }
246
247 /* The texture will always be dirty if some layers aren't flushed.
248 * I don't think this case occurs often though. */
249 if (first_layer == 0 && last_layer >= max_layer) {
250 fully_decompressed_mask |= 1u << level;
251 }
252 }
253
254 if (planes & PIPE_MASK_Z)
255 texture->dirty_level_mask &= ~fully_decompressed_mask;
256 if (planes & PIPE_MASK_S)
257 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
258
259 sctx->db_flush_depth_inplace = false;
260 sctx->db_flush_stencil_inplace = false;
261 si_mark_atom_dirty(sctx, &sctx->db_render_state);
262 }
263
264 /* Helper function of si_flush_depth_texture: decompress the given levels
265 * of Z and/or S planes in place.
266 */
267 static void
268 si_blit_decompress_zs_in_place(struct si_context *sctx,
269 struct r600_texture *texture,
270 unsigned levels_z, unsigned levels_s,
271 unsigned first_layer, unsigned last_layer)
272 {
273 unsigned both = levels_z & levels_s;
274
275 /* First, do combined Z & S decompresses for levels that need it. */
276 if (both) {
277 si_blit_decompress_zs_planes_in_place(
278 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
279 both,
280 first_layer, last_layer);
281 levels_z &= ~both;
282 levels_s &= ~both;
283 }
284
285 /* Now do separate Z and S decompresses. */
286 if (levels_z) {
287 si_blit_decompress_zs_planes_in_place(
288 sctx, texture, PIPE_MASK_Z,
289 levels_z,
290 first_layer, last_layer);
291 }
292
293 if (levels_s) {
294 si_blit_decompress_zs_planes_in_place(
295 sctx, texture, PIPE_MASK_S,
296 levels_s,
297 first_layer, last_layer);
298 }
299 }
300
301 static void
302 si_flush_depth_texture(struct si_context *sctx,
303 struct r600_texture *tex,
304 unsigned required_planes,
305 unsigned first_level, unsigned last_level,
306 unsigned first_layer, unsigned last_layer)
307 {
308 unsigned inplace_planes = 0;
309 unsigned copy_planes = 0;
310 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
311 unsigned levels_z = 0;
312 unsigned levels_s = 0;
313
314 if (required_planes & PIPE_MASK_Z) {
315 levels_z = level_mask & tex->dirty_level_mask;
316
317 if (levels_z) {
318 if (r600_can_sample_zs(tex, false))
319 inplace_planes |= PIPE_MASK_Z;
320 else
321 copy_planes |= PIPE_MASK_Z;
322 }
323 }
324 if (required_planes & PIPE_MASK_S) {
325 levels_s = level_mask & tex->stencil_dirty_level_mask;
326
327 if (levels_s) {
328 if (r600_can_sample_zs(tex, true))
329 inplace_planes |= PIPE_MASK_S;
330 else
331 copy_planes |= PIPE_MASK_S;
332 }
333 }
334
335 /* We may have to allocate the flushed texture here when called from
336 * si_decompress_subresource.
337 */
338 if (copy_planes &&
339 (tex->flushed_depth_texture ||
340 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
341 struct r600_texture *dst = tex->flushed_depth_texture;
342 unsigned fully_copied_levels;
343 unsigned levels = 0;
344
345 assert(tex->flushed_depth_texture);
346
347 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
348 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
349
350 if (copy_planes & PIPE_MASK_Z) {
351 levels |= levels_z;
352 levels_z = 0;
353 }
354 if (copy_planes & PIPE_MASK_S) {
355 levels |= levels_s;
356 levels_s = 0;
357 }
358
359 fully_copied_levels = si_blit_dbcb_copy(
360 sctx, tex, dst, copy_planes, levels,
361 first_layer, last_layer,
362 0, u_max_sample(&tex->resource.b.b));
363
364 if (copy_planes & PIPE_MASK_Z)
365 tex->dirty_level_mask &= ~fully_copied_levels;
366 if (copy_planes & PIPE_MASK_S)
367 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
368 }
369
370 if (inplace_planes) {
371 si_blit_decompress_zs_in_place(
372 sctx, tex,
373 levels_z, levels_s,
374 first_layer, last_layer);
375 }
376 }
377
378 static void
379 si_flush_depth_textures(struct si_context *sctx,
380 struct si_textures_info *textures)
381 {
382 unsigned i;
383 unsigned mask = textures->depth_texture_mask;
384
385 while (mask) {
386 struct pipe_sampler_view *view;
387 struct si_sampler_view *sview;
388 struct r600_texture *tex;
389
390 i = u_bit_scan(&mask);
391
392 view = textures->views.views[i];
393 assert(view);
394 sview = (struct si_sampler_view*)view;
395
396 tex = (struct r600_texture *)view->texture;
397 assert(tex->db_compatible);
398
399 si_flush_depth_texture(
400 sctx, tex,
401 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
402 view->u.tex.first_level, view->u.tex.last_level,
403 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
404 }
405 }
406
407 static void si_blit_decompress_color(struct pipe_context *ctx,
408 struct r600_texture *rtex,
409 unsigned first_level, unsigned last_level,
410 unsigned first_layer, unsigned last_layer,
411 bool need_dcc_decompress)
412 {
413 struct si_context *sctx = (struct si_context *)ctx;
414 void* custom_blend;
415 unsigned layer, checked_last_layer, max_layer;
416 unsigned level_mask =
417 u_bit_consecutive(first_level, last_level - first_level + 1);
418
419 if (!need_dcc_decompress)
420 level_mask &= rtex->dirty_level_mask;
421 if (!level_mask)
422 return;
423
424 if (rtex->dcc_offset && need_dcc_decompress) {
425 custom_blend = sctx->custom_blend_dcc_decompress;
426
427 /* disable levels without DCC */
428 for (int i = first_level; i <= last_level; i++) {
429 if (!rtex->dcc_offset ||
430 !rtex->surface.level[i].dcc_enabled)
431 level_mask &= ~(1 << i);
432 }
433 } else if (rtex->fmask.size) {
434 custom_blend = sctx->custom_blend_decompress;
435 } else {
436 custom_blend = sctx->custom_blend_fastclear;
437 }
438
439 while (level_mask) {
440 unsigned level = u_bit_scan(&level_mask);
441
442 /* The smaller the mipmap level, the less layers there are
443 * as far as 3D textures are concerned. */
444 max_layer = util_max_layer(&rtex->resource.b.b, level);
445 checked_last_layer = MIN2(last_layer, max_layer);
446
447 for (layer = first_layer; layer <= checked_last_layer; layer++) {
448 struct pipe_surface *cbsurf, surf_tmpl;
449
450 surf_tmpl.format = rtex->resource.b.b.format;
451 surf_tmpl.u.tex.level = level;
452 surf_tmpl.u.tex.first_layer = layer;
453 surf_tmpl.u.tex.last_layer = layer;
454 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
455
456 si_blitter_begin(ctx, SI_DECOMPRESS);
457 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
458 si_blitter_end(ctx);
459
460 pipe_surface_reference(&cbsurf, NULL);
461 }
462
463 /* The texture will always be dirty if some layers aren't flushed.
464 * I don't think this case occurs often though. */
465 if (first_layer == 0 && last_layer >= max_layer) {
466 rtex->dirty_level_mask &= ~(1 << level);
467 }
468 }
469 }
470
471 static void
472 si_decompress_sampler_color_textures(struct si_context *sctx,
473 struct si_textures_info *textures)
474 {
475 unsigned i;
476 unsigned mask = textures->compressed_colortex_mask;
477
478 while (mask) {
479 struct pipe_sampler_view *view;
480 struct r600_texture *tex;
481
482 i = u_bit_scan(&mask);
483
484 view = textures->views.views[i];
485 assert(view);
486
487 tex = (struct r600_texture *)view->texture;
488 assert(tex->cmask.size || tex->fmask.size || tex->dcc_offset);
489
490 si_blit_decompress_color(&sctx->b.b, tex,
491 view->u.tex.first_level, view->u.tex.last_level,
492 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
493 false);
494 }
495 }
496
497 static void
498 si_decompress_image_color_textures(struct si_context *sctx,
499 struct si_images_info *images)
500 {
501 unsigned i;
502 unsigned mask = images->compressed_colortex_mask;
503
504 while (mask) {
505 const struct pipe_image_view *view;
506 struct r600_texture *tex;
507
508 i = u_bit_scan(&mask);
509
510 view = &images->views[i];
511 assert(view->resource->target != PIPE_BUFFER);
512
513 tex = (struct r600_texture *)view->resource;
514 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
515 continue;
516
517 si_blit_decompress_color(&sctx->b.b, tex,
518 view->u.tex.level, view->u.tex.level,
519 0, util_max_layer(&tex->resource.b.b, view->u.tex.level),
520 false);
521 }
522 }
523
524 static void si_check_render_feedback_textures(struct si_context *sctx,
525 struct si_textures_info *textures)
526 {
527 uint32_t mask = textures->views.enabled_mask;
528
529 while (mask) {
530 const struct pipe_sampler_view *view;
531 struct r600_texture *tex;
532 bool render_feedback = false;
533
534 unsigned i = u_bit_scan(&mask);
535
536 view = textures->views.views[i];
537 if(view->texture->target == PIPE_BUFFER)
538 continue;
539
540 tex = (struct r600_texture *)view->texture;
541 if (!tex->dcc_offset)
542 continue;
543
544 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
545 struct r600_surface * surf;
546
547 if (!sctx->framebuffer.state.cbufs[j])
548 continue;
549
550 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
551
552 if (tex == (struct r600_texture*)surf->base.texture &&
553 surf->base.u.tex.level >= view->u.tex.first_level &&
554 surf->base.u.tex.level <= view->u.tex.last_level &&
555 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
556 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
557 render_feedback = true;
558 }
559
560 if (render_feedback) {
561 struct si_screen *screen = sctx->screen;
562 r600_texture_disable_dcc(&screen->b, tex);
563 }
564 }
565 }
566
567 static void si_check_render_feedback_images(struct si_context *sctx,
568 struct si_images_info *images)
569 {
570 uint32_t mask = images->enabled_mask;
571
572 while (mask) {
573 const struct pipe_image_view *view;
574 struct r600_texture *tex;
575 bool render_feedback = false;
576
577 unsigned i = u_bit_scan(&mask);
578
579 view = &images->views[i];
580 if (view->resource->target == PIPE_BUFFER)
581 continue;
582
583 tex = (struct r600_texture *)view->resource;
584 if (!tex->dcc_offset)
585 continue;
586
587 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
588 struct r600_surface * surf;
589
590 if (!sctx->framebuffer.state.cbufs[j])
591 continue;
592
593 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
594
595 if (tex == (struct r600_texture*)surf->base.texture &&
596 surf->base.u.tex.level == view->u.tex.level &&
597 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
598 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
599 render_feedback = true;
600 }
601
602 if (render_feedback) {
603 struct si_screen *screen = sctx->screen;
604 r600_texture_disable_dcc(&screen->b, tex);
605 }
606 }
607 }
608
609 static void si_check_render_feedback(struct si_context *sctx)
610 {
611
612 if (!sctx->need_check_render_feedback)
613 return;
614
615 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
616 si_check_render_feedback_images(sctx, &sctx->images[i]);
617 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
618 }
619 sctx->need_check_render_feedback = false;
620 }
621
622 static void si_decompress_textures(struct si_context *sctx, int shader_start,
623 int shader_end)
624 {
625 unsigned compressed_colortex_counter;
626
627 if (sctx->blitter->running)
628 return;
629
630 /* Update the compressed_colortex_mask if necessary. */
631 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
632 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
633 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
634 si_update_compressed_colortex_masks(sctx);
635 }
636
637 /* Flush depth textures which need to be flushed. */
638 for (int i = shader_start; i < shader_end; i++) {
639 if (sctx->samplers[i].depth_texture_mask) {
640 si_flush_depth_textures(sctx, &sctx->samplers[i]);
641 }
642 if (sctx->samplers[i].compressed_colortex_mask) {
643 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
644 }
645 if (sctx->images[i].compressed_colortex_mask) {
646 si_decompress_image_color_textures(sctx, &sctx->images[i]);
647 }
648 }
649
650 si_check_render_feedback(sctx);
651 }
652
653 void si_decompress_graphics_textures(struct si_context *sctx)
654 {
655 si_decompress_textures(sctx, 0, SI_NUM_GRAPHICS_SHADERS);
656 }
657
658 void si_decompress_compute_textures(struct si_context *sctx)
659 {
660 si_decompress_textures(sctx, SI_NUM_GRAPHICS_SHADERS, SI_NUM_SHADERS);
661 }
662
663 static void si_clear(struct pipe_context *ctx, unsigned buffers,
664 const union pipe_color_union *color,
665 double depth, unsigned stencil)
666 {
667 struct si_context *sctx = (struct si_context *)ctx;
668 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
669 struct pipe_surface *zsbuf = fb->zsbuf;
670 struct r600_texture *zstex =
671 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
672
673 if (buffers & PIPE_CLEAR_COLOR) {
674 evergreen_do_fast_color_clear(&sctx->b, fb,
675 &sctx->framebuffer.atom, &buffers,
676 &sctx->framebuffer.dirty_cbufs,
677 color);
678 if (!buffers)
679 return; /* all buffers have been fast cleared */
680 }
681
682 if (buffers & PIPE_CLEAR_COLOR) {
683 int i;
684
685 /* These buffers cannot use fast clear, make sure to disable expansion. */
686 for (i = 0; i < fb->nr_cbufs; i++) {
687 struct r600_texture *tex;
688
689 /* If not clearing this buffer, skip. */
690 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
691 continue;
692
693 if (!fb->cbufs[i])
694 continue;
695
696 tex = (struct r600_texture *)fb->cbufs[i]->texture;
697 if (tex->fmask.size == 0)
698 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
699 }
700 }
701
702 if (zstex && zstex->htile_buffer &&
703 zsbuf->u.tex.level == 0 &&
704 zsbuf->u.tex.first_layer == 0 &&
705 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
706 if (buffers & PIPE_CLEAR_DEPTH) {
707 /* Need to disable EXPCLEAR temporarily if clearing
708 * to a new value. */
709 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
710 sctx->db_depth_disable_expclear = true;
711 }
712
713 zstex->depth_clear_value = depth;
714 sctx->framebuffer.dirty_zsbuf = true;
715 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
716 sctx->db_depth_clear = true;
717 si_mark_atom_dirty(sctx, &sctx->db_render_state);
718 }
719
720 if (buffers & PIPE_CLEAR_STENCIL) {
721 stencil &= 0xff;
722
723 /* Need to disable EXPCLEAR temporarily if clearing
724 * to a new value. */
725 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
726 sctx->db_stencil_disable_expclear = true;
727 }
728
729 zstex->stencil_clear_value = stencil;
730 sctx->framebuffer.dirty_zsbuf = true;
731 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
732 sctx->db_stencil_clear = true;
733 si_mark_atom_dirty(sctx, &sctx->db_render_state);
734 }
735 }
736
737 si_blitter_begin(ctx, SI_CLEAR);
738 util_blitter_clear(sctx->blitter, fb->width, fb->height,
739 util_framebuffer_get_num_layers(fb),
740 buffers, color, depth, stencil);
741 si_blitter_end(ctx);
742
743 if (sctx->db_depth_clear) {
744 sctx->db_depth_clear = false;
745 sctx->db_depth_disable_expclear = false;
746 zstex->depth_cleared = true;
747 si_mark_atom_dirty(sctx, &sctx->db_render_state);
748 }
749
750 if (sctx->db_stencil_clear) {
751 sctx->db_stencil_clear = false;
752 sctx->db_stencil_disable_expclear = false;
753 zstex->stencil_cleared = true;
754 si_mark_atom_dirty(sctx, &sctx->db_render_state);
755 }
756 }
757
758 static void si_clear_render_target(struct pipe_context *ctx,
759 struct pipe_surface *dst,
760 const union pipe_color_union *color,
761 unsigned dstx, unsigned dsty,
762 unsigned width, unsigned height,
763 bool render_condition_enabled)
764 {
765 struct si_context *sctx = (struct si_context *)ctx;
766
767 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
768 util_blitter_clear_render_target(sctx->blitter, dst, color,
769 dstx, dsty, width, height);
770 si_blitter_end(ctx);
771 }
772
773 static void si_clear_depth_stencil(struct pipe_context *ctx,
774 struct pipe_surface *dst,
775 unsigned clear_flags,
776 double depth,
777 unsigned stencil,
778 unsigned dstx, unsigned dsty,
779 unsigned width, unsigned height,
780 bool render_condition_enabled)
781 {
782 struct si_context *sctx = (struct si_context *)ctx;
783
784 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
785 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
786 dstx, dsty, width, height);
787 si_blitter_end(ctx);
788 }
789
790 /* Helper for decompressing a portion of a color or depth resource before
791 * blitting if any decompression is needed.
792 * The driver doesn't decompress resources automatically while u_blitter is
793 * rendering. */
794 static void si_decompress_subresource(struct pipe_context *ctx,
795 struct pipe_resource *tex,
796 unsigned planes, unsigned level,
797 unsigned first_layer, unsigned last_layer)
798 {
799 struct si_context *sctx = (struct si_context *)ctx;
800 struct r600_texture *rtex = (struct r600_texture*)tex;
801
802 if (rtex->db_compatible) {
803 planes &= PIPE_MASK_Z | PIPE_MASK_S;
804
805 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
806 planes &= ~PIPE_MASK_S;
807
808 si_flush_depth_texture(sctx, rtex, planes,
809 level, level,
810 first_layer, last_layer);
811 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
812 si_blit_decompress_color(ctx, rtex, level, level,
813 first_layer, last_layer, false);
814 }
815 }
816
817 struct texture_orig_info {
818 unsigned format;
819 unsigned width0;
820 unsigned height0;
821 unsigned npix_x;
822 unsigned npix_y;
823 unsigned npix0_x;
824 unsigned npix0_y;
825 };
826
827 void si_resource_copy_region(struct pipe_context *ctx,
828 struct pipe_resource *dst,
829 unsigned dst_level,
830 unsigned dstx, unsigned dsty, unsigned dstz,
831 struct pipe_resource *src,
832 unsigned src_level,
833 const struct pipe_box *src_box)
834 {
835 struct si_context *sctx = (struct si_context *)ctx;
836 struct pipe_surface *dst_view, dst_templ;
837 struct pipe_sampler_view src_templ, *src_view;
838 unsigned dst_width, dst_height, src_width0, src_height0;
839 unsigned src_force_level = 0;
840 struct pipe_box sbox, dstbox;
841
842 /* Handle buffers first. */
843 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
844 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
845 return;
846 }
847
848 assert(u_max_sample(dst) == u_max_sample(src));
849
850 /* The driver doesn't decompress resources automatically while
851 * u_blitter is rendering. */
852 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
853 src_box->z, src_box->z + src_box->depth - 1);
854
855 dst_width = u_minify(dst->width0, dst_level);
856 dst_height = u_minify(dst->height0, dst_level);
857 src_width0 = src->width0;
858 src_height0 = src->height0;
859
860 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
861 util_blitter_default_src_texture(&src_templ, src, src_level);
862
863 if (util_format_is_compressed(src->format) ||
864 util_format_is_compressed(dst->format)) {
865 unsigned blocksize = util_format_get_blocksize(src->format);
866
867 if (blocksize == 8)
868 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
869 else
870 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
871 dst_templ.format = src_templ.format;
872
873 dst_width = util_format_get_nblocksx(dst->format, dst_width);
874 dst_height = util_format_get_nblocksy(dst->format, dst_height);
875 src_width0 = util_format_get_nblocksx(src->format, src_width0);
876 src_height0 = util_format_get_nblocksy(src->format, src_height0);
877
878 dstx = util_format_get_nblocksx(dst->format, dstx);
879 dsty = util_format_get_nblocksy(dst->format, dsty);
880
881 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
882 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
883 sbox.z = src_box->z;
884 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
885 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
886 sbox.depth = src_box->depth;
887 src_box = &sbox;
888
889 src_force_level = src_level;
890 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src) ||
891 /* also *8_SNORM has precision issues, use UNORM instead */
892 util_format_is_snorm8(src->format)) {
893 if (util_format_is_subsampled_422(src->format)) {
894 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
895 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
896
897 dst_width = util_format_get_nblocksx(dst->format, dst_width);
898 src_width0 = util_format_get_nblocksx(src->format, src_width0);
899
900 dstx = util_format_get_nblocksx(dst->format, dstx);
901
902 sbox = *src_box;
903 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
904 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
905 src_box = &sbox;
906 } else {
907 unsigned blocksize = util_format_get_blocksize(src->format);
908
909 switch (blocksize) {
910 case 1:
911 dst_templ.format = PIPE_FORMAT_R8_UNORM;
912 src_templ.format = PIPE_FORMAT_R8_UNORM;
913 break;
914 case 2:
915 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
916 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
917 break;
918 case 4:
919 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
920 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
921 break;
922 case 8:
923 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
924 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
925 break;
926 case 16:
927 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
928 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
929 break;
930 default:
931 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
932 util_format_short_name(src->format), blocksize);
933 assert(0);
934 }
935 }
936 }
937
938 /* Initialize the surface. */
939 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
940 dst_width, dst_height);
941
942 /* Initialize the sampler view. */
943 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
944 src_width0, src_height0,
945 src_force_level);
946
947 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
948 abs(src_box->depth), &dstbox);
949
950 /* Copy. */
951 si_blitter_begin(ctx, SI_COPY);
952 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
953 src_view, src_box, src_width0, src_height0,
954 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
955 false);
956 si_blitter_end(ctx);
957
958 pipe_surface_reference(&dst_view, NULL);
959 pipe_sampler_view_reference(&src_view, NULL);
960 }
961
962 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
963 const struct pipe_blit_info *info)
964 {
965 struct si_context *sctx = (struct si_context*)ctx;
966 struct r600_texture *src = (struct r600_texture*)info->src.resource;
967 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
968 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
969 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
970 enum pipe_format format = info->src.format;
971 unsigned sample_mask = ~0;
972 struct pipe_resource *tmp, templ;
973 struct pipe_blit_info blit;
974
975 /* Check basic requirements for hw resolve. */
976 if (!(info->src.resource->nr_samples > 1 &&
977 info->dst.resource->nr_samples <= 1 &&
978 !util_format_is_pure_integer(format) &&
979 !util_format_is_depth_or_stencil(format) &&
980 util_max_layer(info->src.resource, 0) == 0))
981 return false;
982
983 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
984 * the format is R16G16. Use R16A16, which does work.
985 */
986 if (format == PIPE_FORMAT_R16G16_UNORM)
987 format = PIPE_FORMAT_R16A16_UNORM;
988 if (format == PIPE_FORMAT_R16G16_SNORM)
989 format = PIPE_FORMAT_R16A16_SNORM;
990
991 /* Check the remaining requirements for hw resolve. */
992 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
993 !info->scissor_enable &&
994 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
995 util_is_format_compatible(util_format_description(info->src.format),
996 util_format_description(info->dst.format)) &&
997 dst_width == info->src.resource->width0 &&
998 dst_height == info->src.resource->height0 &&
999 info->dst.box.x == 0 &&
1000 info->dst.box.y == 0 &&
1001 info->dst.box.width == dst_width &&
1002 info->dst.box.height == dst_height &&
1003 info->dst.box.depth == 1 &&
1004 info->src.box.x == 0 &&
1005 info->src.box.y == 0 &&
1006 info->src.box.width == dst_width &&
1007 info->src.box.height == dst_height &&
1008 info->src.box.depth == 1 &&
1009 dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
1010 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1011 /* Check the last constraint. */
1012 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1013 /* The next fast clear will switch to this mode to
1014 * get direct hw resolve next time if the mode is
1015 * different now.
1016 */
1017 src->last_msaa_resolve_target_micro_mode =
1018 dst->surface.micro_tile_mode;
1019 goto resolve_to_temp;
1020 }
1021
1022 /* Resolving into a surface with DCC is unsupported. Since
1023 * it's being overwritten anyway, clear it to uncompressed.
1024 * This is still the fastest codepath even with this clear.
1025 */
1026 if (dst->dcc_offset &&
1027 dst->surface.level[info->dst.level].dcc_enabled) {
1028 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1029 0xFFFFFFFF);
1030 dst->dirty_level_mask &= ~(1 << info->dst.level);
1031 }
1032
1033 /* Resolve directly from src to dst. */
1034 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1035 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1036 util_blitter_custom_resolve_color(sctx->blitter,
1037 info->dst.resource, info->dst.level,
1038 info->dst.box.z,
1039 info->src.resource, info->src.box.z,
1040 sample_mask, sctx->custom_blend_resolve,
1041 format);
1042 si_blitter_end(ctx);
1043 return true;
1044 }
1045
1046 resolve_to_temp:
1047 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1048 * a temporary texture and blit.
1049 */
1050 memset(&templ, 0, sizeof(templ));
1051 templ.target = PIPE_TEXTURE_2D;
1052 templ.format = info->src.resource->format;
1053 templ.width0 = info->src.resource->width0;
1054 templ.height0 = info->src.resource->height0;
1055 templ.depth0 = 1;
1056 templ.array_size = 1;
1057 templ.usage = PIPE_USAGE_DEFAULT;
1058 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1059 R600_RESOURCE_FLAG_DISABLE_DCC;
1060
1061 /* The src and dst microtile modes must be the same. */
1062 if (src->surface.micro_tile_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING)
1063 templ.bind = PIPE_BIND_SCANOUT;
1064 else
1065 templ.bind = 0;
1066
1067 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1068 if (!tmp)
1069 return false;
1070
1071 assert(src->surface.micro_tile_mode ==
1072 ((struct r600_texture*)tmp)->surface.micro_tile_mode);
1073
1074 /* resolve */
1075 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1076 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1077 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
1078 info->src.resource, info->src.box.z,
1079 sample_mask, sctx->custom_blend_resolve,
1080 format);
1081 si_blitter_end(ctx);
1082
1083 /* blit */
1084 blit = *info;
1085 blit.src.resource = tmp;
1086 blit.src.box.z = 0;
1087
1088 si_blitter_begin(ctx, SI_BLIT |
1089 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1090 util_blitter_blit(sctx->blitter, &blit);
1091 si_blitter_end(ctx);
1092
1093 pipe_resource_reference(&tmp, NULL);
1094 return true;
1095 }
1096
1097 static void si_blit(struct pipe_context *ctx,
1098 const struct pipe_blit_info *info)
1099 {
1100 struct si_context *sctx = (struct si_context*)ctx;
1101
1102 if (do_hardware_msaa_resolve(ctx, info)) {
1103 return;
1104 }
1105
1106 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1107
1108 /* The driver doesn't decompress resources automatically while
1109 * u_blitter is rendering. */
1110 si_decompress_subresource(ctx, info->src.resource, info->mask,
1111 info->src.level,
1112 info->src.box.z,
1113 info->src.box.z + info->src.box.depth - 1);
1114
1115 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1116 util_try_blit_via_copy_region(ctx, info))
1117 return;
1118
1119 si_blitter_begin(ctx, SI_BLIT |
1120 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1121 util_blitter_blit(sctx->blitter, info);
1122 si_blitter_end(ctx);
1123 }
1124
1125 static boolean si_generate_mipmap(struct pipe_context *ctx,
1126 struct pipe_resource *tex,
1127 enum pipe_format format,
1128 unsigned base_level, unsigned last_level,
1129 unsigned first_layer, unsigned last_layer)
1130 {
1131 struct si_context *sctx = (struct si_context*)ctx;
1132 struct r600_texture *rtex = (struct r600_texture *)tex;
1133
1134 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1135 return false;
1136
1137 /* The driver doesn't decompress resources automatically while
1138 * u_blitter is rendering. */
1139 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1140 base_level, first_layer, last_layer);
1141
1142 /* Clear dirty_level_mask for the levels that will be overwritten. */
1143 assert(base_level < last_level);
1144 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1145 last_level - base_level);
1146
1147 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1148 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1149 base_level, last_level,
1150 first_layer, last_layer);
1151 si_blitter_end(ctx);
1152 return true;
1153 }
1154
1155 static void si_flush_resource(struct pipe_context *ctx,
1156 struct pipe_resource *res)
1157 {
1158 struct r600_texture *rtex = (struct r600_texture*)res;
1159
1160 assert(res->target != PIPE_BUFFER);
1161 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1162
1163 /* st/dri calls flush twice per frame (not a bug), this prevents double
1164 * decompression. */
1165 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1166 return;
1167
1168 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1169 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1170 0, util_max_layer(res, 0),
1171 rtex->dcc_separate_buffer != NULL);
1172 }
1173
1174 /* Always do the analysis even if DCC is disabled at the moment. */
1175 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1176 rtex->separate_dcc_dirty = false;
1177 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1178 }
1179 }
1180
1181 static void si_decompress_dcc(struct pipe_context *ctx,
1182 struct r600_texture *rtex)
1183 {
1184 if (!rtex->dcc_offset)
1185 return;
1186
1187 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1188 0, util_max_layer(&rtex->resource.b.b, 0),
1189 true);
1190 }
1191
1192 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1193 struct pipe_resource *dst,
1194 unsigned offset, unsigned size,
1195 const void *clear_value_ptr,
1196 int clear_value_size)
1197 {
1198 struct si_context *sctx = (struct si_context*)ctx;
1199 uint32_t dword_value;
1200 unsigned i;
1201
1202 assert(offset % clear_value_size == 0);
1203 assert(size % clear_value_size == 0);
1204
1205 if (clear_value_size > 4) {
1206 const uint32_t *u32 = clear_value_ptr;
1207 bool clear_dword_duplicated = true;
1208
1209 /* See if we can lower large fills to dword fills. */
1210 for (i = 1; i < clear_value_size / 4; i++)
1211 if (u32[0] != u32[i]) {
1212 clear_dword_duplicated = false;
1213 break;
1214 }
1215
1216 if (!clear_dword_duplicated) {
1217 /* Use transform feedback for 64-bit, 96-bit, and
1218 * 128-bit fills.
1219 */
1220 union pipe_color_union clear_value;
1221
1222 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1223 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1224 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1225 size, clear_value_size / 4,
1226 &clear_value);
1227 si_blitter_end(ctx);
1228 return;
1229 }
1230 }
1231
1232 /* Expand the clear value to a dword. */
1233 switch (clear_value_size) {
1234 case 1:
1235 dword_value = *(uint8_t*)clear_value_ptr;
1236 dword_value |= (dword_value << 8) |
1237 (dword_value << 16) |
1238 (dword_value << 24);
1239 break;
1240 case 2:
1241 dword_value = *(uint16_t*)clear_value_ptr;
1242 dword_value |= dword_value << 16;
1243 break;
1244 default:
1245 dword_value = *(uint32_t*)clear_value_ptr;
1246 }
1247
1248 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1249 R600_COHERENCY_SHADER);
1250 }
1251
1252 void si_init_blit_functions(struct si_context *sctx)
1253 {
1254 sctx->b.b.clear = si_clear;
1255 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1256 sctx->b.b.clear_render_target = si_clear_render_target;
1257 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1258 sctx->b.b.resource_copy_region = si_resource_copy_region;
1259 sctx->b.b.blit = si_blit;
1260 sctx->b.b.flush_resource = si_flush_resource;
1261 sctx->b.b.generate_mipmap = si_generate_mipmap;
1262 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1263 sctx->b.decompress_dcc = si_decompress_dcc;
1264 }