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radeonsi/gfx10: move s_sendmsg gs_alloc_req to the beginning of shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_compute.h"
28 #include "util/format/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
34 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
35
36 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
37 SI_SAVE_FRAGMENT_STATE,
38
39 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
40 SI_DISABLE_RENDER_COND,
41
42 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
43 };
44
45 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op)
46 {
47 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
48 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
49 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
50 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
51 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
52 (struct pipe_stream_output_target**)sctx->streamout.targets);
53 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
54
55 if (op & SI_SAVE_FRAGMENT_STATE) {
56 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
57 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
58 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
59 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
60 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask);
61 util_blitter_save_scissor(sctx->blitter, &sctx->scissors[0]);
62 util_blitter_save_window_rectangles(sctx->blitter,
63 sctx->window_rectangles_include,
64 sctx->num_window_rectangles,
65 sctx->window_rectangles);
66 }
67
68 if (op & SI_SAVE_FRAMEBUFFER)
69 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
70
71 if (op & SI_SAVE_TEXTURES) {
72 util_blitter_save_fragment_sampler_states(
73 sctx->blitter, 2,
74 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
75
76 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
77 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
78 }
79
80 if (op & SI_DISABLE_RENDER_COND)
81 sctx->render_cond_force_off = true;
82
83 if (sctx->screen->dpbb_allowed) {
84 sctx->dpbb_force_off = true;
85 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
86 }
87 }
88
89 void si_blitter_end(struct si_context *sctx)
90 {
91 if (sctx->screen->dpbb_allowed) {
92 sctx->dpbb_force_off = false;
93 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
94 }
95
96 sctx->render_cond_force_off = false;
97
98 /* Restore shader pointers because the VS blit shader changed all
99 * non-global VS user SGPRs. */
100 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
101 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
102 sctx->vertex_buffer_user_sgprs_dirty = sctx->num_vertex_elements > 0;
103 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
104 }
105
106 static unsigned u_max_sample(struct pipe_resource *r)
107 {
108 return r->nr_samples ? r->nr_samples - 1 : 0;
109 }
110
111 static unsigned
112 si_blit_dbcb_copy(struct si_context *sctx,
113 struct si_texture *src,
114 struct si_texture *dst,
115 unsigned planes, unsigned level_mask,
116 unsigned first_layer, unsigned last_layer,
117 unsigned first_sample, unsigned last_sample)
118 {
119 struct pipe_surface surf_tmpl = {{0}};
120 unsigned layer, sample, checked_last_layer, max_layer;
121 unsigned fully_copied_levels = 0;
122
123 if (planes & PIPE_MASK_Z)
124 sctx->dbcb_depth_copy_enabled = true;
125 if (planes & PIPE_MASK_S)
126 sctx->dbcb_stencil_copy_enabled = true;
127 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
128
129 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
130
131 sctx->decompression_enabled = true;
132
133 while (level_mask) {
134 unsigned level = u_bit_scan(&level_mask);
135
136 /* The smaller the mipmap level, the less layers there are
137 * as far as 3D textures are concerned. */
138 max_layer = util_max_layer(&src->buffer.b.b, level);
139 checked_last_layer = MIN2(last_layer, max_layer);
140
141 surf_tmpl.u.tex.level = level;
142
143 for (layer = first_layer; layer <= checked_last_layer; layer++) {
144 struct pipe_surface *zsurf, *cbsurf;
145
146 surf_tmpl.format = src->buffer.b.b.format;
147 surf_tmpl.u.tex.first_layer = layer;
148 surf_tmpl.u.tex.last_layer = layer;
149
150 zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl);
151
152 surf_tmpl.format = dst->buffer.b.b.format;
153 cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl);
154
155 for (sample = first_sample; sample <= last_sample; sample++) {
156 if (sample != sctx->dbcb_copy_sample) {
157 sctx->dbcb_copy_sample = sample;
158 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
159 }
160
161 si_blitter_begin(sctx, SI_DECOMPRESS);
162 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
163 sctx->custom_dsa_flush, 1.0f);
164 si_blitter_end(sctx);
165 }
166
167 pipe_surface_reference(&zsurf, NULL);
168 pipe_surface_reference(&cbsurf, NULL);
169 }
170
171 if (first_layer == 0 && last_layer >= max_layer &&
172 first_sample == 0 && last_sample >= u_max_sample(&src->buffer.b.b))
173 fully_copied_levels |= 1u << level;
174 }
175
176 sctx->decompression_enabled = false;
177 sctx->dbcb_depth_copy_enabled = false;
178 sctx->dbcb_stencil_copy_enabled = false;
179 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
180
181 return fully_copied_levels;
182 }
183
184 /* Helper function for si_blit_decompress_zs_in_place.
185 */
186 static void
187 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
188 struct si_texture *texture,
189 unsigned planes, unsigned level_mask,
190 unsigned first_layer, unsigned last_layer)
191 {
192 struct pipe_surface *zsurf, surf_tmpl = {{0}};
193 unsigned layer, max_layer, checked_last_layer;
194 unsigned fully_decompressed_mask = 0;
195
196 if (!level_mask)
197 return;
198
199 if (planes & PIPE_MASK_S)
200 sctx->db_flush_stencil_inplace = true;
201 if (planes & PIPE_MASK_Z)
202 sctx->db_flush_depth_inplace = true;
203 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
204
205 surf_tmpl.format = texture->buffer.b.b.format;
206
207 sctx->decompression_enabled = true;
208
209 while (level_mask) {
210 unsigned level = u_bit_scan(&level_mask);
211
212 surf_tmpl.u.tex.level = level;
213
214 /* The smaller the mipmap level, the less layers there are
215 * as far as 3D textures are concerned. */
216 max_layer = util_max_layer(&texture->buffer.b.b, level);
217 checked_last_layer = MIN2(last_layer, max_layer);
218
219 for (layer = first_layer; layer <= checked_last_layer; layer++) {
220 surf_tmpl.u.tex.first_layer = layer;
221 surf_tmpl.u.tex.last_layer = layer;
222
223 zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl);
224
225 si_blitter_begin(sctx, SI_DECOMPRESS);
226 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
227 sctx->custom_dsa_flush,
228 1.0f);
229 si_blitter_end(sctx);
230
231 pipe_surface_reference(&zsurf, NULL);
232 }
233
234 /* The texture will always be dirty if some layers aren't flushed.
235 * I don't think this case occurs often though. */
236 if (first_layer == 0 && last_layer >= max_layer) {
237 fully_decompressed_mask |= 1u << level;
238 }
239 }
240
241 if (planes & PIPE_MASK_Z)
242 texture->dirty_level_mask &= ~fully_decompressed_mask;
243 if (planes & PIPE_MASK_S)
244 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
245
246 sctx->decompression_enabled = false;
247 sctx->db_flush_depth_inplace = false;
248 sctx->db_flush_stencil_inplace = false;
249 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
250 }
251
252 /* Helper function of si_flush_depth_texture: decompress the given levels
253 * of Z and/or S planes in place.
254 */
255 static void
256 si_blit_decompress_zs_in_place(struct si_context *sctx,
257 struct si_texture *texture,
258 unsigned levels_z, unsigned levels_s,
259 unsigned first_layer, unsigned last_layer)
260 {
261 unsigned both = levels_z & levels_s;
262
263 /* First, do combined Z & S decompresses for levels that need it. */
264 if (both) {
265 si_blit_decompress_zs_planes_in_place(
266 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
267 both,
268 first_layer, last_layer);
269 levels_z &= ~both;
270 levels_s &= ~both;
271 }
272
273 /* Now do separate Z and S decompresses. */
274 if (levels_z) {
275 si_blit_decompress_zs_planes_in_place(
276 sctx, texture, PIPE_MASK_Z,
277 levels_z,
278 first_layer, last_layer);
279 }
280
281 if (levels_s) {
282 si_blit_decompress_zs_planes_in_place(
283 sctx, texture, PIPE_MASK_S,
284 levels_s,
285 first_layer, last_layer);
286 }
287 }
288
289 static void
290 si_decompress_depth(struct si_context *sctx,
291 struct si_texture *tex,
292 unsigned required_planes,
293 unsigned first_level, unsigned last_level,
294 unsigned first_layer, unsigned last_layer)
295 {
296 unsigned inplace_planes = 0;
297 unsigned copy_planes = 0;
298 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
299 unsigned levels_z = 0;
300 unsigned levels_s = 0;
301
302 if (required_planes & PIPE_MASK_Z) {
303 levels_z = level_mask & tex->dirty_level_mask;
304
305 if (levels_z) {
306 if (si_can_sample_zs(tex, false))
307 inplace_planes |= PIPE_MASK_Z;
308 else
309 copy_planes |= PIPE_MASK_Z;
310 }
311 }
312 if (required_planes & PIPE_MASK_S) {
313 levels_s = level_mask & tex->stencil_dirty_level_mask;
314
315 if (levels_s) {
316 if (si_can_sample_zs(tex, true))
317 inplace_planes |= PIPE_MASK_S;
318 else
319 copy_planes |= PIPE_MASK_S;
320 }
321 }
322
323 if (unlikely(sctx->log))
324 u_log_printf(sctx->log,
325 "\n------------------------------------------------\n"
326 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
327 first_level, last_level, levels_z, levels_s);
328
329 /* We may have to allocate the flushed texture here when called from
330 * si_decompress_subresource.
331 */
332 if (copy_planes &&
333 (tex->flushed_depth_texture ||
334 si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b))) {
335 struct si_texture *dst = tex->flushed_depth_texture;
336 unsigned fully_copied_levels;
337 unsigned levels = 0;
338
339 assert(tex->flushed_depth_texture);
340
341 if (util_format_is_depth_and_stencil(dst->buffer.b.b.format))
342 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
343
344 if (copy_planes & PIPE_MASK_Z) {
345 levels |= levels_z;
346 levels_z = 0;
347 }
348 if (copy_planes & PIPE_MASK_S) {
349 levels |= levels_s;
350 levels_s = 0;
351 }
352
353 fully_copied_levels = si_blit_dbcb_copy(
354 sctx, tex, dst, copy_planes, levels,
355 first_layer, last_layer,
356 0, u_max_sample(&tex->buffer.b.b));
357
358 if (copy_planes & PIPE_MASK_Z)
359 tex->dirty_level_mask &= ~fully_copied_levels;
360 if (copy_planes & PIPE_MASK_S)
361 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
362 }
363
364 if (inplace_planes) {
365 bool has_htile = si_htile_enabled(tex, first_level, inplace_planes);
366 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level,
367 inplace_planes);
368
369 /* Don't decompress if there is no HTILE or when HTILE is
370 * TC-compatible. */
371 if (has_htile && !tc_compat_htile) {
372 si_blit_decompress_zs_in_place(
373 sctx, tex,
374 levels_z, levels_s,
375 first_layer, last_layer);
376 } else {
377 /* This is only a cache flush.
378 *
379 * Only clear the mask that we are flushing, because
380 * si_make_DB_shader_coherent() treats different levels
381 * and depth and stencil differently.
382 */
383 if (inplace_planes & PIPE_MASK_Z)
384 tex->dirty_level_mask &= ~levels_z;
385 if (inplace_planes & PIPE_MASK_S)
386 tex->stencil_dirty_level_mask &= ~levels_s;
387 }
388
389 /* Only in-place decompression needs to flush DB caches, or
390 * when we don't decompress but TC-compatible planes are dirty.
391 */
392 si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
393 inplace_planes & PIPE_MASK_S,
394 tc_compat_htile);
395 }
396 /* set_framebuffer_state takes care of coherency for single-sample.
397 * The DB->CB copy uses CB for the final writes.
398 */
399 if (copy_planes && tex->buffer.b.b.nr_samples > 1)
400 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
401 false, true /* no DCC */);
402 }
403
404 static void
405 si_decompress_sampler_depth_textures(struct si_context *sctx,
406 struct si_samplers *textures)
407 {
408 unsigned i;
409 unsigned mask = textures->needs_depth_decompress_mask;
410
411 while (mask) {
412 struct pipe_sampler_view *view;
413 struct si_sampler_view *sview;
414 struct si_texture *tex;
415
416 i = u_bit_scan(&mask);
417
418 view = textures->views[i];
419 assert(view);
420 sview = (struct si_sampler_view*)view;
421
422 tex = (struct si_texture *)view->texture;
423 assert(tex->db_compatible);
424
425 si_decompress_depth(sctx, tex,
426 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
427 view->u.tex.first_level, view->u.tex.last_level,
428 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
429 }
430 }
431
432 static void si_blit_decompress_color(struct si_context *sctx,
433 struct si_texture *tex,
434 unsigned first_level, unsigned last_level,
435 unsigned first_layer, unsigned last_layer,
436 bool need_dcc_decompress,
437 bool need_fmask_expand)
438 {
439 void* custom_blend;
440 unsigned layer, checked_last_layer, max_layer;
441 unsigned level_mask =
442 u_bit_consecutive(first_level, last_level - first_level + 1);
443
444 if (!need_dcc_decompress)
445 level_mask &= tex->dirty_level_mask;
446 if (!level_mask)
447 goto expand_fmask;
448
449 if (unlikely(sctx->log))
450 u_log_printf(sctx->log,
451 "\n------------------------------------------------\n"
452 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
453 first_level, last_level, level_mask);
454
455 if (need_dcc_decompress) {
456 custom_blend = sctx->custom_blend_dcc_decompress;
457
458 assert(tex->surface.dcc_offset);
459
460 /* disable levels without DCC */
461 for (int i = first_level; i <= last_level; i++) {
462 if (!vi_dcc_enabled(tex, i))
463 level_mask &= ~(1 << i);
464 }
465 } else if (tex->surface.fmask_size) {
466 custom_blend = sctx->custom_blend_fmask_decompress;
467 } else {
468 custom_blend = sctx->custom_blend_eliminate_fastclear;
469 }
470
471 sctx->decompression_enabled = true;
472
473 while (level_mask) {
474 unsigned level = u_bit_scan(&level_mask);
475
476 /* The smaller the mipmap level, the less layers there are
477 * as far as 3D textures are concerned. */
478 max_layer = util_max_layer(&tex->buffer.b.b, level);
479 checked_last_layer = MIN2(last_layer, max_layer);
480
481 for (layer = first_layer; layer <= checked_last_layer; layer++) {
482 struct pipe_surface *cbsurf, surf_tmpl;
483
484 surf_tmpl.format = tex->buffer.b.b.format;
485 surf_tmpl.u.tex.level = level;
486 surf_tmpl.u.tex.first_layer = layer;
487 surf_tmpl.u.tex.last_layer = layer;
488 cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl);
489
490 /* Required before and after FMASK and DCC_DECOMPRESS. */
491 if (custom_blend == sctx->custom_blend_fmask_decompress ||
492 custom_blend == sctx->custom_blend_dcc_decompress)
493 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
494
495 si_blitter_begin(sctx, SI_DECOMPRESS);
496 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
497 si_blitter_end(sctx);
498
499 if (custom_blend == sctx->custom_blend_fmask_decompress ||
500 custom_blend == sctx->custom_blend_dcc_decompress)
501 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
502
503 pipe_surface_reference(&cbsurf, NULL);
504 }
505
506 /* The texture will always be dirty if some layers aren't flushed.
507 * I don't think this case occurs often though. */
508 if (first_layer == 0 && last_layer >= max_layer) {
509 tex->dirty_level_mask &= ~(1 << level);
510 }
511 }
512
513 sctx->decompression_enabled = false;
514 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
515 vi_dcc_enabled(tex, first_level),
516 tex->surface.u.gfx9.dcc.pipe_aligned);
517
518 expand_fmask:
519 if (need_fmask_expand && tex->surface.fmask_offset && !tex->fmask_is_identity) {
520 si_compute_expand_fmask(&sctx->b, &tex->buffer.b.b);
521 tex->fmask_is_identity = true;
522 }
523 }
524
525 static void
526 si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
527 unsigned first_level, unsigned last_level,
528 bool need_fmask_expand)
529 {
530 /* CMASK or DCC can be discarded and we can still end up here. */
531 if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->surface.dcc_offset)
532 return;
533
534 si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
535 util_max_layer(&tex->buffer.b.b, first_level),
536 false, need_fmask_expand);
537 }
538
539 static void
540 si_decompress_sampler_color_textures(struct si_context *sctx,
541 struct si_samplers *textures)
542 {
543 unsigned i;
544 unsigned mask = textures->needs_color_decompress_mask;
545
546 while (mask) {
547 struct pipe_sampler_view *view;
548 struct si_texture *tex;
549
550 i = u_bit_scan(&mask);
551
552 view = textures->views[i];
553 assert(view);
554
555 tex = (struct si_texture *)view->texture;
556
557 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
558 view->u.tex.last_level, false);
559 }
560 }
561
562 static void
563 si_decompress_image_color_textures(struct si_context *sctx,
564 struct si_images *images)
565 {
566 unsigned i;
567 unsigned mask = images->needs_color_decompress_mask;
568
569 while (mask) {
570 const struct pipe_image_view *view;
571 struct si_texture *tex;
572
573 i = u_bit_scan(&mask);
574
575 view = &images->views[i];
576 assert(view->resource->target != PIPE_BUFFER);
577
578 tex = (struct si_texture *)view->resource;
579
580 si_decompress_color_texture(sctx, tex, view->u.tex.level,
581 view->u.tex.level,
582 view->access & PIPE_IMAGE_ACCESS_WRITE);
583 }
584 }
585
586 static void si_check_render_feedback_texture(struct si_context *sctx,
587 struct si_texture *tex,
588 unsigned first_level,
589 unsigned last_level,
590 unsigned first_layer,
591 unsigned last_layer)
592 {
593 bool render_feedback = false;
594
595 if (!tex->surface.dcc_offset)
596 return;
597
598 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
599 struct si_surface * surf;
600
601 if (!sctx->framebuffer.state.cbufs[j])
602 continue;
603
604 surf = (struct si_surface*)sctx->framebuffer.state.cbufs[j];
605
606 if (tex == (struct si_texture *)surf->base.texture &&
607 surf->base.u.tex.level >= first_level &&
608 surf->base.u.tex.level <= last_level &&
609 surf->base.u.tex.first_layer <= last_layer &&
610 surf->base.u.tex.last_layer >= first_layer) {
611 render_feedback = true;
612 break;
613 }
614 }
615
616 if (render_feedback)
617 si_texture_disable_dcc(sctx, tex);
618 }
619
620 static void si_check_render_feedback_textures(struct si_context *sctx,
621 struct si_samplers *textures)
622 {
623 uint32_t mask = textures->enabled_mask;
624
625 while (mask) {
626 const struct pipe_sampler_view *view;
627 struct si_texture *tex;
628
629 unsigned i = u_bit_scan(&mask);
630
631 view = textures->views[i];
632 if(view->texture->target == PIPE_BUFFER)
633 continue;
634
635 tex = (struct si_texture *)view->texture;
636
637 si_check_render_feedback_texture(sctx, tex,
638 view->u.tex.first_level,
639 view->u.tex.last_level,
640 view->u.tex.first_layer,
641 view->u.tex.last_layer);
642 }
643 }
644
645 static void si_check_render_feedback_images(struct si_context *sctx,
646 struct si_images *images)
647 {
648 uint32_t mask = images->enabled_mask;
649
650 while (mask) {
651 const struct pipe_image_view *view;
652 struct si_texture *tex;
653
654 unsigned i = u_bit_scan(&mask);
655
656 view = &images->views[i];
657 if (view->resource->target == PIPE_BUFFER)
658 continue;
659
660 tex = (struct si_texture *)view->resource;
661
662 si_check_render_feedback_texture(sctx, tex,
663 view->u.tex.level,
664 view->u.tex.level,
665 view->u.tex.first_layer,
666 view->u.tex.last_layer);
667 }
668 }
669
670 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
671 {
672 util_dynarray_foreach(&sctx->resident_tex_handles,
673 struct si_texture_handle *, tex_handle) {
674 struct pipe_sampler_view *view;
675 struct si_texture *tex;
676
677 view = (*tex_handle)->view;
678 if (view->texture->target == PIPE_BUFFER)
679 continue;
680
681 tex = (struct si_texture *)view->texture;
682
683 si_check_render_feedback_texture(sctx, tex,
684 view->u.tex.first_level,
685 view->u.tex.last_level,
686 view->u.tex.first_layer,
687 view->u.tex.last_layer);
688 }
689 }
690
691 static void si_check_render_feedback_resident_images(struct si_context *sctx)
692 {
693 util_dynarray_foreach(&sctx->resident_img_handles,
694 struct si_image_handle *, img_handle) {
695 struct pipe_image_view *view;
696 struct si_texture *tex;
697
698 view = &(*img_handle)->view;
699 if (view->resource->target == PIPE_BUFFER)
700 continue;
701
702 tex = (struct si_texture *)view->resource;
703
704 si_check_render_feedback_texture(sctx, tex,
705 view->u.tex.level,
706 view->u.tex.level,
707 view->u.tex.first_layer,
708 view->u.tex.last_layer);
709 }
710 }
711
712 static void si_check_render_feedback(struct si_context *sctx)
713 {
714 if (!sctx->need_check_render_feedback)
715 return;
716
717 /* There is no render feedback if color writes are disabled.
718 * (e.g. a pixel shader with image stores)
719 */
720 if (!si_get_total_colormask(sctx))
721 return;
722
723 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
724 si_check_render_feedback_images(sctx, &sctx->images[i]);
725 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
726 }
727
728 si_check_render_feedback_resident_images(sctx);
729 si_check_render_feedback_resident_textures(sctx);
730
731 sctx->need_check_render_feedback = false;
732 }
733
734 static void si_decompress_resident_textures(struct si_context *sctx)
735 {
736 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
737 struct si_texture_handle *, tex_handle) {
738 struct pipe_sampler_view *view = (*tex_handle)->view;
739 struct si_texture *tex = (struct si_texture *)view->texture;
740
741 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
742 view->u.tex.last_level, false);
743 }
744
745 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
746 struct si_texture_handle *, tex_handle) {
747 struct pipe_sampler_view *view = (*tex_handle)->view;
748 struct si_sampler_view *sview = (struct si_sampler_view *)view;
749 struct si_texture *tex = (struct si_texture *)view->texture;
750
751 si_decompress_depth(sctx, tex,
752 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
753 view->u.tex.first_level, view->u.tex.last_level,
754 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
755 }
756 }
757
758 static void si_decompress_resident_images(struct si_context *sctx)
759 {
760 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
761 struct si_image_handle *, img_handle) {
762 struct pipe_image_view *view = &(*img_handle)->view;
763 struct si_texture *tex = (struct si_texture *)view->resource;
764
765 si_decompress_color_texture(sctx, tex, view->u.tex.level,
766 view->u.tex.level,
767 view->access & PIPE_IMAGE_ACCESS_WRITE);
768 }
769 }
770
771 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
772 {
773 unsigned compressed_colortex_counter, mask;
774
775 if (sctx->blitter->running)
776 return;
777
778 /* Update the compressed_colortex_mask if necessary. */
779 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
780 if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) {
781 sctx->last_compressed_colortex_counter = compressed_colortex_counter;
782 si_update_needs_color_decompress_masks(sctx);
783 }
784
785 /* Decompress color & depth textures if needed. */
786 mask = sctx->shader_needs_decompress_mask & shader_mask;
787 while (mask) {
788 unsigned i = u_bit_scan(&mask);
789
790 if (sctx->samplers[i].needs_depth_decompress_mask) {
791 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
792 }
793 if (sctx->samplers[i].needs_color_decompress_mask) {
794 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
795 }
796 if (sctx->images[i].needs_color_decompress_mask) {
797 si_decompress_image_color_textures(sctx, &sctx->images[i]);
798 }
799 }
800
801 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
802 if (sctx->uses_bindless_samplers)
803 si_decompress_resident_textures(sctx);
804 if (sctx->uses_bindless_images)
805 si_decompress_resident_images(sctx);
806
807 if (sctx->ps_uses_fbfetch) {
808 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
809 si_decompress_color_texture(sctx,
810 (struct si_texture*)cb0->texture,
811 cb0->u.tex.first_layer,
812 cb0->u.tex.last_layer, false);
813 }
814
815 si_check_render_feedback(sctx);
816 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
817 if (sctx->cs_shader_state.program->sel.info.uses_bindless_samplers)
818 si_decompress_resident_textures(sctx);
819 if (sctx->cs_shader_state.program->sel.info.uses_bindless_images)
820 si_decompress_resident_images(sctx);
821 }
822 }
823
824 /* Helper for decompressing a portion of a color or depth resource before
825 * blitting if any decompression is needed.
826 * The driver doesn't decompress resources automatically while u_blitter is
827 * rendering. */
828 void si_decompress_subresource(struct pipe_context *ctx,
829 struct pipe_resource *tex,
830 unsigned planes, unsigned level,
831 unsigned first_layer, unsigned last_layer)
832 {
833 struct si_context *sctx = (struct si_context *)ctx;
834 struct si_texture *stex = (struct si_texture*)tex;
835
836 if (stex->db_compatible) {
837 planes &= PIPE_MASK_Z | PIPE_MASK_S;
838
839 if (!stex->surface.has_stencil)
840 planes &= ~PIPE_MASK_S;
841
842 /* If we've rendered into the framebuffer and it's a blitting
843 * source, make sure the decompression pass is invoked
844 * by dirtying the framebuffer.
845 */
846 if (sctx->framebuffer.state.zsbuf &&
847 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
848 sctx->framebuffer.state.zsbuf->texture == tex)
849 si_update_fb_dirtiness_after_rendering(sctx);
850
851 si_decompress_depth(sctx, stex, planes,
852 level, level,
853 first_layer, last_layer);
854 } else if (stex->surface.fmask_size || stex->cmask_buffer || stex->surface.dcc_offset) {
855 /* If we've rendered into the framebuffer and it's a blitting
856 * source, make sure the decompression pass is invoked
857 * by dirtying the framebuffer.
858 */
859 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
860 if (sctx->framebuffer.state.cbufs[i] &&
861 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
862 sctx->framebuffer.state.cbufs[i]->texture == tex) {
863 si_update_fb_dirtiness_after_rendering(sctx);
864 break;
865 }
866 }
867
868 si_blit_decompress_color(sctx, stex, level, level,
869 first_layer, last_layer, false, false);
870 }
871 }
872
873 struct texture_orig_info {
874 unsigned format;
875 unsigned width0;
876 unsigned height0;
877 unsigned npix_x;
878 unsigned npix_y;
879 unsigned npix0_x;
880 unsigned npix0_y;
881 };
882
883 void si_resource_copy_region(struct pipe_context *ctx,
884 struct pipe_resource *dst,
885 unsigned dst_level,
886 unsigned dstx, unsigned dsty, unsigned dstz,
887 struct pipe_resource *src,
888 unsigned src_level,
889 const struct pipe_box *src_box)
890 {
891 struct si_context *sctx = (struct si_context *)ctx;
892 struct si_texture *ssrc = (struct si_texture*)src;
893 struct si_texture *sdst = (struct si_texture*)dst;
894 struct pipe_surface *dst_view, dst_templ;
895 struct pipe_sampler_view src_templ, *src_view;
896 unsigned dst_width, dst_height, src_width0, src_height0;
897 unsigned dst_width0, dst_height0, src_force_level = 0;
898 struct pipe_box sbox, dstbox;
899
900 /* Handle buffers first. */
901 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
902 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
903 return;
904 }
905
906 if (!util_format_is_compressed(src->format) &&
907 !util_format_is_compressed(dst->format) &&
908 !util_format_is_depth_or_stencil(src->format) &&
909 src->nr_samples <= 1 &&
910 !sdst->surface.dcc_offset &&
911 !(dst->target != src->target &&
912 (src->target == PIPE_TEXTURE_1D_ARRAY || dst->target == PIPE_TEXTURE_1D_ARRAY))) {
913 si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz, src_box);
914 return;
915 }
916
917 assert(u_max_sample(dst) == u_max_sample(src));
918
919 /* The driver doesn't decompress resources automatically while
920 * u_blitter is rendering. */
921 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
922 src_box->z, src_box->z + src_box->depth - 1);
923
924 dst_width = u_minify(dst->width0, dst_level);
925 dst_height = u_minify(dst->height0, dst_level);
926 dst_width0 = dst->width0;
927 dst_height0 = dst->height0;
928 src_width0 = src->width0;
929 src_height0 = src->height0;
930
931 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
932 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
933
934 if (util_format_is_compressed(src->format) ||
935 util_format_is_compressed(dst->format)) {
936 unsigned blocksize = ssrc->surface.bpe;
937
938 if (blocksize == 8)
939 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
940 else
941 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
942 dst_templ.format = src_templ.format;
943
944 dst_width = util_format_get_nblocksx(dst->format, dst_width);
945 dst_height = util_format_get_nblocksy(dst->format, dst_height);
946 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
947 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
948 src_width0 = util_format_get_nblocksx(src->format, src_width0);
949 src_height0 = util_format_get_nblocksy(src->format, src_height0);
950
951 dstx = util_format_get_nblocksx(dst->format, dstx);
952 dsty = util_format_get_nblocksy(dst->format, dsty);
953
954 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
955 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
956 sbox.z = src_box->z;
957 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
958 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
959 sbox.depth = src_box->depth;
960 src_box = &sbox;
961
962 src_force_level = src_level;
963 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
964 if (util_format_is_subsampled_422(src->format)) {
965 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
966 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
967
968 dst_width = util_format_get_nblocksx(dst->format, dst_width);
969 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
970 src_width0 = util_format_get_nblocksx(src->format, src_width0);
971
972 dstx = util_format_get_nblocksx(dst->format, dstx);
973
974 sbox = *src_box;
975 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
976 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
977 src_box = &sbox;
978 } else {
979 unsigned blocksize = ssrc->surface.bpe;
980
981 switch (blocksize) {
982 case 1:
983 dst_templ.format = PIPE_FORMAT_R8_UNORM;
984 src_templ.format = PIPE_FORMAT_R8_UNORM;
985 break;
986 case 2:
987 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
988 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
989 break;
990 case 4:
991 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
992 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
993 break;
994 case 8:
995 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
996 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
997 break;
998 case 16:
999 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1000 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1001 break;
1002 default:
1003 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1004 util_format_short_name(src->format), blocksize);
1005 assert(0);
1006 }
1007 }
1008 }
1009
1010 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1011 * equivalent instead, which doesn't force DCC decompression.
1012 * Note that some chips avoid this issue by using SDMA.
1013 */
1014 if (util_format_is_snorm8(dst_templ.format)) {
1015 dst_templ.format = src_templ.format =
1016 util_format_snorm8_to_sint8(dst_templ.format);
1017 }
1018
1019 vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level,
1020 dst_templ.format);
1021 vi_disable_dcc_if_incompatible_format(sctx, src, src_level,
1022 src_templ.format);
1023
1024 /* Initialize the surface. */
1025 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1026 dst_width0, dst_height0,
1027 dst_width, dst_height);
1028
1029 /* Initialize the sampler view. */
1030 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1031 src_width0, src_height0,
1032 src_force_level);
1033
1034 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1035 abs(src_box->depth), &dstbox);
1036
1037 /* Copy. */
1038 si_blitter_begin(sctx, SI_COPY);
1039 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1040 src_view, src_box, src_width0, src_height0,
1041 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1042 false);
1043 si_blitter_end(sctx);
1044
1045 pipe_surface_reference(&dst_view, NULL);
1046 pipe_sampler_view_reference(&src_view, NULL);
1047 }
1048
1049 static void si_do_CB_resolve(struct si_context *sctx,
1050 const struct pipe_blit_info *info,
1051 struct pipe_resource *dst,
1052 unsigned dst_level, unsigned dst_z,
1053 enum pipe_format format)
1054 {
1055 /* Required before and after CB_RESOLVE. */
1056 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1057
1058 si_blitter_begin(sctx, SI_COLOR_RESOLVE |
1059 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1060 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1061 info->src.resource, info->src.box.z,
1062 ~0, sctx->custom_blend_resolve,
1063 format);
1064 si_blitter_end(sctx);
1065
1066 /* Flush caches for possible texturing. */
1067 si_make_CB_shader_coherent(sctx, 1, false, true /* no DCC */);
1068 }
1069
1070 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1071 const struct pipe_blit_info *info)
1072 {
1073 struct si_context *sctx = (struct si_context*)ctx;
1074 struct si_texture *src = (struct si_texture*)info->src.resource;
1075 struct si_texture *dst = (struct si_texture*)info->dst.resource;
1076 ASSERTED struct si_texture *stmp;
1077 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1078 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1079 enum pipe_format format = info->src.format;
1080 struct pipe_resource *tmp, templ;
1081 struct pipe_blit_info blit;
1082
1083 /* Check basic requirements for hw resolve. */
1084 if (!(info->src.resource->nr_samples > 1 &&
1085 info->dst.resource->nr_samples <= 1 &&
1086 !util_format_is_pure_integer(format) &&
1087 !util_format_is_depth_or_stencil(format) &&
1088 util_max_layer(info->src.resource, 0) == 0))
1089 return false;
1090
1091 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1092 * the format is R16G16. Use R16A16, which does work.
1093 */
1094 if (format == PIPE_FORMAT_R16G16_UNORM)
1095 format = PIPE_FORMAT_R16A16_UNORM;
1096 if (format == PIPE_FORMAT_R16G16_SNORM)
1097 format = PIPE_FORMAT_R16A16_SNORM;
1098
1099 /* Check the remaining requirements for hw resolve. */
1100 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1101 !info->scissor_enable &&
1102 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1103 util_is_format_compatible(util_format_description(info->src.format),
1104 util_format_description(info->dst.format)) &&
1105 dst_width == info->src.resource->width0 &&
1106 dst_height == info->src.resource->height0 &&
1107 info->dst.box.x == 0 &&
1108 info->dst.box.y == 0 &&
1109 info->dst.box.width == dst_width &&
1110 info->dst.box.height == dst_height &&
1111 info->dst.box.depth == 1 &&
1112 info->src.box.x == 0 &&
1113 info->src.box.y == 0 &&
1114 info->src.box.width == dst_width &&
1115 info->src.box.height == dst_height &&
1116 info->src.box.depth == 1 &&
1117 !dst->surface.is_linear &&
1118 (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1119 /* Check the last constraint. */
1120 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1121 /* The next fast clear will switch to this mode to
1122 * get direct hw resolve next time if the mode is
1123 * different now.
1124 *
1125 * TODO-GFX10: This does not work in GFX10 because MSAA
1126 * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes.
1127 * In some cases we could change the swizzle of the
1128 * destination texture instead, but the more general
1129 * solution is to implement compute shader resolve.
1130 */
1131 src->last_msaa_resolve_target_micro_mode =
1132 dst->surface.micro_tile_mode;
1133 goto resolve_to_temp;
1134 }
1135
1136 /* Resolving into a surface with DCC is unsupported. Since
1137 * it's being overwritten anyway, clear it to uncompressed.
1138 * This is still the fastest codepath even with this clear.
1139 */
1140 if (vi_dcc_enabled(dst, info->dst.level)) {
1141 if (!vi_dcc_clear_level(sctx, dst, info->dst.level,
1142 DCC_UNCOMPRESSED))
1143 goto resolve_to_temp;
1144
1145 dst->dirty_level_mask &= ~(1 << info->dst.level);
1146 }
1147
1148 /* Resolve directly from src to dst. */
1149 si_do_CB_resolve(sctx, info, info->dst.resource,
1150 info->dst.level, info->dst.box.z, format);
1151 return true;
1152 }
1153
1154 resolve_to_temp:
1155 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1156 * a temporary texture and blit.
1157 */
1158 memset(&templ, 0, sizeof(templ));
1159 templ.target = PIPE_TEXTURE_2D;
1160 templ.format = info->src.resource->format;
1161 templ.width0 = info->src.resource->width0;
1162 templ.height0 = info->src.resource->height0;
1163 templ.depth0 = 1;
1164 templ.array_size = 1;
1165 templ.usage = PIPE_USAGE_DEFAULT;
1166 templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING |
1167 SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE |
1168 SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(src->surface.micro_tile_mode) |
1169 SI_RESOURCE_FLAG_DISABLE_DCC;
1170
1171 /* The src and dst microtile modes must be the same. */
1172 if (sctx->chip_class <= GFX8 &&
1173 src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1174 templ.bind = PIPE_BIND_SCANOUT;
1175 else
1176 templ.bind = 0;
1177
1178 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1179 if (!tmp)
1180 return false;
1181 stmp = (struct si_texture*)tmp;
1182
1183 assert(!stmp->surface.is_linear);
1184 assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode);
1185
1186 /* resolve */
1187 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1188
1189 /* blit */
1190 blit = *info;
1191 blit.src.resource = tmp;
1192 blit.src.box.z = 0;
1193
1194 si_blitter_begin(sctx, SI_BLIT |
1195 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1196 util_blitter_blit(sctx->blitter, &blit);
1197 si_blitter_end(sctx);
1198
1199 pipe_resource_reference(&tmp, NULL);
1200 return true;
1201 }
1202
1203 static void si_blit(struct pipe_context *ctx,
1204 const struct pipe_blit_info *info)
1205 {
1206 struct si_context *sctx = (struct si_context*)ctx;
1207 struct si_texture *dst = (struct si_texture *)info->dst.resource;
1208
1209 if (do_hardware_msaa_resolve(ctx, info)) {
1210 return;
1211 }
1212
1213 /* Using SDMA for copying to a linear texture in GTT is much faster.
1214 * This improves DRI PRIME performance.
1215 *
1216 * resource_copy_region can't do this yet, because dma_copy calls it
1217 * on failure (recursion).
1218 */
1219 if (dst->surface.is_linear &&
1220 util_can_blit_via_copy_region(info, false)) {
1221 sctx->dma_copy(ctx, info->dst.resource, info->dst.level,
1222 info->dst.box.x, info->dst.box.y,
1223 info->dst.box.z,
1224 info->src.resource, info->src.level,
1225 &info->src.box);
1226 return;
1227 }
1228
1229 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1230
1231 /* The driver doesn't decompress resources automatically while
1232 * u_blitter is rendering. */
1233 vi_disable_dcc_if_incompatible_format(sctx, info->src.resource,
1234 info->src.level,
1235 info->src.format);
1236 vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource,
1237 info->dst.level,
1238 info->dst.format);
1239 si_decompress_subresource(ctx, info->src.resource, PIPE_MASK_RGBAZS,
1240 info->src.level,
1241 info->src.box.z,
1242 info->src.box.z + info->src.box.depth - 1);
1243
1244 if (sctx->screen->debug_flags & DBG(FORCE_SDMA) &&
1245 util_try_blit_via_copy_region(ctx, info))
1246 return;
1247
1248 si_blitter_begin(sctx, SI_BLIT |
1249 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1250 util_blitter_blit(sctx->blitter, info);
1251 si_blitter_end(sctx);
1252 }
1253
1254 static bool si_generate_mipmap(struct pipe_context *ctx,
1255 struct pipe_resource *tex,
1256 enum pipe_format format,
1257 unsigned base_level, unsigned last_level,
1258 unsigned first_layer, unsigned last_layer)
1259 {
1260 struct si_context *sctx = (struct si_context*)ctx;
1261 struct si_texture *stex = (struct si_texture *)tex;
1262
1263 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1264 return false;
1265
1266 /* The driver doesn't decompress resources automatically while
1267 * u_blitter is rendering. */
1268 vi_disable_dcc_if_incompatible_format(sctx, tex, base_level,
1269 format);
1270 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1271 base_level, first_layer, last_layer);
1272
1273 /* Clear dirty_level_mask for the levels that will be overwritten. */
1274 assert(base_level < last_level);
1275 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1276 last_level - base_level);
1277
1278 sctx->generate_mipmap_for_depth = stex->is_depth;
1279
1280 si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1281 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1282 base_level, last_level,
1283 first_layer, last_layer);
1284 si_blitter_end(sctx);
1285
1286 sctx->generate_mipmap_for_depth = false;
1287 return true;
1288 }
1289
1290 static void si_flush_resource(struct pipe_context *ctx,
1291 struct pipe_resource *res)
1292 {
1293 struct si_context *sctx = (struct si_context*)ctx;
1294 struct si_texture *tex = (struct si_texture*)res;
1295
1296 assert(res->target != PIPE_BUFFER);
1297 assert(!tex->dcc_separate_buffer || tex->dcc_gather_statistics);
1298
1299 /* st/dri calls flush twice per frame (not a bug), this prevents double
1300 * decompression. */
1301 if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
1302 return;
1303
1304 if (!tex->is_depth && (tex->cmask_buffer || tex->surface.dcc_offset)) {
1305 si_blit_decompress_color(sctx, tex, 0, res->last_level,
1306 0, util_max_layer(res, 0),
1307 tex->dcc_separate_buffer != NULL, false);
1308
1309 if (tex->surface.display_dcc_offset && tex->displayable_dcc_dirty) {
1310 si_retile_dcc(sctx, tex);
1311 tex->displayable_dcc_dirty = false;
1312 }
1313 }
1314
1315 /* Always do the analysis even if DCC is disabled at the moment. */
1316 if (tex->dcc_gather_statistics) {
1317 bool separate_dcc_dirty = tex->separate_dcc_dirty;
1318
1319 /* If the color buffer hasn't been unbound and fast clear hasn't
1320 * been used, separate_dcc_dirty is false, but there may have been
1321 * new rendering. Check if the color buffer is bound and assume
1322 * it's dirty.
1323 *
1324 * Note that DRI2 never unbinds window colorbuffers, which means
1325 * the DCC pipeline statistics query would never be re-set and would
1326 * keep adding new results until all free memory is exhausted if we
1327 * didn't do this.
1328 */
1329 if (!separate_dcc_dirty) {
1330 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
1331 if (sctx->framebuffer.state.cbufs[i] &&
1332 sctx->framebuffer.state.cbufs[i]->texture == res) {
1333 separate_dcc_dirty = true;
1334 break;
1335 }
1336 }
1337 }
1338
1339 if (separate_dcc_dirty) {
1340 tex->separate_dcc_dirty = false;
1341 vi_separate_dcc_process_and_reset_stats(ctx, tex);
1342 }
1343 }
1344 }
1345
1346 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
1347 {
1348 /* If graphics is disabled, we can't decompress DCC, but it shouldn't
1349 * be compressed either. The caller should simply discard it.
1350 */
1351 if (!tex->surface.dcc_offset || !sctx->has_graphics)
1352 return;
1353
1354 si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level,
1355 0, util_max_layer(&tex->buffer.b.b, 0),
1356 true, false);
1357 }
1358
1359 void si_init_blit_functions(struct si_context *sctx)
1360 {
1361 sctx->b.resource_copy_region = si_resource_copy_region;
1362
1363 if (sctx->has_graphics) {
1364 sctx->b.blit = si_blit;
1365 sctx->b.flush_resource = si_flush_resource;
1366 sctx->b.generate_mipmap = si_generate_mipmap;
1367 }
1368 }