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gallium/u_blitter: use 2D_ARRAY for cubemap blits if possible
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "util/u_format.h"
26 #include "util/u_surface.h"
27
28 enum si_blitter_op /* bitmask */
29 {
30 SI_SAVE_TEXTURES = 1,
31 SI_SAVE_FRAMEBUFFER = 2,
32 SI_SAVE_FRAGMENT_STATE = 4,
33 SI_DISABLE_RENDER_COND = 8,
34
35 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
36
37 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
38
39 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
40 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
41
42 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
43 SI_SAVE_FRAGMENT_STATE,
44
45 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
46 SI_DISABLE_RENDER_COND,
47
48 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
49 };
50
51 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
52 {
53 struct si_context *sctx = (struct si_context *)ctx;
54
55 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
56 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
57 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
58 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
59 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
60 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
61 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
62 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
63 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
64
65 if (op & SI_SAVE_FRAGMENT_STATE) {
66 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
67 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
68 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
69 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
70 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
71 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
72 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
73 }
74
75 if (op & SI_SAVE_FRAMEBUFFER)
76 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
77
78 if (op & SI_SAVE_TEXTURES) {
79 util_blitter_save_fragment_sampler_states(
80 sctx->blitter, 2,
81 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
82
83 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
84 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
85 }
86
87 if (op & SI_DISABLE_RENDER_COND)
88 sctx->b.render_cond_force_off = true;
89 }
90
91 static void si_blitter_end(struct pipe_context *ctx)
92 {
93 struct si_context *sctx = (struct si_context *)ctx;
94
95 sctx->b.render_cond_force_off = false;
96 }
97
98 static unsigned u_max_sample(struct pipe_resource *r)
99 {
100 return r->nr_samples ? r->nr_samples - 1 : 0;
101 }
102
103 static unsigned
104 si_blit_dbcb_copy(struct si_context *sctx,
105 struct r600_texture *src,
106 struct r600_texture *dst,
107 unsigned planes, unsigned level_mask,
108 unsigned first_layer, unsigned last_layer,
109 unsigned first_sample, unsigned last_sample)
110 {
111 struct pipe_surface surf_tmpl = {{0}};
112 unsigned layer, sample, checked_last_layer, max_layer;
113 unsigned fully_copied_levels = 0;
114
115 if (planes & PIPE_MASK_Z)
116 sctx->dbcb_depth_copy_enabled = true;
117 if (planes & PIPE_MASK_S)
118 sctx->dbcb_stencil_copy_enabled = true;
119 si_mark_atom_dirty(sctx, &sctx->db_render_state);
120
121 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
122
123 while (level_mask) {
124 unsigned level = u_bit_scan(&level_mask);
125
126 /* The smaller the mipmap level, the less layers there are
127 * as far as 3D textures are concerned. */
128 max_layer = util_max_layer(&src->resource.b.b, level);
129 checked_last_layer = MIN2(last_layer, max_layer);
130
131 surf_tmpl.u.tex.level = level;
132
133 for (layer = first_layer; layer <= checked_last_layer; layer++) {
134 struct pipe_surface *zsurf, *cbsurf;
135
136 surf_tmpl.format = src->resource.b.b.format;
137 surf_tmpl.u.tex.first_layer = layer;
138 surf_tmpl.u.tex.last_layer = layer;
139
140 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
141
142 surf_tmpl.format = dst->resource.b.b.format;
143 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
144
145 for (sample = first_sample; sample <= last_sample; sample++) {
146 if (sample != sctx->dbcb_copy_sample) {
147 sctx->dbcb_copy_sample = sample;
148 si_mark_atom_dirty(sctx, &sctx->db_render_state);
149 }
150
151 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
152 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
153 sctx->custom_dsa_flush, 1.0f);
154 si_blitter_end(&sctx->b.b);
155 }
156
157 pipe_surface_reference(&zsurf, NULL);
158 pipe_surface_reference(&cbsurf, NULL);
159 }
160
161 if (first_layer == 0 && last_layer >= max_layer &&
162 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
163 fully_copied_levels |= 1u << level;
164 }
165
166 sctx->dbcb_depth_copy_enabled = false;
167 sctx->dbcb_stencil_copy_enabled = false;
168 si_mark_atom_dirty(sctx, &sctx->db_render_state);
169
170 return fully_copied_levels;
171 }
172
173 static void si_blit_decompress_depth(struct pipe_context *ctx,
174 struct r600_texture *texture,
175 struct r600_texture *staging,
176 unsigned first_level, unsigned last_level,
177 unsigned first_layer, unsigned last_layer,
178 unsigned first_sample, unsigned last_sample)
179 {
180 const struct util_format_description *desc;
181 unsigned planes = 0;
182
183 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
184
185 desc = util_format_description(staging->resource.b.b.format);
186
187 if (util_format_has_depth(desc))
188 planes |= PIPE_MASK_Z;
189 if (util_format_has_stencil(desc))
190 planes |= PIPE_MASK_S;
191
192 si_blit_dbcb_copy(
193 (struct si_context *)ctx, texture, staging, planes,
194 u_bit_consecutive(first_level, last_level - first_level + 1),
195 first_layer, last_layer, first_sample, last_sample);
196 }
197
198 /* Helper function for si_blit_decompress_zs_in_place.
199 */
200 static void
201 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
202 struct r600_texture *texture,
203 unsigned planes, unsigned level_mask,
204 unsigned first_layer, unsigned last_layer)
205 {
206 struct pipe_surface *zsurf, surf_tmpl = {{0}};
207 unsigned layer, max_layer, checked_last_layer;
208 unsigned fully_decompressed_mask = 0;
209
210 if (!level_mask)
211 return;
212
213 if (planes & PIPE_MASK_S)
214 sctx->db_flush_stencil_inplace = true;
215 if (planes & PIPE_MASK_Z)
216 sctx->db_flush_depth_inplace = true;
217 si_mark_atom_dirty(sctx, &sctx->db_render_state);
218
219 surf_tmpl.format = texture->resource.b.b.format;
220
221 while (level_mask) {
222 unsigned level = u_bit_scan(&level_mask);
223
224 surf_tmpl.u.tex.level = level;
225
226 /* The smaller the mipmap level, the less layers there are
227 * as far as 3D textures are concerned. */
228 max_layer = util_max_layer(&texture->resource.b.b, level);
229 checked_last_layer = MIN2(last_layer, max_layer);
230
231 for (layer = first_layer; layer <= checked_last_layer; layer++) {
232 surf_tmpl.u.tex.first_layer = layer;
233 surf_tmpl.u.tex.last_layer = layer;
234
235 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
236
237 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
238 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
239 sctx->custom_dsa_flush,
240 1.0f);
241 si_blitter_end(&sctx->b.b);
242
243 pipe_surface_reference(&zsurf, NULL);
244 }
245
246 /* The texture will always be dirty if some layers aren't flushed.
247 * I don't think this case occurs often though. */
248 if (first_layer == 0 && last_layer >= max_layer) {
249 fully_decompressed_mask |= 1u << level;
250 }
251 }
252
253 if (planes & PIPE_MASK_Z)
254 texture->dirty_level_mask &= ~fully_decompressed_mask;
255 if (planes & PIPE_MASK_S)
256 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
257
258 sctx->db_flush_depth_inplace = false;
259 sctx->db_flush_stencil_inplace = false;
260 si_mark_atom_dirty(sctx, &sctx->db_render_state);
261 }
262
263 /* Helper function of si_flush_depth_texture: decompress the given levels
264 * of Z and/or S planes in place.
265 */
266 static void
267 si_blit_decompress_zs_in_place(struct si_context *sctx,
268 struct r600_texture *texture,
269 unsigned levels_z, unsigned levels_s,
270 unsigned first_layer, unsigned last_layer)
271 {
272 unsigned both = levels_z & levels_s;
273
274 /* First, do combined Z & S decompresses for levels that need it. */
275 if (both) {
276 si_blit_decompress_zs_planes_in_place(
277 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
278 both,
279 first_layer, last_layer);
280 levels_z &= ~both;
281 levels_s &= ~both;
282 }
283
284 /* Now do separate Z and S decompresses. */
285 if (levels_z) {
286 si_blit_decompress_zs_planes_in_place(
287 sctx, texture, PIPE_MASK_Z,
288 levels_z,
289 first_layer, last_layer);
290 }
291
292 if (levels_s) {
293 si_blit_decompress_zs_planes_in_place(
294 sctx, texture, PIPE_MASK_S,
295 levels_s,
296 first_layer, last_layer);
297 }
298 }
299
300 static void
301 si_flush_depth_texture(struct si_context *sctx,
302 struct r600_texture *tex,
303 unsigned required_planes,
304 unsigned first_level, unsigned last_level,
305 unsigned first_layer, unsigned last_layer)
306 {
307 unsigned inplace_planes = 0;
308 unsigned copy_planes = 0;
309 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
310 unsigned levels_z = 0;
311 unsigned levels_s = 0;
312
313 if (required_planes & PIPE_MASK_Z) {
314 levels_z = level_mask & tex->dirty_level_mask;
315
316 if (levels_z) {
317 if (r600_can_sample_zs(tex, false))
318 inplace_planes |= PIPE_MASK_Z;
319 else
320 copy_planes |= PIPE_MASK_Z;
321 }
322 }
323 if (required_planes & PIPE_MASK_S) {
324 levels_s = level_mask & tex->stencil_dirty_level_mask;
325
326 if (levels_s) {
327 if (r600_can_sample_zs(tex, true))
328 inplace_planes |= PIPE_MASK_S;
329 else
330 copy_planes |= PIPE_MASK_S;
331 }
332 }
333
334 assert(!tex->tc_compatible_htile || levels_z == 0);
335
336 /* We may have to allocate the flushed texture here when called from
337 * si_decompress_subresource.
338 */
339 if (copy_planes &&
340 (tex->flushed_depth_texture ||
341 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
342 struct r600_texture *dst = tex->flushed_depth_texture;
343 unsigned fully_copied_levels;
344 unsigned levels = 0;
345
346 assert(tex->flushed_depth_texture);
347
348 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
349 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
350
351 if (copy_planes & PIPE_MASK_Z) {
352 levels |= levels_z;
353 levels_z = 0;
354 }
355 if (copy_planes & PIPE_MASK_S) {
356 levels |= levels_s;
357 levels_s = 0;
358 }
359
360 fully_copied_levels = si_blit_dbcb_copy(
361 sctx, tex, dst, copy_planes, levels,
362 first_layer, last_layer,
363 0, u_max_sample(&tex->resource.b.b));
364
365 if (copy_planes & PIPE_MASK_Z)
366 tex->dirty_level_mask &= ~fully_copied_levels;
367 if (copy_planes & PIPE_MASK_S)
368 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
369 }
370
371 if (inplace_planes) {
372 si_blit_decompress_zs_in_place(
373 sctx, tex,
374 levels_z, levels_s,
375 first_layer, last_layer);
376 }
377 }
378
379 static void
380 si_flush_depth_textures(struct si_context *sctx,
381 struct si_textures_info *textures)
382 {
383 unsigned i;
384 unsigned mask = textures->depth_texture_mask;
385
386 while (mask) {
387 struct pipe_sampler_view *view;
388 struct si_sampler_view *sview;
389 struct r600_texture *tex;
390
391 i = u_bit_scan(&mask);
392
393 view = textures->views.views[i];
394 assert(view);
395 sview = (struct si_sampler_view*)view;
396
397 tex = (struct r600_texture *)view->texture;
398 assert(tex->db_compatible);
399
400 si_flush_depth_texture(
401 sctx, tex,
402 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
403 view->u.tex.first_level, view->u.tex.last_level,
404 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
405 }
406 }
407
408 static void si_blit_decompress_color(struct pipe_context *ctx,
409 struct r600_texture *rtex,
410 unsigned first_level, unsigned last_level,
411 unsigned first_layer, unsigned last_layer,
412 bool need_dcc_decompress)
413 {
414 struct si_context *sctx = (struct si_context *)ctx;
415 void* custom_blend;
416 unsigned layer, checked_last_layer, max_layer;
417 unsigned level_mask =
418 u_bit_consecutive(first_level, last_level - first_level + 1);
419
420 if (!need_dcc_decompress)
421 level_mask &= rtex->dirty_level_mask;
422 if (!level_mask)
423 return;
424
425 if (rtex->dcc_offset && need_dcc_decompress) {
426 custom_blend = sctx->custom_blend_dcc_decompress;
427
428 /* disable levels without DCC */
429 for (int i = first_level; i <= last_level; i++) {
430 if (!vi_dcc_enabled(rtex, i))
431 level_mask &= ~(1 << i);
432 }
433 } else if (rtex->fmask.size) {
434 custom_blend = sctx->custom_blend_decompress;
435 } else {
436 custom_blend = sctx->custom_blend_fastclear;
437 }
438
439 while (level_mask) {
440 unsigned level = u_bit_scan(&level_mask);
441
442 /* The smaller the mipmap level, the less layers there are
443 * as far as 3D textures are concerned. */
444 max_layer = util_max_layer(&rtex->resource.b.b, level);
445 checked_last_layer = MIN2(last_layer, max_layer);
446
447 for (layer = first_layer; layer <= checked_last_layer; layer++) {
448 struct pipe_surface *cbsurf, surf_tmpl;
449
450 surf_tmpl.format = rtex->resource.b.b.format;
451 surf_tmpl.u.tex.level = level;
452 surf_tmpl.u.tex.first_layer = layer;
453 surf_tmpl.u.tex.last_layer = layer;
454 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
455
456 si_blitter_begin(ctx, SI_DECOMPRESS);
457 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
458 si_blitter_end(ctx);
459
460 pipe_surface_reference(&cbsurf, NULL);
461 }
462
463 /* The texture will always be dirty if some layers aren't flushed.
464 * I don't think this case occurs often though. */
465 if (first_layer == 0 && last_layer >= max_layer) {
466 rtex->dirty_level_mask &= ~(1 << level);
467 }
468 }
469 }
470
471 static void
472 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
473 unsigned first_level, unsigned last_level)
474 {
475 /* CMASK or DCC can be discarded and we can still end up here. */
476 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
477 return;
478
479 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
480 util_max_layer(&tex->resource.b.b, first_level),
481 false);
482 }
483
484 static void
485 si_decompress_sampler_color_textures(struct si_context *sctx,
486 struct si_textures_info *textures)
487 {
488 unsigned i;
489 unsigned mask = textures->compressed_colortex_mask;
490
491 while (mask) {
492 struct pipe_sampler_view *view;
493 struct r600_texture *tex;
494
495 i = u_bit_scan(&mask);
496
497 view = textures->views.views[i];
498 assert(view);
499
500 tex = (struct r600_texture *)view->texture;
501
502 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
503 view->u.tex.last_level);
504 }
505 }
506
507 static void
508 si_decompress_image_color_textures(struct si_context *sctx,
509 struct si_images_info *images)
510 {
511 unsigned i;
512 unsigned mask = images->compressed_colortex_mask;
513
514 while (mask) {
515 const struct pipe_image_view *view;
516 struct r600_texture *tex;
517
518 i = u_bit_scan(&mask);
519
520 view = &images->views[i];
521 assert(view->resource->target != PIPE_BUFFER);
522
523 tex = (struct r600_texture *)view->resource;
524
525 si_decompress_color_texture(sctx, tex, view->u.tex.level,
526 view->u.tex.level);
527 }
528 }
529
530 static void si_check_render_feedback_texture(struct si_context *sctx,
531 struct r600_texture *tex,
532 unsigned first_level,
533 unsigned last_level,
534 unsigned first_layer,
535 unsigned last_layer)
536 {
537 bool render_feedback = false;
538
539 if (!tex->dcc_offset)
540 return;
541
542 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
543 struct r600_surface * surf;
544
545 if (!sctx->framebuffer.state.cbufs[j])
546 continue;
547
548 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
549
550 if (tex == (struct r600_texture *)surf->base.texture &&
551 surf->base.u.tex.level >= first_level &&
552 surf->base.u.tex.level <= last_level &&
553 surf->base.u.tex.first_layer <= last_layer &&
554 surf->base.u.tex.last_layer >= first_layer) {
555 render_feedback = true;
556 break;
557 }
558 }
559
560 if (render_feedback)
561 r600_texture_disable_dcc(&sctx->b, tex);
562 }
563
564 static void si_check_render_feedback_textures(struct si_context *sctx,
565 struct si_textures_info *textures)
566 {
567 uint32_t mask = textures->views.enabled_mask;
568
569 while (mask) {
570 const struct pipe_sampler_view *view;
571 struct r600_texture *tex;
572
573 unsigned i = u_bit_scan(&mask);
574
575 view = textures->views.views[i];
576 if(view->texture->target == PIPE_BUFFER)
577 continue;
578
579 tex = (struct r600_texture *)view->texture;
580
581 si_check_render_feedback_texture(sctx, tex,
582 view->u.tex.first_level,
583 view->u.tex.last_level,
584 view->u.tex.first_layer,
585 view->u.tex.last_layer);
586 }
587 }
588
589 static void si_check_render_feedback_images(struct si_context *sctx,
590 struct si_images_info *images)
591 {
592 uint32_t mask = images->enabled_mask;
593
594 while (mask) {
595 const struct pipe_image_view *view;
596 struct r600_texture *tex;
597
598 unsigned i = u_bit_scan(&mask);
599
600 view = &images->views[i];
601 if (view->resource->target == PIPE_BUFFER)
602 continue;
603
604 tex = (struct r600_texture *)view->resource;
605
606 si_check_render_feedback_texture(sctx, tex,
607 view->u.tex.level,
608 view->u.tex.level,
609 view->u.tex.first_layer,
610 view->u.tex.last_layer);
611 }
612 }
613
614 static void si_check_render_feedback(struct si_context *sctx)
615 {
616
617 if (!sctx->need_check_render_feedback)
618 return;
619
620 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
621 si_check_render_feedback_images(sctx, &sctx->images[i]);
622 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
623 }
624 sctx->need_check_render_feedback = false;
625 }
626
627 static void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
628 {
629 unsigned compressed_colortex_counter, mask;
630
631 if (sctx->blitter->running)
632 return;
633
634 /* Update the compressed_colortex_mask if necessary. */
635 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
636 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
637 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
638 si_update_compressed_colortex_masks(sctx);
639 }
640
641 /* Decompress color & depth textures if needed. */
642 mask = sctx->compressed_tex_shader_mask & shader_mask;
643 while (mask) {
644 unsigned i = u_bit_scan(&mask);
645
646 if (sctx->samplers[i].depth_texture_mask) {
647 si_flush_depth_textures(sctx, &sctx->samplers[i]);
648 }
649 if (sctx->samplers[i].compressed_colortex_mask) {
650 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
651 }
652 if (sctx->images[i].compressed_colortex_mask) {
653 si_decompress_image_color_textures(sctx, &sctx->images[i]);
654 }
655 }
656
657 si_check_render_feedback(sctx);
658 }
659
660 void si_decompress_graphics_textures(struct si_context *sctx)
661 {
662 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
663 }
664
665 void si_decompress_compute_textures(struct si_context *sctx)
666 {
667 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
668 }
669
670 static void si_clear(struct pipe_context *ctx, unsigned buffers,
671 const union pipe_color_union *color,
672 double depth, unsigned stencil)
673 {
674 struct si_context *sctx = (struct si_context *)ctx;
675 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
676 struct pipe_surface *zsbuf = fb->zsbuf;
677 struct r600_texture *zstex =
678 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
679
680 if (buffers & PIPE_CLEAR_COLOR) {
681 evergreen_do_fast_color_clear(&sctx->b, fb,
682 &sctx->framebuffer.atom, &buffers,
683 &sctx->framebuffer.dirty_cbufs,
684 color);
685 if (!buffers)
686 return; /* all buffers have been fast cleared */
687 }
688
689 if (buffers & PIPE_CLEAR_COLOR) {
690 int i;
691
692 /* These buffers cannot use fast clear, make sure to disable expansion. */
693 for (i = 0; i < fb->nr_cbufs; i++) {
694 struct r600_texture *tex;
695
696 /* If not clearing this buffer, skip. */
697 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
698 continue;
699
700 if (!fb->cbufs[i])
701 continue;
702
703 tex = (struct r600_texture *)fb->cbufs[i]->texture;
704 if (tex->fmask.size == 0)
705 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
706 }
707 }
708
709 if (zstex && zstex->htile_buffer &&
710 zsbuf->u.tex.level == 0 &&
711 zsbuf->u.tex.first_layer == 0 &&
712 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
713 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
714 if (buffers & PIPE_CLEAR_DEPTH &&
715 (!zstex->tc_compatible_htile ||
716 depth == 0 || depth == 1)) {
717 /* Need to disable EXPCLEAR temporarily if clearing
718 * to a new value. */
719 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
720 sctx->db_depth_disable_expclear = true;
721 }
722
723 zstex->depth_clear_value = depth;
724 sctx->framebuffer.dirty_zsbuf = true;
725 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
726 sctx->db_depth_clear = true;
727 si_mark_atom_dirty(sctx, &sctx->db_render_state);
728 }
729
730 /* TC-compatible HTILE only supports stencil clears to 0. */
731 if (buffers & PIPE_CLEAR_STENCIL &&
732 (!zstex->tc_compatible_htile || stencil == 0)) {
733 stencil &= 0xff;
734
735 /* Need to disable EXPCLEAR temporarily if clearing
736 * to a new value. */
737 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
738 sctx->db_stencil_disable_expclear = true;
739 }
740
741 zstex->stencil_clear_value = stencil;
742 sctx->framebuffer.dirty_zsbuf = true;
743 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
744 sctx->db_stencil_clear = true;
745 si_mark_atom_dirty(sctx, &sctx->db_render_state);
746 }
747 }
748
749 si_blitter_begin(ctx, SI_CLEAR);
750 util_blitter_clear(sctx->blitter, fb->width, fb->height,
751 util_framebuffer_get_num_layers(fb),
752 buffers, color, depth, stencil);
753 si_blitter_end(ctx);
754
755 if (sctx->db_depth_clear) {
756 sctx->db_depth_clear = false;
757 sctx->db_depth_disable_expclear = false;
758 zstex->depth_cleared = true;
759 si_mark_atom_dirty(sctx, &sctx->db_render_state);
760 }
761
762 if (sctx->db_stencil_clear) {
763 sctx->db_stencil_clear = false;
764 sctx->db_stencil_disable_expclear = false;
765 zstex->stencil_cleared = true;
766 si_mark_atom_dirty(sctx, &sctx->db_render_state);
767 }
768 }
769
770 static void si_clear_render_target(struct pipe_context *ctx,
771 struct pipe_surface *dst,
772 const union pipe_color_union *color,
773 unsigned dstx, unsigned dsty,
774 unsigned width, unsigned height,
775 bool render_condition_enabled)
776 {
777 struct si_context *sctx = (struct si_context *)ctx;
778
779 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
780 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
781 util_blitter_clear_render_target(sctx->blitter, dst, color,
782 dstx, dsty, width, height);
783 si_blitter_end(ctx);
784 }
785
786 static void si_clear_depth_stencil(struct pipe_context *ctx,
787 struct pipe_surface *dst,
788 unsigned clear_flags,
789 double depth,
790 unsigned stencil,
791 unsigned dstx, unsigned dsty,
792 unsigned width, unsigned height,
793 bool render_condition_enabled)
794 {
795 struct si_context *sctx = (struct si_context *)ctx;
796
797 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
798 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
799 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
800 dstx, dsty, width, height);
801 si_blitter_end(ctx);
802 }
803
804 /* Helper for decompressing a portion of a color or depth resource before
805 * blitting if any decompression is needed.
806 * The driver doesn't decompress resources automatically while u_blitter is
807 * rendering. */
808 static void si_decompress_subresource(struct pipe_context *ctx,
809 struct pipe_resource *tex,
810 unsigned planes, unsigned level,
811 unsigned first_layer, unsigned last_layer)
812 {
813 struct si_context *sctx = (struct si_context *)ctx;
814 struct r600_texture *rtex = (struct r600_texture*)tex;
815
816 if (rtex->db_compatible) {
817 planes &= PIPE_MASK_Z | PIPE_MASK_S;
818
819 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
820 planes &= ~PIPE_MASK_S;
821
822 si_flush_depth_texture(sctx, rtex, planes,
823 level, level,
824 first_layer, last_layer);
825 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
826 si_blit_decompress_color(ctx, rtex, level, level,
827 first_layer, last_layer, false);
828 }
829 }
830
831 struct texture_orig_info {
832 unsigned format;
833 unsigned width0;
834 unsigned height0;
835 unsigned npix_x;
836 unsigned npix_y;
837 unsigned npix0_x;
838 unsigned npix0_y;
839 };
840
841 void si_resource_copy_region(struct pipe_context *ctx,
842 struct pipe_resource *dst,
843 unsigned dst_level,
844 unsigned dstx, unsigned dsty, unsigned dstz,
845 struct pipe_resource *src,
846 unsigned src_level,
847 const struct pipe_box *src_box)
848 {
849 struct si_context *sctx = (struct si_context *)ctx;
850 struct r600_texture *rsrc = (struct r600_texture*)src;
851 struct pipe_surface *dst_view, dst_templ;
852 struct pipe_sampler_view src_templ, *src_view;
853 unsigned dst_width, dst_height, src_width0, src_height0;
854 unsigned dst_width0, dst_height0, src_force_level = 0;
855 struct pipe_box sbox, dstbox;
856
857 /* Handle buffers first. */
858 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
859 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
860 return;
861 }
862
863 assert(u_max_sample(dst) == u_max_sample(src));
864
865 /* The driver doesn't decompress resources automatically while
866 * u_blitter is rendering. */
867 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
868 src_box->z, src_box->z + src_box->depth - 1);
869
870 dst_width = u_minify(dst->width0, dst_level);
871 dst_height = u_minify(dst->height0, dst_level);
872 dst_width0 = dst->width0;
873 dst_height0 = dst->height0;
874 src_width0 = src->width0;
875 src_height0 = src->height0;
876
877 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
878 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
879
880 if (util_format_is_compressed(src->format) ||
881 util_format_is_compressed(dst->format)) {
882 unsigned blocksize = rsrc->surface.bpe;
883
884 if (blocksize == 8)
885 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
886 else
887 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
888 dst_templ.format = src_templ.format;
889
890 dst_width = util_format_get_nblocksx(dst->format, dst_width);
891 dst_height = util_format_get_nblocksy(dst->format, dst_height);
892 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
893 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
894 src_width0 = util_format_get_nblocksx(src->format, src_width0);
895 src_height0 = util_format_get_nblocksy(src->format, src_height0);
896
897 dstx = util_format_get_nblocksx(dst->format, dstx);
898 dsty = util_format_get_nblocksy(dst->format, dsty);
899
900 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
901 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
902 sbox.z = src_box->z;
903 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
904 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
905 sbox.depth = src_box->depth;
906 src_box = &sbox;
907
908 src_force_level = src_level;
909 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
910 if (util_format_is_subsampled_422(src->format)) {
911 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
912 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
913
914 dst_width = util_format_get_nblocksx(dst->format, dst_width);
915 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
916 src_width0 = util_format_get_nblocksx(src->format, src_width0);
917
918 dstx = util_format_get_nblocksx(dst->format, dstx);
919
920 sbox = *src_box;
921 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
922 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
923 src_box = &sbox;
924 } else {
925 unsigned blocksize = rsrc->surface.bpe;
926
927 switch (blocksize) {
928 case 1:
929 dst_templ.format = PIPE_FORMAT_R8_UNORM;
930 src_templ.format = PIPE_FORMAT_R8_UNORM;
931 break;
932 case 2:
933 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
934 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
935 break;
936 case 4:
937 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
938 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
939 break;
940 case 8:
941 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
942 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
943 break;
944 case 16:
945 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
946 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
947 break;
948 default:
949 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
950 util_format_short_name(src->format), blocksize);
951 assert(0);
952 }
953 }
954 }
955
956 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
957 dst_templ.format);
958 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
959 src_templ.format);
960
961 /* Initialize the surface. */
962 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
963 dst_width0, dst_height0,
964 dst_width, dst_height);
965
966 /* Initialize the sampler view. */
967 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
968 src_width0, src_height0,
969 src_force_level);
970
971 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
972 abs(src_box->depth), &dstbox);
973
974 /* Copy. */
975 si_blitter_begin(ctx, SI_COPY);
976 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
977 src_view, src_box, src_width0, src_height0,
978 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
979 false);
980 si_blitter_end(ctx);
981
982 pipe_surface_reference(&dst_view, NULL);
983 pipe_sampler_view_reference(&src_view, NULL);
984 }
985
986 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
987 const struct pipe_blit_info *info)
988 {
989 struct si_context *sctx = (struct si_context*)ctx;
990 struct r600_texture *src = (struct r600_texture*)info->src.resource;
991 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
992 MAYBE_UNUSED struct r600_texture *rtmp;
993 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
994 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
995 enum pipe_format format = info->src.format;
996 unsigned sample_mask = ~0;
997 struct pipe_resource *tmp, templ;
998 struct pipe_blit_info blit;
999
1000 /* Check basic requirements for hw resolve. */
1001 if (!(info->src.resource->nr_samples > 1 &&
1002 info->dst.resource->nr_samples <= 1 &&
1003 !util_format_is_pure_integer(format) &&
1004 !util_format_is_depth_or_stencil(format) &&
1005 util_max_layer(info->src.resource, 0) == 0))
1006 return false;
1007
1008 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1009 * the format is R16G16. Use R16A16, which does work.
1010 */
1011 if (format == PIPE_FORMAT_R16G16_UNORM)
1012 format = PIPE_FORMAT_R16A16_UNORM;
1013 if (format == PIPE_FORMAT_R16G16_SNORM)
1014 format = PIPE_FORMAT_R16A16_SNORM;
1015
1016 /* Check the remaining requirements for hw resolve. */
1017 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1018 !info->scissor_enable &&
1019 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1020 util_is_format_compatible(util_format_description(info->src.format),
1021 util_format_description(info->dst.format)) &&
1022 dst_width == info->src.resource->width0 &&
1023 dst_height == info->src.resource->height0 &&
1024 info->dst.box.x == 0 &&
1025 info->dst.box.y == 0 &&
1026 info->dst.box.width == dst_width &&
1027 info->dst.box.height == dst_height &&
1028 info->dst.box.depth == 1 &&
1029 info->src.box.x == 0 &&
1030 info->src.box.y == 0 &&
1031 info->src.box.width == dst_width &&
1032 info->src.box.height == dst_height &&
1033 info->src.box.depth == 1 &&
1034 !dst->surface.is_linear &&
1035 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1036 /* Check the last constraint. */
1037 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1038 /* The next fast clear will switch to this mode to
1039 * get direct hw resolve next time if the mode is
1040 * different now.
1041 */
1042 src->last_msaa_resolve_target_micro_mode =
1043 dst->surface.micro_tile_mode;
1044 goto resolve_to_temp;
1045 }
1046
1047 /* Resolving into a surface with DCC is unsupported. Since
1048 * it's being overwritten anyway, clear it to uncompressed.
1049 * This is still the fastest codepath even with this clear.
1050 */
1051 if (vi_dcc_enabled(dst, info->dst.level)) {
1052 /* TODO: Implement per-level DCC clears for GFX9. */
1053 if (sctx->b.chip_class >= GFX9 &&
1054 info->dst.resource->last_level != 0)
1055 goto resolve_to_temp;
1056
1057 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1058 0xFFFFFFFF);
1059 dst->dirty_level_mask &= ~(1 << info->dst.level);
1060 }
1061
1062 /* Resolve directly from src to dst. */
1063 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1064 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1065 util_blitter_custom_resolve_color(sctx->blitter,
1066 info->dst.resource, info->dst.level,
1067 info->dst.box.z,
1068 info->src.resource, info->src.box.z,
1069 sample_mask, sctx->custom_blend_resolve,
1070 format);
1071 si_blitter_end(ctx);
1072 return true;
1073 }
1074
1075 resolve_to_temp:
1076 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1077 * a temporary texture and blit.
1078 */
1079 memset(&templ, 0, sizeof(templ));
1080 templ.target = PIPE_TEXTURE_2D;
1081 templ.format = info->src.resource->format;
1082 templ.width0 = info->src.resource->width0;
1083 templ.height0 = info->src.resource->height0;
1084 templ.depth0 = 1;
1085 templ.array_size = 1;
1086 templ.usage = PIPE_USAGE_DEFAULT;
1087 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1088 R600_RESOURCE_FLAG_DISABLE_DCC;
1089
1090 /* The src and dst microtile modes must be the same. */
1091 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1092 templ.bind = PIPE_BIND_SCANOUT;
1093 else
1094 templ.bind = 0;
1095
1096 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1097 if (!tmp)
1098 return false;
1099 rtmp = (struct r600_texture*)tmp;
1100
1101 assert(!rtmp->surface.is_linear);
1102 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1103
1104 /* resolve */
1105 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1106 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1107 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
1108 info->src.resource, info->src.box.z,
1109 sample_mask, sctx->custom_blend_resolve,
1110 format);
1111 si_blitter_end(ctx);
1112
1113 /* blit */
1114 blit = *info;
1115 blit.src.resource = tmp;
1116 blit.src.box.z = 0;
1117
1118 si_blitter_begin(ctx, SI_BLIT |
1119 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1120 util_blitter_blit(sctx->blitter, &blit);
1121 si_blitter_end(ctx);
1122
1123 pipe_resource_reference(&tmp, NULL);
1124 return true;
1125 }
1126
1127 static void si_blit(struct pipe_context *ctx,
1128 const struct pipe_blit_info *info)
1129 {
1130 struct si_context *sctx = (struct si_context*)ctx;
1131 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1132
1133 if (do_hardware_msaa_resolve(ctx, info)) {
1134 return;
1135 }
1136
1137 /* Using SDMA for copying to a linear texture in GTT is much faster.
1138 * This improves DRI PRIME performance.
1139 *
1140 * resource_copy_region can't do this yet, because dma_copy calls it
1141 * on failure (recursion).
1142 */
1143 if (rdst->surface.is_linear &&
1144 sctx->b.dma_copy &&
1145 util_can_blit_via_copy_region(info, false)) {
1146 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1147 info->dst.box.x, info->dst.box.y,
1148 info->dst.box.z,
1149 info->src.resource, info->src.level,
1150 &info->src.box);
1151 return;
1152 }
1153
1154 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1155
1156 /* The driver doesn't decompress resources automatically while
1157 * u_blitter is rendering. */
1158 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1159 info->src.level,
1160 info->src.format);
1161 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1162 info->dst.level,
1163 info->dst.format);
1164 si_decompress_subresource(ctx, info->src.resource, info->mask,
1165 info->src.level,
1166 info->src.box.z,
1167 info->src.box.z + info->src.box.depth - 1);
1168
1169 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1170 util_try_blit_via_copy_region(ctx, info))
1171 return;
1172
1173 si_blitter_begin(ctx, SI_BLIT |
1174 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1175 util_blitter_blit(sctx->blitter, info);
1176 si_blitter_end(ctx);
1177 }
1178
1179 static boolean si_generate_mipmap(struct pipe_context *ctx,
1180 struct pipe_resource *tex,
1181 enum pipe_format format,
1182 unsigned base_level, unsigned last_level,
1183 unsigned first_layer, unsigned last_layer)
1184 {
1185 struct si_context *sctx = (struct si_context*)ctx;
1186 struct r600_texture *rtex = (struct r600_texture *)tex;
1187
1188 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1189 return false;
1190
1191 /* The driver doesn't decompress resources automatically while
1192 * u_blitter is rendering. */
1193 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1194 format);
1195 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1196 base_level, first_layer, last_layer);
1197
1198 /* Clear dirty_level_mask for the levels that will be overwritten. */
1199 assert(base_level < last_level);
1200 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1201 last_level - base_level);
1202
1203 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1204 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1205 base_level, last_level,
1206 first_layer, last_layer);
1207 si_blitter_end(ctx);
1208 return true;
1209 }
1210
1211 static void si_flush_resource(struct pipe_context *ctx,
1212 struct pipe_resource *res)
1213 {
1214 struct r600_texture *rtex = (struct r600_texture*)res;
1215
1216 assert(res->target != PIPE_BUFFER);
1217 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1218
1219 /* st/dri calls flush twice per frame (not a bug), this prevents double
1220 * decompression. */
1221 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1222 return;
1223
1224 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1225 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1226 0, util_max_layer(res, 0),
1227 rtex->dcc_separate_buffer != NULL);
1228 }
1229
1230 /* Always do the analysis even if DCC is disabled at the moment. */
1231 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1232 rtex->separate_dcc_dirty = false;
1233 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1234 }
1235 }
1236
1237 static void si_decompress_dcc(struct pipe_context *ctx,
1238 struct r600_texture *rtex)
1239 {
1240 if (!rtex->dcc_offset)
1241 return;
1242
1243 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1244 0, util_max_layer(&rtex->resource.b.b, 0),
1245 true);
1246 }
1247
1248 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1249 struct pipe_resource *dst,
1250 unsigned offset, unsigned size,
1251 const void *clear_value_ptr,
1252 int clear_value_size)
1253 {
1254 struct si_context *sctx = (struct si_context*)ctx;
1255 uint32_t dword_value;
1256 unsigned i;
1257
1258 assert(offset % clear_value_size == 0);
1259 assert(size % clear_value_size == 0);
1260
1261 if (clear_value_size > 4) {
1262 const uint32_t *u32 = clear_value_ptr;
1263 bool clear_dword_duplicated = true;
1264
1265 /* See if we can lower large fills to dword fills. */
1266 for (i = 1; i < clear_value_size / 4; i++)
1267 if (u32[0] != u32[i]) {
1268 clear_dword_duplicated = false;
1269 break;
1270 }
1271
1272 if (!clear_dword_duplicated) {
1273 /* Use transform feedback for 64-bit, 96-bit, and
1274 * 128-bit fills.
1275 */
1276 union pipe_color_union clear_value;
1277
1278 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1279 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1280 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1281 size, clear_value_size / 4,
1282 &clear_value);
1283 si_blitter_end(ctx);
1284 return;
1285 }
1286 }
1287
1288 /* Expand the clear value to a dword. */
1289 switch (clear_value_size) {
1290 case 1:
1291 dword_value = *(uint8_t*)clear_value_ptr;
1292 dword_value |= (dword_value << 8) |
1293 (dword_value << 16) |
1294 (dword_value << 24);
1295 break;
1296 case 2:
1297 dword_value = *(uint16_t*)clear_value_ptr;
1298 dword_value |= dword_value << 16;
1299 break;
1300 default:
1301 dword_value = *(uint32_t*)clear_value_ptr;
1302 }
1303
1304 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1305 R600_COHERENCY_SHADER);
1306 }
1307
1308 void si_init_blit_functions(struct si_context *sctx)
1309 {
1310 sctx->b.b.clear = si_clear;
1311 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1312 sctx->b.b.clear_render_target = si_clear_render_target;
1313 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1314 sctx->b.b.resource_copy_region = si_resource_copy_region;
1315 sctx->b.b.blit = si_blit;
1316 sctx->b.b.flush_resource = si_flush_resource;
1317 sctx->b.b.generate_mipmap = si_generate_mipmap;
1318 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1319 sctx->b.decompress_dcc = si_decompress_dcc;
1320 }