src/gallium/drivers/radeonsi/si_blit.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2015 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "si_compute.h"
  27 #include "si_pipe.h"
  28 #include "util/format/u_format.h"
  29 #include "util/u_log.h"
  30 #include "util/u_surface.h"
  31
  32 enum
  33 {
  34    SI_COPY =
  35       SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES | SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
  36
  37    SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES | SI_SAVE_FRAGMENT_STATE,
  38
  39    SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
  40
  41    SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
  42 };
  43
  44 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op)
  45 {
  46    util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
  47    util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
  48    util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
  49    util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
  50    util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
  51                                 (struct pipe_stream_output_target **)sctx->streamout.targets);
  52    util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
  53
  54    if (op & SI_SAVE_FRAGMENT_STATE) {
  55       util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
  56       util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
  57       util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
  58       util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
  59       util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask);
  60       util_blitter_save_scissor(sctx->blitter, &sctx->scissors[0]);
  61       util_blitter_save_window_rectangles(sctx->blitter, sctx->window_rectangles_include,
  62                                           sctx->num_window_rectangles, sctx->window_rectangles);
  63    }
  64
  65    if (op & SI_SAVE_FRAMEBUFFER)
  66       util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
  67
  68    if (op & SI_SAVE_TEXTURES) {
  69       util_blitter_save_fragment_sampler_states(
  70          sctx->blitter, 2, (void **)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
  71
  72       util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
  73                                                sctx->samplers[PIPE_SHADER_FRAGMENT].views);
  74    }
  75
  76    if (op & SI_DISABLE_RENDER_COND)
  77       sctx->render_cond_force_off = true;
  78
  79    if (sctx->screen->dpbb_allowed) {
  80       sctx->dpbb_force_off = true;
  81       si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
  82    }
  83 }
  84
  85 void si_blitter_end(struct si_context *sctx)
  86 {
  87    if (sctx->screen->dpbb_allowed) {
  88       sctx->dpbb_force_off = false;
  89       si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
  90    }
  91
  92    sctx->render_cond_force_off = false;
  93
  94    /* Restore shader pointers because the VS blit shader changed all
  95     * non-global VS user SGPRs. */
  96    sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
  97    sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
  98    sctx->vertex_buffer_user_sgprs_dirty = sctx->num_vertex_elements > 0;
  99    si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
 100 }
 101
 102 static unsigned u_max_sample(struct pipe_resource *r)
 103 {
 104    return r->nr_samples ? r->nr_samples - 1 : 0;
 105 }
 106
 107 static unsigned si_blit_dbcb_copy(struct si_context *sctx, struct si_texture *src,
 108                                   struct si_texture *dst, unsigned planes, unsigned level_mask,
 109                                   unsigned first_layer, unsigned last_layer, unsigned first_sample,
 110                                   unsigned last_sample)
 111 {
 112    struct pipe_surface surf_tmpl = {{0}};
 113    unsigned layer, sample, checked_last_layer, max_layer;
 114    unsigned fully_copied_levels = 0;
 115
 116    if (planes & PIPE_MASK_Z)
 117       sctx->dbcb_depth_copy_enabled = true;
 118    if (planes & PIPE_MASK_S)
 119       sctx->dbcb_stencil_copy_enabled = true;
 120    si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
 121
 122    assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
 123
 124    sctx->decompression_enabled = true;
 125
 126    while (level_mask) {
 127       unsigned level = u_bit_scan(&level_mask);
 128
 129       /* The smaller the mipmap level, the less layers there are
 130        * as far as 3D textures are concerned. */
 131       max_layer = util_max_layer(&src->buffer.b.b, level);
 132       checked_last_layer = MIN2(last_layer, max_layer);
 133
 134       surf_tmpl.u.tex.level = level;
 135
 136       for (layer = first_layer; layer <= checked_last_layer; layer++) {
 137          struct pipe_surface *zsurf, *cbsurf;
 138
 139          surf_tmpl.format = src->buffer.b.b.format;
 140          surf_tmpl.u.tex.first_layer = layer;
 141          surf_tmpl.u.tex.last_layer = layer;
 142
 143          zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl);
 144
 145          surf_tmpl.format = dst->buffer.b.b.format;
 146          cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl);
 147
 148          for (sample = first_sample; sample <= last_sample; sample++) {
 149             if (sample != sctx->dbcb_copy_sample) {
 150                sctx->dbcb_copy_sample = sample;
 151                si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
 152             }
 153
 154             si_blitter_begin(sctx, SI_DECOMPRESS);
 155             util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
 156                                               sctx->custom_dsa_flush, 1.0f);
 157             si_blitter_end(sctx);
 158          }
 159
 160          pipe_surface_reference(&zsurf, NULL);
 161          pipe_surface_reference(&cbsurf, NULL);
 162       }
 163
 164       if (first_layer == 0 && last_layer >= max_layer && first_sample == 0 &&
 165           last_sample >= u_max_sample(&src->buffer.b.b))
 166          fully_copied_levels |= 1u << level;
 167    }
 168
 169    sctx->decompression_enabled = false;
 170    sctx->dbcb_depth_copy_enabled = false;
 171    sctx->dbcb_stencil_copy_enabled = false;
 172    si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
 173
 174    return fully_copied_levels;
 175 }
 176
 177 /* Helper function for si_blit_decompress_zs_in_place.
 178  */
 179 static void si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
 180                                                   struct si_texture *texture, unsigned planes,
 181                                                   unsigned level_mask, unsigned first_layer,
 182                                                   unsigned last_layer)
 183 {
 184    struct pipe_surface *zsurf, surf_tmpl = {{0}};
 185    unsigned layer, max_layer, checked_last_layer;
 186    unsigned fully_decompressed_mask = 0;
 187
 188    if (!level_mask)
 189       return;
 190
 191    if (planes & PIPE_MASK_S)
 192       sctx->db_flush_stencil_inplace = true;
 193    if (planes & PIPE_MASK_Z)
 194       sctx->db_flush_depth_inplace = true;
 195    si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
 196
 197    surf_tmpl.format = texture->buffer.b.b.format;
 198
 199    sctx->decompression_enabled = true;
 200
 201    while (level_mask) {
 202       unsigned level = u_bit_scan(&level_mask);
 203
 204       surf_tmpl.u.tex.level = level;
 205
 206       /* The smaller the mipmap level, the less layers there are
 207        * as far as 3D textures are concerned. */
 208       max_layer = util_max_layer(&texture->buffer.b.b, level);
 209       checked_last_layer = MIN2(last_layer, max_layer);
 210
 211       for (layer = first_layer; layer <= checked_last_layer; layer++) {
 212          surf_tmpl.u.tex.first_layer = layer;
 213          surf_tmpl.u.tex.last_layer = layer;
 214
 215          zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl);
 216
 217          si_blitter_begin(sctx, SI_DECOMPRESS);
 218          util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0, sctx->custom_dsa_flush,
 219                                            1.0f);
 220          si_blitter_end(sctx);
 221
 222          pipe_surface_reference(&zsurf, NULL);
 223       }
 224
 225       /* The texture will always be dirty if some layers aren't flushed.
 226        * I don't think this case occurs often though. */
 227       if (first_layer == 0 && last_layer >= max_layer) {
 228          fully_decompressed_mask |= 1u << level;
 229       }
 230    }
 231
 232    if (planes & PIPE_MASK_Z)
 233       texture->dirty_level_mask &= ~fully_decompressed_mask;
 234    if (planes & PIPE_MASK_S)
 235       texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
 236
 237    sctx->decompression_enabled = false;
 238    sctx->db_flush_depth_inplace = false;
 239    sctx->db_flush_stencil_inplace = false;
 240    si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
 241 }
 242
 243 /* Helper function of si_flush_depth_texture: decompress the given levels
 244  * of Z and/or S planes in place.
 245  */
 246 static void si_blit_decompress_zs_in_place(struct si_context *sctx, struct si_texture *texture,
 247                                            unsigned levels_z, unsigned levels_s,
 248                                            unsigned first_layer, unsigned last_layer)
 249 {
 250    unsigned both = levels_z & levels_s;
 251
 252    /* First, do combined Z & S decompresses for levels that need it. */
 253    if (both) {
 254       si_blit_decompress_zs_planes_in_place(sctx, texture, PIPE_MASK_Z | PIPE_MASK_S, both,
 255                                             first_layer, last_layer);
 256       levels_z &= ~both;
 257       levels_s &= ~both;
 258    }
 259
 260    /* Now do separate Z and S decompresses. */
 261    if (levels_z) {
 262       si_blit_decompress_zs_planes_in_place(sctx, texture, PIPE_MASK_Z, levels_z, first_layer,
 263                                             last_layer);
 264    }
 265
 266    if (levels_s) {
 267       si_blit_decompress_zs_planes_in_place(sctx, texture, PIPE_MASK_S, levels_s, first_layer,
 268                                             last_layer);
 269    }
 270 }
 271
 272 static void si_decompress_depth(struct si_context *sctx, struct si_texture *tex,
 273                                 unsigned required_planes, unsigned first_level, unsigned last_level,
 274                                 unsigned first_layer, unsigned last_layer)
 275 {
 276    unsigned inplace_planes = 0;
 277    unsigned copy_planes = 0;
 278    unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
 279    unsigned levels_z = 0;
 280    unsigned levels_s = 0;
 281
 282    if (required_planes & PIPE_MASK_Z) {
 283       levels_z = level_mask & tex->dirty_level_mask;
 284
 285       if (levels_z) {
 286          if (si_can_sample_zs(tex, false))
 287             inplace_planes |= PIPE_MASK_Z;
 288          else
 289             copy_planes |= PIPE_MASK_Z;
 290       }
 291    }
 292    if (required_planes & PIPE_MASK_S) {
 293       levels_s = level_mask & tex->stencil_dirty_level_mask;
 294
 295       if (levels_s) {
 296          if (si_can_sample_zs(tex, true))
 297             inplace_planes |= PIPE_MASK_S;
 298          else
 299             copy_planes |= PIPE_MASK_S;
 300       }
 301    }
 302
 303    if (unlikely(sctx->log))
 304       u_log_printf(sctx->log,
 305                    "\n------------------------------------------------\n"
 306                    "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
 307                    first_level, last_level, levels_z, levels_s);
 308
 309    /* We may have to allocate the flushed texture here when called from
 310     * si_decompress_subresource.
 311     */
 312    if (copy_planes &&
 313        (tex->flushed_depth_texture || si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b))) {
 314       struct si_texture *dst = tex->flushed_depth_texture;
 315       unsigned fully_copied_levels;
 316       unsigned levels = 0;
 317
 318       assert(tex->flushed_depth_texture);
 319
 320       if (util_format_is_depth_and_stencil(dst->buffer.b.b.format))
 321          copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
 322
 323       if (copy_planes & PIPE_MASK_Z) {
 324          levels |= levels_z;
 325          levels_z = 0;
 326       }
 327       if (copy_planes & PIPE_MASK_S) {
 328          levels |= levels_s;
 329          levels_s = 0;
 330       }
 331
 332       fully_copied_levels = si_blit_dbcb_copy(sctx, tex, dst, copy_planes, levels, first_layer,
 333                                               last_layer, 0, u_max_sample(&tex->buffer.b.b));
 334
 335       if (copy_planes & PIPE_MASK_Z)
 336          tex->dirty_level_mask &= ~fully_copied_levels;
 337       if (copy_planes & PIPE_MASK_S)
 338          tex->stencil_dirty_level_mask &= ~fully_copied_levels;
 339    }
 340
 341    if (inplace_planes) {
 342       bool has_htile = si_htile_enabled(tex, first_level, inplace_planes);
 343       bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level, inplace_planes);
 344
 345       /* Don't decompress if there is no HTILE or when HTILE is
 346        * TC-compatible. */
 347       if (has_htile && !tc_compat_htile) {
 348          si_blit_decompress_zs_in_place(sctx, tex, levels_z, levels_s, first_layer, last_layer);
 349       } else {
 350          /* This is only a cache flush.
 351           *
 352           * Only clear the mask that we are flushing, because
 353           * si_make_DB_shader_coherent() treats different levels
 354           * and depth and stencil differently.
 355           */
 356          if (inplace_planes & PIPE_MASK_Z)
 357             tex->dirty_level_mask &= ~levels_z;
 358          if (inplace_planes & PIPE_MASK_S)
 359             tex->stencil_dirty_level_mask &= ~levels_s;
 360       }
 361
 362       /* We just had to completely decompress Z/S for texturing. Enable
 363        * TC-compatible HTILE on the next clear, so that the decompression
 364        * doesn't have to be done for this texture ever again.
 365        *
 366        * TC-compatible HTILE might slightly reduce Z/S performance, but
 367        * the decompression is much worse.
 368        */
 369       if (has_htile && !tc_compat_htile &&
 370           tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE)
 371          tex->enable_tc_compatible_htile_next_clear = true;
 372
 373       /* Only in-place decompression needs to flush DB caches, or
 374        * when we don't decompress but TC-compatible planes are dirty.
 375        */
 376       si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, inplace_planes & PIPE_MASK_S,
 377                                  tc_compat_htile);
 378    }
 379    /* set_framebuffer_state takes care of coherency for single-sample.
 380     * The DB->CB copy uses CB for the final writes.
 381     */
 382    if (copy_planes && tex->buffer.b.b.nr_samples > 1)
 383       si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, false, true /* no DCC */);
 384 }
 385
 386 static void si_decompress_sampler_depth_textures(struct si_context *sctx,
 387                                                  struct si_samplers *textures)
 388 {
 389    unsigned i;
 390    unsigned mask = textures->needs_depth_decompress_mask;
 391
 392    while (mask) {
 393       struct pipe_sampler_view *view;
 394       struct si_sampler_view *sview;
 395       struct si_texture *tex;
 396
 397       i = u_bit_scan(&mask);
 398
 399       view = textures->views[i];
 400       assert(view);
 401       sview = (struct si_sampler_view *)view;
 402
 403       tex = (struct si_texture *)view->texture;
 404       assert(tex->db_compatible);
 405
 406       si_decompress_depth(sctx, tex, sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
 407                           view->u.tex.first_level, view->u.tex.last_level, 0,
 408                           util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
 409    }
 410 }
 411
 412 static void si_blit_decompress_color(struct si_context *sctx, struct si_texture *tex,
 413                                      unsigned first_level, unsigned last_level,
 414                                      unsigned first_layer, unsigned last_layer,
 415                                      bool need_dcc_decompress, bool need_fmask_expand)
 416 {
 417    void *custom_blend;
 418    unsigned layer, checked_last_layer, max_layer;
 419    unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
 420
 421    if (!need_dcc_decompress)
 422       level_mask &= tex->dirty_level_mask;
 423    if (!level_mask)
 424       goto expand_fmask;
 425
 426    if (unlikely(sctx->log))
 427       u_log_printf(sctx->log,
 428                    "\n------------------------------------------------\n"
 429                    "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
 430                    first_level, last_level, level_mask);
 431
 432    if (need_dcc_decompress) {
 433       assert(sctx->chip_class == GFX8);
 434       custom_blend = sctx->custom_blend_dcc_decompress;
 435
 436       assert(vi_dcc_enabled(tex, first_level));
 437
 438       /* disable levels without DCC */
 439       for (int i = first_level; i <= last_level; i++) {
 440          if (!vi_dcc_enabled(tex, i))
 441             level_mask &= ~(1 << i);
 442       }
 443    } else if (tex->surface.fmask_size) {
 444       custom_blend = sctx->custom_blend_fmask_decompress;
 445    } else {
 446       custom_blend = sctx->custom_blend_eliminate_fastclear;
 447    }
 448
 449    sctx->decompression_enabled = true;
 450
 451    while (level_mask) {
 452       unsigned level = u_bit_scan(&level_mask);
 453
 454       /* The smaller the mipmap level, the less layers there are
 455        * as far as 3D textures are concerned. */
 456       max_layer = util_max_layer(&tex->buffer.b.b, level);
 457       checked_last_layer = MIN2(last_layer, max_layer);
 458
 459       for (layer = first_layer; layer <= checked_last_layer; layer++) {
 460          struct pipe_surface *cbsurf, surf_tmpl;
 461
 462          surf_tmpl.format = tex->buffer.b.b.format;
 463          surf_tmpl.u.tex.level = level;
 464          surf_tmpl.u.tex.first_layer = layer;
 465          surf_tmpl.u.tex.last_layer = layer;
 466          cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl);
 467
 468          /* Required before and after FMASK and DCC_DECOMPRESS. */
 469          if (custom_blend == sctx->custom_blend_fmask_decompress ||
 470              custom_blend == sctx->custom_blend_dcc_decompress)
 471             sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
 472
 473          si_blitter_begin(sctx, SI_DECOMPRESS);
 474          util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
 475          si_blitter_end(sctx);
 476
 477          if (custom_blend == sctx->custom_blend_fmask_decompress ||
 478              custom_blend == sctx->custom_blend_dcc_decompress)
 479             sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
 480
 481          pipe_surface_reference(&cbsurf, NULL);
 482       }
 483
 484       /* The texture will always be dirty if some layers aren't flushed.
 485        * I don't think this case occurs often though. */
 486       if (first_layer == 0 && last_layer >= max_layer) {
 487          tex->dirty_level_mask &= ~(1 << level);
 488       }
 489    }
 490
 491    sctx->decompression_enabled = false;
 492    si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, vi_dcc_enabled(tex, first_level),
 493                               tex->surface.u.gfx9.dcc.pipe_aligned);
 494
 495 expand_fmask:
 496    if (need_fmask_expand && tex->surface.fmask_offset && !tex->fmask_is_identity) {
 497       si_compute_expand_fmask(&sctx->b, &tex->buffer.b.b);
 498       tex->fmask_is_identity = true;
 499    }
 500 }
 501
 502 static void si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
 503                                         unsigned first_level, unsigned last_level,
 504                                         bool need_fmask_expand)
 505 {
 506    /* CMASK or DCC can be discarded and we can still end up here. */
 507    if (!tex->cmask_buffer && !tex->surface.fmask_size &&
 508        !vi_dcc_enabled(tex, first_level))
 509       return;
 510
 511    si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
 512                             util_max_layer(&tex->buffer.b.b, first_level), false,
 513                             need_fmask_expand);
 514 }
 515
 516 static void si_decompress_sampler_color_textures(struct si_context *sctx,
 517                                                  struct si_samplers *textures)
 518 {
 519    unsigned i;
 520    unsigned mask = textures->needs_color_decompress_mask;
 521
 522    while (mask) {
 523       struct pipe_sampler_view *view;
 524       struct si_texture *tex;
 525
 526       i = u_bit_scan(&mask);
 527
 528       view = textures->views[i];
 529       assert(view);
 530
 531       tex = (struct si_texture *)view->texture;
 532
 533       si_decompress_color_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level,
 534                                   false);
 535    }
 536 }
 537
 538 static void si_decompress_image_color_textures(struct si_context *sctx, struct si_images *images)
 539 {
 540    unsigned i;
 541    unsigned mask = images->needs_color_decompress_mask;
 542
 543    while (mask) {
 544       const struct pipe_image_view *view;
 545       struct si_texture *tex;
 546
 547       i = u_bit_scan(&mask);
 548
 549       view = &images->views[i];
 550       assert(view->resource->target != PIPE_BUFFER);
 551
 552       tex = (struct si_texture *)view->resource;
 553
 554       si_decompress_color_texture(sctx, tex, view->u.tex.level, view->u.tex.level,
 555                                   view->access & PIPE_IMAGE_ACCESS_WRITE);
 556    }
 557 }
 558
 559 static void si_check_render_feedback_texture(struct si_context *sctx, struct si_texture *tex,
 560                                              unsigned first_level, unsigned last_level,
 561                                              unsigned first_layer, unsigned last_layer)
 562 {
 563    bool render_feedback = false;
 564
 565    if (!vi_dcc_enabled(tex, first_level))
 566       return;
 567
 568    for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
 569       struct si_surface *surf;
 570
 571       if (!sctx->framebuffer.state.cbufs[j])
 572          continue;
 573
 574       surf = (struct si_surface *)sctx->framebuffer.state.cbufs[j];
 575
 576       if (tex == (struct si_texture *)surf->base.texture && surf->base.u.tex.level >= first_level &&
 577           surf->base.u.tex.level <= last_level && surf->base.u.tex.first_layer <= last_layer &&
 578           surf->base.u.tex.last_layer >= first_layer) {
 579          render_feedback = true;
 580          break;
 581       }
 582    }
 583
 584    if (render_feedback)
 585       si_texture_disable_dcc(sctx, tex);
 586 }
 587
 588 static void si_check_render_feedback_textures(struct si_context *sctx, struct si_samplers *textures)
 589 {
 590    uint32_t mask = textures->enabled_mask;
 591
 592    while (mask) {
 593       const struct pipe_sampler_view *view;
 594       struct si_texture *tex;
 595
 596       unsigned i = u_bit_scan(&mask);
 597
 598       view = textures->views[i];
 599       if (view->texture->target == PIPE_BUFFER)
 600          continue;
 601
 602       tex = (struct si_texture *)view->texture;
 603
 604       si_check_render_feedback_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level,
 605                                        view->u.tex.first_layer, view->u.tex.last_layer);
 606    }
 607 }
 608
 609 static void si_check_render_feedback_images(struct si_context *sctx, struct si_images *images)
 610 {
 611    uint32_t mask = images->enabled_mask;
 612
 613    while (mask) {
 614       const struct pipe_image_view *view;
 615       struct si_texture *tex;
 616
 617       unsigned i = u_bit_scan(&mask);
 618
 619       view = &images->views[i];
 620       if (view->resource->target == PIPE_BUFFER)
 621          continue;
 622
 623       tex = (struct si_texture *)view->resource;
 624
 625       si_check_render_feedback_texture(sctx, tex, view->u.tex.level, view->u.tex.level,
 626                                        view->u.tex.first_layer, view->u.tex.last_layer);
 627    }
 628 }
 629
 630 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
 631 {
 632    util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) {
 633       struct pipe_sampler_view *view;
 634       struct si_texture *tex;
 635
 636       view = (*tex_handle)->view;
 637       if (view->texture->target == PIPE_BUFFER)
 638          continue;
 639
 640       tex = (struct si_texture *)view->texture;
 641
 642       si_check_render_feedback_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level,
 643                                        view->u.tex.first_layer, view->u.tex.last_layer);
 644    }
 645 }
 646
 647 static void si_check_render_feedback_resident_images(struct si_context *sctx)
 648 {
 649    util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) {
 650       struct pipe_image_view *view;
 651       struct si_texture *tex;
 652
 653       view = &(*img_handle)->view;
 654       if (view->resource->target == PIPE_BUFFER)
 655          continue;
 656
 657       tex = (struct si_texture *)view->resource;
 658
 659       si_check_render_feedback_texture(sctx, tex, view->u.tex.level, view->u.tex.level,
 660                                        view->u.tex.first_layer, view->u.tex.last_layer);
 661    }
 662 }
 663
 664 static void si_check_render_feedback(struct si_context *sctx)
 665 {
 666    if (!sctx->need_check_render_feedback)
 667       return;
 668
 669    /* There is no render feedback if color writes are disabled.
 670     * (e.g. a pixel shader with image stores)
 671     */
 672    if (!si_get_total_colormask(sctx))
 673       return;
 674
 675    for (int i = 0; i < SI_NUM_SHADERS; ++i) {
 676       si_check_render_feedback_images(sctx, &sctx->images[i]);
 677       si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
 678    }
 679
 680    si_check_render_feedback_resident_images(sctx);
 681    si_check_render_feedback_resident_textures(sctx);
 682
 683    sctx->need_check_render_feedback = false;
 684 }
 685
 686 static void si_decompress_resident_textures(struct si_context *sctx)
 687 {
 688    util_dynarray_foreach (&sctx->resident_tex_needs_color_decompress, struct si_texture_handle *,
 689                           tex_handle) {
 690       struct pipe_sampler_view *view = (*tex_handle)->view;
 691       struct si_texture *tex = (struct si_texture *)view->texture;
 692
 693       si_decompress_color_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level,
 694                                   false);
 695    }
 696
 697    util_dynarray_foreach (&sctx->resident_tex_needs_depth_decompress, struct si_texture_handle *,
 698                           tex_handle) {
 699       struct pipe_sampler_view *view = (*tex_handle)->view;
 700       struct si_sampler_view *sview = (struct si_sampler_view *)view;
 701       struct si_texture *tex = (struct si_texture *)view->texture;
 702
 703       si_decompress_depth(sctx, tex, sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
 704                           view->u.tex.first_level, view->u.tex.last_level, 0,
 705                           util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
 706    }
 707 }
 708
 709 static void si_decompress_resident_images(struct si_context *sctx)
 710 {
 711    util_dynarray_foreach (&sctx->resident_img_needs_color_decompress, struct si_image_handle *,
 712                           img_handle) {
 713       struct pipe_image_view *view = &(*img_handle)->view;
 714       struct si_texture *tex = (struct si_texture *)view->resource;
 715
 716       si_decompress_color_texture(sctx, tex, view->u.tex.level, view->u.tex.level,
 717                                   view->access & PIPE_IMAGE_ACCESS_WRITE);
 718    }
 719 }
 720
 721 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
 722 {
 723    unsigned compressed_colortex_counter, mask;
 724
 725    if (sctx->blitter->running)
 726       return;
 727
 728    /* Update the compressed_colortex_mask if necessary. */
 729    compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
 730    if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) {
 731       sctx->last_compressed_colortex_counter = compressed_colortex_counter;
 732       si_update_needs_color_decompress_masks(sctx);
 733    }
 734
 735    /* Decompress color & depth textures if needed. */
 736    mask = sctx->shader_needs_decompress_mask & shader_mask;
 737    while (mask) {
 738       unsigned i = u_bit_scan(&mask);
 739
 740       if (sctx->samplers[i].needs_depth_decompress_mask) {
 741          si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
 742       }
 743       if (sctx->samplers[i].needs_color_decompress_mask) {
 744          si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
 745       }
 746       if (sctx->images[i].needs_color_decompress_mask) {
 747          si_decompress_image_color_textures(sctx, &sctx->images[i]);
 748       }
 749    }
 750
 751    if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
 752       if (sctx->uses_bindless_samplers)
 753          si_decompress_resident_textures(sctx);
 754       if (sctx->uses_bindless_images)
 755          si_decompress_resident_images(sctx);
 756
 757       if (sctx->ps_uses_fbfetch) {
 758          struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
 759          si_decompress_color_texture(sctx, (struct si_texture *)cb0->texture,
 760                                      cb0->u.tex.first_layer, cb0->u.tex.last_layer, false);
 761       }
 762
 763       si_check_render_feedback(sctx);
 764    } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
 765       if (sctx->cs_shader_state.program->sel.info.uses_bindless_samplers)
 766          si_decompress_resident_textures(sctx);
 767       if (sctx->cs_shader_state.program->sel.info.uses_bindless_images)
 768          si_decompress_resident_images(sctx);
 769    }
 770 }
 771
 772 /* Helper for decompressing a portion of a color or depth resource before
 773  * blitting if any decompression is needed.
 774  * The driver doesn't decompress resources automatically while u_blitter is
 775  * rendering. */
 776 void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
 777                                unsigned level, unsigned first_layer, unsigned last_layer)
 778 {
 779    struct si_context *sctx = (struct si_context *)ctx;
 780    struct si_texture *stex = (struct si_texture *)tex;
 781
 782    if (stex->db_compatible) {
 783       planes &= PIPE_MASK_Z | PIPE_MASK_S;
 784
 785       if (!stex->surface.has_stencil)
 786          planes &= ~PIPE_MASK_S;
 787
 788       /* If we've rendered into the framebuffer and it's a blitting
 789        * source, make sure the decompression pass is invoked
 790        * by dirtying the framebuffer.
 791        */
 792       if (sctx->framebuffer.state.zsbuf && sctx->framebuffer.state.zsbuf->u.tex.level == level &&
 793           sctx->framebuffer.state.zsbuf->texture == tex)
 794          si_update_fb_dirtiness_after_rendering(sctx);
 795
 796       si_decompress_depth(sctx, stex, planes, level, level, first_layer, last_layer);
 797    } else if (stex->surface.fmask_size || stex->cmask_buffer ||
 798               vi_dcc_enabled(stex, level)) {
 799       /* If we've rendered into the framebuffer and it's a blitting
 800        * source, make sure the decompression pass is invoked
 801        * by dirtying the framebuffer.
 802        */
 803       for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
 804          if (sctx->framebuffer.state.cbufs[i] &&
 805              sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
 806              sctx->framebuffer.state.cbufs[i]->texture == tex) {
 807             si_update_fb_dirtiness_after_rendering(sctx);
 808             break;
 809          }
 810       }
 811
 812       si_blit_decompress_color(sctx, stex, level, level, first_layer, last_layer, false, false);
 813    }
 814 }
 815
 816 struct texture_orig_info {
 817    unsigned format;
 818    unsigned width0;
 819    unsigned height0;
 820    unsigned npix_x;
 821    unsigned npix_y;
 822    unsigned npix0_x;
 823    unsigned npix0_y;
 824 };
 825
 826 void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
 827                              unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
 828                              struct pipe_resource *src, unsigned src_level,
 829                              const struct pipe_box *src_box)
 830 {
 831    struct si_context *sctx = (struct si_context *)ctx;
 832    struct si_texture *ssrc = (struct si_texture *)src;
 833    struct si_texture *sdst = (struct si_texture *)dst;
 834    struct pipe_surface *dst_view, dst_templ;
 835    struct pipe_sampler_view src_templ, *src_view;
 836    unsigned dst_width, dst_height, src_width0, src_height0;
 837    unsigned dst_width0, dst_height0, src_force_level = 0;
 838    struct pipe_box sbox, dstbox;
 839
 840    /* Handle buffers first. */
 841    if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 842       si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
 843       return;
 844    }
 845
 846    if (!util_format_is_compressed(src->format) && !util_format_is_compressed(dst->format) &&
 847        !util_format_is_depth_or_stencil(src->format) && src->nr_samples <= 1 &&
 848        !vi_dcc_enabled(sdst, dst_level) &&
 849        !(dst->target != src->target &&
 850          (src->target == PIPE_TEXTURE_1D_ARRAY || dst->target == PIPE_TEXTURE_1D_ARRAY))) {
 851       si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz,
 852                             src_box, false);
 853       return;
 854    }
 855
 856    assert(u_max_sample(dst) == u_max_sample(src));
 857
 858    /* The driver doesn't decompress resources automatically while
 859     * u_blitter is rendering. */
 860    si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level, src_box->z,
 861                              src_box->z + src_box->depth - 1);
 862
 863    dst_width = u_minify(dst->width0, dst_level);
 864    dst_height = u_minify(dst->height0, dst_level);
 865    dst_width0 = dst->width0;
 866    dst_height0 = dst->height0;
 867    src_width0 = src->width0;
 868    src_height0 = src->height0;
 869
 870    util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
 871    util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
 872
 873    if (util_format_is_compressed(src->format) || util_format_is_compressed(dst->format)) {
 874       unsigned blocksize = ssrc->surface.bpe;
 875
 876       if (blocksize == 8)
 877          src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
 878       else
 879          src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
 880       dst_templ.format = src_templ.format;
 881
 882       dst_width = util_format_get_nblocksx(dst->format, dst_width);
 883       dst_height = util_format_get_nblocksy(dst->format, dst_height);
 884       dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
 885       dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
 886       src_width0 = util_format_get_nblocksx(src->format, src_width0);
 887       src_height0 = util_format_get_nblocksy(src->format, src_height0);
 888
 889       dstx = util_format_get_nblocksx(dst->format, dstx);
 890       dsty = util_format_get_nblocksy(dst->format, dsty);
 891
 892       sbox.x = util_format_get_nblocksx(src->format, src_box->x);
 893       sbox.y = util_format_get_nblocksy(src->format, src_box->y);
 894       sbox.z = src_box->z;
 895       sbox.width = util_format_get_nblocksx(src->format, src_box->width);
 896       sbox.height = util_format_get_nblocksy(src->format, src_box->height);
 897       sbox.depth = src_box->depth;
 898       src_box = &sbox;
 899
 900       src_force_level = src_level;
 901    } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
 902       if (util_format_is_subsampled_422(src->format)) {
 903          src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
 904          dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
 905
 906          dst_width = util_format_get_nblocksx(dst->format, dst_width);
 907          dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
 908          src_width0 = util_format_get_nblocksx(src->format, src_width0);
 909
 910          dstx = util_format_get_nblocksx(dst->format, dstx);
 911
 912          sbox = *src_box;
 913          sbox.x = util_format_get_nblocksx(src->format, src_box->x);
 914          sbox.width = util_format_get_nblocksx(src->format, src_box->width);
 915          src_box = &sbox;
 916       } else {
 917          unsigned blocksize = ssrc->surface.bpe;
 918
 919          switch (blocksize) {
 920          case 1:
 921             dst_templ.format = PIPE_FORMAT_R8_UNORM;
 922             src_templ.format = PIPE_FORMAT_R8_UNORM;
 923             break;
 924          case 2:
 925             dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
 926             src_templ.format = PIPE_FORMAT_R8G8_UNORM;
 927             break;
 928          case 4:
 929             dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 930             src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 931             break;
 932          case 8:
 933             dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
 934             src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
 935             break;
 936          case 16:
 937             dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
 938             src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
 939             break;
 940          default:
 941             fprintf(stderr, "Unhandled format %s with blocksize %u\n",
 942                     util_format_short_name(src->format), blocksize);
 943             assert(0);
 944          }
 945       }
 946    }
 947
 948    /* SNORM8 blitting has precision issues on some chips. Use the SINT
 949     * equivalent instead, which doesn't force DCC decompression.
 950     * Note that some chips avoid this issue by using SDMA.
 951     */
 952    if (util_format_is_snorm8(dst_templ.format)) {
 953       dst_templ.format = src_templ.format = util_format_snorm8_to_sint8(dst_templ.format);
 954    }
 955
 956    vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level, dst_templ.format);
 957    vi_disable_dcc_if_incompatible_format(sctx, src, src_level, src_templ.format);
 958
 959    /* Initialize the surface. */
 960    dst_view = si_create_surface_custom(ctx, dst, &dst_templ, dst_width0, dst_height0, dst_width,
 961                                        dst_height);
 962
 963    /* Initialize the sampler view. */
 964    src_view =
 965       si_create_sampler_view_custom(ctx, src, &src_templ, src_width0, src_height0, src_force_level);
 966
 967    u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height), abs(src_box->depth),
 968             &dstbox);
 969
 970    /* Copy. */
 971    si_blitter_begin(sctx, SI_COPY);
 972    util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox, src_view, src_box, src_width0,
 973                              src_height0, PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL, false);
 974    si_blitter_end(sctx);
 975
 976    pipe_surface_reference(&dst_view, NULL);
 977    pipe_sampler_view_reference(&src_view, NULL);
 978 }
 979
 980 static void si_do_CB_resolve(struct si_context *sctx, const struct pipe_blit_info *info,
 981                              struct pipe_resource *dst, unsigned dst_level, unsigned dst_z,
 982                              enum pipe_format format)
 983 {
 984    /* Required before and after CB_RESOLVE. */
 985    sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
 986
 987    si_blitter_begin(
 988       sctx, SI_COLOR_RESOLVE | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
 989    util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z, info->src.resource,
 990                                      info->src.box.z, ~0, sctx->custom_blend_resolve, format);
 991    si_blitter_end(sctx);
 992
 993    /* Flush caches for possible texturing. */
 994    si_make_CB_shader_coherent(sctx, 1, false, true /* no DCC */);
 995 }
 996
 997 static bool do_hardware_msaa_resolve(struct pipe_context *ctx, const struct pipe_blit_info *info)
 998 {
 999    struct si_context *sctx = (struct si_context *)ctx;
1000    struct si_texture *src = (struct si_texture *)info->src.resource;
1001    struct si_texture *dst = (struct si_texture *)info->dst.resource;
1002    ASSERTED struct si_texture *stmp;
1003    unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1004    unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1005    enum pipe_format format = info->src.format;
1006    struct pipe_resource *tmp, templ;
1007    struct pipe_blit_info blit;
1008
1009    /* Check basic requirements for hw resolve. */
1010    if (!(info->src.resource->nr_samples > 1 && info->dst.resource->nr_samples <= 1 &&
1011          !util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format) &&
1012          util_max_layer(info->src.resource, 0) == 0))
1013       return false;
1014
1015    /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1016     * the format is R16G16. Use R16A16, which does work.
1017     */
1018    if (format == PIPE_FORMAT_R16G16_UNORM)
1019       format = PIPE_FORMAT_R16A16_UNORM;
1020    if (format == PIPE_FORMAT_R16G16_SNORM)
1021       format = PIPE_FORMAT_R16A16_SNORM;
1022
1023    /* Check the remaining requirements for hw resolve. */
1024    if (util_max_layer(info->dst.resource, info->dst.level) == 0 && !info->scissor_enable &&
1025        (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1026        util_is_format_compatible(util_format_description(info->src.format),
1027                                  util_format_description(info->dst.format)) &&
1028        dst_width == info->src.resource->width0 && dst_height == info->src.resource->height0 &&
1029        info->dst.box.x == 0 && info->dst.box.y == 0 && info->dst.box.width == dst_width &&
1030        info->dst.box.height == dst_height && info->dst.box.depth == 1 && info->src.box.x == 0 &&
1031        info->src.box.y == 0 && info->src.box.width == dst_width &&
1032        info->src.box.height == dst_height && info->src.box.depth == 1 && !dst->surface.is_linear &&
1033        (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1034       /* Check the last constraint. */
1035       if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1036          /* The next fast clear will switch to this mode to
1037           * get direct hw resolve next time if the mode is
1038           * different now.
1039           *
1040           * TODO-GFX10: This does not work in GFX10 because MSAA
1041           * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes.
1042           * In some cases we could change the swizzle of the
1043           * destination texture instead, but the more general
1044           * solution is to implement compute shader resolve.
1045           */
1046          src->last_msaa_resolve_target_micro_mode = dst->surface.micro_tile_mode;
1047          goto resolve_to_temp;
1048       }
1049
1050       /* Resolving into a surface with DCC is unsupported. Since
1051        * it's being overwritten anyway, clear it to uncompressed.
1052        * This is still the fastest codepath even with this clear.
1053        */
1054       if (vi_dcc_enabled(dst, info->dst.level)) {
1055          if (!vi_dcc_clear_level(sctx, dst, info->dst.level, DCC_UNCOMPRESSED))
1056             goto resolve_to_temp;
1057
1058          dst->dirty_level_mask &= ~(1 << info->dst.level);
1059       }
1060
1061       /* Resolve directly from src to dst. */
1062       si_do_CB_resolve(sctx, info, info->dst.resource, info->dst.level, info->dst.box.z, format);
1063       return true;
1064    }
1065
1066 resolve_to_temp:
1067    /* Shader-based resolve is VERY SLOW. Instead, resolve into
1068     * a temporary texture and blit.
1069     */
1070    memset(&templ, 0, sizeof(templ));
1071    templ.target = PIPE_TEXTURE_2D;
1072    templ.format = info->src.resource->format;
1073    templ.width0 = info->src.resource->width0;
1074    templ.height0 = info->src.resource->height0;
1075    templ.depth0 = 1;
1076    templ.array_size = 1;
1077    templ.usage = PIPE_USAGE_DEFAULT;
1078    templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING | SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE |
1079                  SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(src->surface.micro_tile_mode) |
1080                  SI_RESOURCE_FLAG_DISABLE_DCC;
1081
1082    /* The src and dst microtile modes must be the same. */
1083    if (sctx->chip_class <= GFX8 && src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1084       templ.bind = PIPE_BIND_SCANOUT;
1085    else
1086       templ.bind = 0;
1087
1088    tmp = ctx->screen->resource_create(ctx->screen, &templ);
1089    if (!tmp)
1090       return false;
1091    stmp = (struct si_texture *)tmp;
1092
1093    assert(!stmp->surface.is_linear);
1094    assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode);
1095
1096    /* resolve */
1097    si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1098
1099    /* blit */
1100    blit = *info;
1101    blit.src.resource = tmp;
1102    blit.src.box.z = 0;
1103
1104    si_blitter_begin(sctx, SI_BLIT | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1105    util_blitter_blit(sctx->blitter, &blit);
1106    si_blitter_end(sctx);
1107
1108    pipe_resource_reference(&tmp, NULL);
1109    return true;
1110 }
1111
1112 static void si_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
1113 {
1114    struct si_context *sctx = (struct si_context *)ctx;
1115    struct si_texture *dst = (struct si_texture *)info->dst.resource;
1116
1117    if (do_hardware_msaa_resolve(ctx, info)) {
1118       return;
1119    }
1120
1121    /* Using SDMA for copying to a linear texture in GTT is much faster.
1122     * This improves DRI PRIME performance.
1123     *
1124     * resource_copy_region can't do this yet, because dma_copy calls it
1125     * on failure (recursion).
1126     */
1127    if (dst->surface.is_linear && util_can_blit_via_copy_region(info, false)) {
1128       sctx->dma_copy(ctx, info->dst.resource, info->dst.level, info->dst.box.x, info->dst.box.y,
1129                      info->dst.box.z, info->src.resource, info->src.level, &info->src.box);
1130       return;
1131    }
1132
1133    assert(util_blitter_is_blit_supported(sctx->blitter, info));
1134
1135    /* The driver doesn't decompress resources automatically while
1136     * u_blitter is rendering. */
1137    vi_disable_dcc_if_incompatible_format(sctx, info->src.resource, info->src.level,
1138                                          info->src.format);
1139    vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource, info->dst.level,
1140                                          info->dst.format);
1141    si_decompress_subresource(ctx, info->src.resource, PIPE_MASK_RGBAZS, info->src.level,
1142                              info->src.box.z, info->src.box.z + info->src.box.depth - 1);
1143
1144    if (sctx->screen->debug_flags & DBG(FORCE_SDMA) && util_try_blit_via_copy_region(ctx, info))
1145       return;
1146
1147    si_blitter_begin(sctx, SI_BLIT | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1148    util_blitter_blit(sctx->blitter, info);
1149    si_blitter_end(sctx);
1150 }
1151
1152 static bool si_generate_mipmap(struct pipe_context *ctx, struct pipe_resource *tex,
1153                                enum pipe_format format, unsigned base_level, unsigned last_level,
1154                                unsigned first_layer, unsigned last_layer)
1155 {
1156    struct si_context *sctx = (struct si_context *)ctx;
1157    struct si_texture *stex = (struct si_texture *)tex;
1158
1159    if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1160       return false;
1161
1162    /* The driver doesn't decompress resources automatically while
1163     * u_blitter is rendering. */
1164    vi_disable_dcc_if_incompatible_format(sctx, tex, base_level, format);
1165    si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS, base_level, first_layer, last_layer);
1166
1167    /* Clear dirty_level_mask for the levels that will be overwritten. */
1168    assert(base_level < last_level);
1169    stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1, last_level - base_level);
1170
1171    sctx->generate_mipmap_for_depth = stex->is_depth;
1172
1173    si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1174    util_blitter_generate_mipmap(sctx->blitter, tex, format, base_level, last_level, first_layer,
1175                                 last_layer);
1176    si_blitter_end(sctx);
1177
1178    sctx->generate_mipmap_for_depth = false;
1179    return true;
1180 }
1181
1182 static void si_flush_resource(struct pipe_context *ctx, struct pipe_resource *res)
1183 {
1184    struct si_context *sctx = (struct si_context *)ctx;
1185    struct si_texture *tex = (struct si_texture *)res;
1186
1187    assert(res->target != PIPE_BUFFER);
1188    assert(!tex->dcc_separate_buffer || tex->dcc_gather_statistics);
1189
1190    /* st/dri calls flush twice per frame (not a bug), this prevents double
1191     * decompression. */
1192    if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
1193       return;
1194
1195    if (!tex->is_depth && (tex->cmask_buffer || vi_dcc_enabled(tex, 0))) {
1196       si_blit_decompress_color(sctx, tex, 0, res->last_level, 0, util_max_layer(res, 0),
1197                                tex->dcc_separate_buffer != NULL, false);
1198
1199       if (tex->surface.display_dcc_offset && tex->displayable_dcc_dirty) {
1200          si_retile_dcc(sctx, tex);
1201          tex->displayable_dcc_dirty = false;
1202       }
1203    }
1204
1205    /* Always do the analysis even if DCC is disabled at the moment. */
1206    if (tex->dcc_gather_statistics) {
1207       bool separate_dcc_dirty = tex->separate_dcc_dirty;
1208
1209       /* If the color buffer hasn't been unbound and fast clear hasn't
1210        * been used, separate_dcc_dirty is false, but there may have been
1211        * new rendering. Check if the color buffer is bound and assume
1212        * it's dirty.
1213        *
1214        * Note that DRI2 never unbinds window colorbuffers, which means
1215        * the DCC pipeline statistics query would never be re-set and would
1216        * keep adding new results until all free memory is exhausted if we
1217        * didn't do this.
1218        */
1219       if (!separate_dcc_dirty) {
1220          for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
1221             if (sctx->framebuffer.state.cbufs[i] &&
1222                 sctx->framebuffer.state.cbufs[i]->texture == res) {
1223                separate_dcc_dirty = true;
1224                break;
1225             }
1226          }
1227       }
1228
1229       if (separate_dcc_dirty) {
1230          tex->separate_dcc_dirty = false;
1231          vi_separate_dcc_process_and_reset_stats(ctx, tex);
1232       }
1233    }
1234 }
1235
1236 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
1237 {
1238    /* If graphics is disabled, we can't decompress DCC, but it shouldn't
1239     * be compressed either. The caller should simply discard it.
1240     */
1241    if (!tex->surface.dcc_offset || !sctx->has_graphics)
1242       return;
1243
1244    if (sctx->chip_class == GFX8) {
1245       si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level, 0,
1246                                util_max_layer(&tex->buffer.b.b, 0), true, false);
1247    } else {
1248       struct pipe_resource *ptex = &tex->buffer.b.b;
1249
1250       /* DCC decompression using a compute shader. */
1251       for (unsigned level = 0; level < tex->surface.num_dcc_levels; level++) {
1252          struct pipe_box box;
1253
1254          u_box_3d(0, 0, 0, u_minify(ptex->width0, level),
1255                   u_minify(ptex->height0, level),
1256                   util_num_layers(ptex, level), &box);
1257          si_compute_copy_image(sctx, ptex, level, ptex, level, 0, 0, 0, &box,
1258                                true);
1259       }
1260
1261       /* Now clear DCC metadata to uncompressed. */
1262       uint32_t clear_value = DCC_UNCOMPRESSED;
1263       si_clear_buffer(sctx, ptex, tex->surface.dcc_offset,
1264                       tex->surface.dcc_size, &clear_value, 4,
1265                       SI_COHERENCY_CB_META, false);
1266    }
1267 }
1268
1269 void si_init_blit_functions(struct si_context *sctx)
1270 {
1271    sctx->b.resource_copy_region = si_resource_copy_region;
1272
1273    if (sctx->has_graphics) {
1274       sctx->b.blit = si_blit;
1275       sctx->b.flush_resource = si_flush_resource;
1276       sctx->b.generate_mipmap = si_generate_mipmap;
1277    }
1278 }