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radeonsi: decompress to flushed depth texture when required
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "util/u_format.h"
27 #include "util/u_surface.h"
28
29 enum si_blitter_op /* bitmask */
30 {
31 SI_SAVE_TEXTURES = 1,
32 SI_SAVE_FRAMEBUFFER = 2,
33 SI_SAVE_FRAGMENT_STATE = 4,
34 SI_DISABLE_RENDER_COND = 8,
35
36 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
37
38 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
39
40 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
41 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
42
43 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
44 SI_SAVE_FRAGMENT_STATE,
45
46 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
47 SI_DISABLE_RENDER_COND,
48
49 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
50 };
51
52 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
53 {
54 struct si_context *sctx = (struct si_context *)ctx;
55
56 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
57 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
58 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
59 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
60 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
61 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
62 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
63 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
64 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
65
66 if (op & SI_SAVE_FRAGMENT_STATE) {
67 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
68 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
69 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
70 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
71 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
72 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
73 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
74 }
75
76 if (op & SI_SAVE_FRAMEBUFFER)
77 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
78
79 if (op & SI_SAVE_TEXTURES) {
80 util_blitter_save_fragment_sampler_states(
81 sctx->blitter, 2,
82 sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
83
84 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
85 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
86 }
87
88 if (op & SI_DISABLE_RENDER_COND)
89 sctx->b.render_cond_force_off = true;
90 }
91
92 static void si_blitter_end(struct pipe_context *ctx)
93 {
94 struct si_context *sctx = (struct si_context *)ctx;
95
96 sctx->b.render_cond_force_off = false;
97 }
98
99 static unsigned u_max_sample(struct pipe_resource *r)
100 {
101 return r->nr_samples ? r->nr_samples - 1 : 0;
102 }
103
104 static unsigned
105 si_blit_dbcb_copy(struct si_context *sctx,
106 struct r600_texture *src,
107 struct r600_texture *dst,
108 unsigned planes, unsigned level_mask,
109 unsigned first_layer, unsigned last_layer,
110 unsigned first_sample, unsigned last_sample)
111 {
112 struct pipe_surface surf_tmpl = {{0}};
113 unsigned layer, sample, checked_last_layer, max_layer;
114 unsigned fully_copied_levels = 0;
115
116 if (planes & PIPE_MASK_Z)
117 sctx->dbcb_depth_copy_enabled = true;
118 if (planes & PIPE_MASK_S)
119 sctx->dbcb_stencil_copy_enabled = true;
120 si_mark_atom_dirty(sctx, &sctx->db_render_state);
121
122 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
123
124 while (level_mask) {
125 unsigned level = u_bit_scan(&level_mask);
126
127 /* The smaller the mipmap level, the less layers there are
128 * as far as 3D textures are concerned. */
129 max_layer = util_max_layer(&src->resource.b.b, level);
130 checked_last_layer = MIN2(last_layer, max_layer);
131
132 surf_tmpl.u.tex.level = level;
133
134 for (layer = first_layer; layer <= checked_last_layer; layer++) {
135 struct pipe_surface *zsurf, *cbsurf;
136
137 surf_tmpl.format = src->resource.b.b.format;
138 surf_tmpl.u.tex.first_layer = layer;
139 surf_tmpl.u.tex.last_layer = layer;
140
141 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
142
143 surf_tmpl.format = dst->resource.b.b.format;
144 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
145
146 for (sample = first_sample; sample <= last_sample; sample++) {
147 if (sample != sctx->dbcb_copy_sample) {
148 sctx->dbcb_copy_sample = sample;
149 si_mark_atom_dirty(sctx, &sctx->db_render_state);
150 }
151
152 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
153 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
154 sctx->custom_dsa_flush, 1.0f);
155 si_blitter_end(&sctx->b.b);
156 }
157
158 pipe_surface_reference(&zsurf, NULL);
159 pipe_surface_reference(&cbsurf, NULL);
160 }
161
162 if (first_layer == 0 && last_layer >= max_layer &&
163 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
164 fully_copied_levels |= 1u << level;
165 }
166
167 sctx->dbcb_depth_copy_enabled = false;
168 sctx->dbcb_stencil_copy_enabled = false;
169 si_mark_atom_dirty(sctx, &sctx->db_render_state);
170
171 return fully_copied_levels;
172 }
173
174 static void si_blit_decompress_depth(struct pipe_context *ctx,
175 struct r600_texture *texture,
176 struct r600_texture *staging,
177 unsigned first_level, unsigned last_level,
178 unsigned first_layer, unsigned last_layer,
179 unsigned first_sample, unsigned last_sample)
180 {
181 const struct util_format_description *desc;
182 unsigned planes = 0;
183
184 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
185
186 desc = util_format_description(staging->resource.b.b.format);
187
188 if (util_format_has_depth(desc))
189 planes |= PIPE_MASK_Z;
190 if (util_format_has_stencil(desc))
191 planes |= PIPE_MASK_S;
192
193 si_blit_dbcb_copy(
194 (struct si_context *)ctx, texture, staging, planes,
195 u_bit_consecutive(first_level, last_level - first_level + 1),
196 first_layer, last_layer, first_sample, last_sample);
197 }
198
199 /* Helper function for si_blit_decompress_zs_in_place.
200 */
201 static void
202 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
203 struct r600_texture *texture,
204 unsigned planes, unsigned level_mask,
205 unsigned first_layer, unsigned last_layer)
206 {
207 struct pipe_surface *zsurf, surf_tmpl = {{0}};
208 unsigned layer, max_layer, checked_last_layer;
209 unsigned fully_decompressed_mask = 0;
210
211 if (!level_mask)
212 return;
213
214 if (planes & PIPE_MASK_S)
215 sctx->db_flush_stencil_inplace = true;
216 if (planes & PIPE_MASK_Z)
217 sctx->db_flush_depth_inplace = true;
218 si_mark_atom_dirty(sctx, &sctx->db_render_state);
219
220 surf_tmpl.format = texture->resource.b.b.format;
221
222 while (level_mask) {
223 unsigned level = u_bit_scan(&level_mask);
224
225 surf_tmpl.u.tex.level = level;
226
227 /* The smaller the mipmap level, the less layers there are
228 * as far as 3D textures are concerned. */
229 max_layer = util_max_layer(&texture->resource.b.b, level);
230 checked_last_layer = MIN2(last_layer, max_layer);
231
232 for (layer = first_layer; layer <= checked_last_layer; layer++) {
233 surf_tmpl.u.tex.first_layer = layer;
234 surf_tmpl.u.tex.last_layer = layer;
235
236 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
237
238 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
239 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
240 sctx->custom_dsa_flush,
241 1.0f);
242 si_blitter_end(&sctx->b.b);
243
244 pipe_surface_reference(&zsurf, NULL);
245 }
246
247 /* The texture will always be dirty if some layers aren't flushed.
248 * I don't think this case occurs often though. */
249 if (first_layer == 0 && last_layer >= max_layer) {
250 fully_decompressed_mask |= 1u << level;
251 }
252 }
253
254 if (planes & PIPE_MASK_Z)
255 texture->dirty_level_mask &= ~fully_decompressed_mask;
256 if (planes & PIPE_MASK_S)
257 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
258
259 sctx->db_flush_depth_inplace = false;
260 sctx->db_flush_stencil_inplace = false;
261 si_mark_atom_dirty(sctx, &sctx->db_render_state);
262 }
263
264 /* Helper function of si_flush_depth_texture: decompress the given levels
265 * of Z and/or S planes in place.
266 */
267 static void
268 si_blit_decompress_zs_in_place(struct si_context *sctx,
269 struct r600_texture *texture,
270 unsigned levels_z, unsigned levels_s,
271 unsigned first_layer, unsigned last_layer)
272 {
273 unsigned both = levels_z & levels_s;
274
275 /* First, do combined Z & S decompresses for levels that need it. */
276 if (both) {
277 si_blit_decompress_zs_planes_in_place(
278 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
279 both,
280 first_layer, last_layer);
281 levels_z &= ~both;
282 levels_s &= ~both;
283 }
284
285 /* Now do separate Z and S decompresses. */
286 if (levels_z) {
287 si_blit_decompress_zs_planes_in_place(
288 sctx, texture, PIPE_MASK_Z,
289 levels_z,
290 first_layer, last_layer);
291 }
292
293 if (levels_s) {
294 si_blit_decompress_zs_planes_in_place(
295 sctx, texture, PIPE_MASK_S,
296 levels_s,
297 first_layer, last_layer);
298 }
299 }
300
301 static void
302 si_flush_depth_texture(struct si_context *sctx,
303 struct r600_texture *tex,
304 unsigned required_planes,
305 unsigned first_level, unsigned last_level,
306 unsigned first_layer, unsigned last_layer)
307 {
308 unsigned inplace_planes = 0;
309 unsigned copy_planes = 0;
310 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
311 unsigned levels_z = 0;
312 unsigned levels_s = 0;
313
314 if (required_planes & PIPE_MASK_Z) {
315 levels_z = level_mask & tex->dirty_level_mask;
316
317 if (levels_z) {
318 if (r600_can_sample_zs(tex, false))
319 inplace_planes |= PIPE_MASK_Z;
320 else
321 copy_planes |= PIPE_MASK_Z;
322 }
323 }
324 if (required_planes & PIPE_MASK_S) {
325 levels_s = level_mask & tex->stencil_dirty_level_mask;
326
327 if (levels_s) {
328 if (r600_can_sample_zs(tex, true))
329 inplace_planes |= PIPE_MASK_S;
330 else
331 copy_planes |= PIPE_MASK_S;
332 }
333 }
334
335 /* We may have to allocate the flushed texture here when called from
336 * si_decompress_subresource.
337 */
338 if (copy_planes &&
339 (tex->flushed_depth_texture ||
340 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
341 struct r600_texture *dst = tex->flushed_depth_texture;
342 unsigned fully_copied_levels;
343 unsigned levels = 0;
344
345 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
346 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
347
348 if (copy_planes & PIPE_MASK_Z) {
349 levels |= levels_z;
350 levels_z = 0;
351 }
352 if (copy_planes & PIPE_MASK_S) {
353 levels |= levels_s;
354 levels_s = 0;
355 }
356
357 fully_copied_levels = si_blit_dbcb_copy(
358 sctx, tex, dst, copy_planes, levels,
359 first_layer, last_layer,
360 0, u_max_sample(&tex->resource.b.b));
361
362 if (copy_planes & PIPE_MASK_Z)
363 tex->dirty_level_mask &= ~fully_copied_levels;
364 if (copy_planes & PIPE_MASK_S)
365 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
366 }
367
368 if (inplace_planes) {
369 si_blit_decompress_zs_in_place(
370 sctx, tex,
371 levels_z, levels_s,
372 first_layer, last_layer);
373 }
374 }
375
376 static void
377 si_flush_depth_textures(struct si_context *sctx,
378 struct si_textures_info *textures)
379 {
380 unsigned i;
381 unsigned mask = textures->depth_texture_mask;
382
383 while (mask) {
384 struct pipe_sampler_view *view;
385 struct si_sampler_view *sview;
386 struct r600_texture *tex;
387
388 i = u_bit_scan(&mask);
389
390 view = textures->views.views[i];
391 assert(view);
392 sview = (struct si_sampler_view*)view;
393
394 tex = (struct r600_texture *)view->texture;
395 assert(tex->db_compatible);
396
397 si_flush_depth_texture(
398 sctx, tex,
399 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
400 view->u.tex.first_level, view->u.tex.last_level,
401 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
402 }
403 }
404
405 static void si_blit_decompress_color(struct pipe_context *ctx,
406 struct r600_texture *rtex,
407 unsigned first_level, unsigned last_level,
408 unsigned first_layer, unsigned last_layer,
409 bool need_dcc_decompress)
410 {
411 struct si_context *sctx = (struct si_context *)ctx;
412 void* custom_blend;
413 unsigned layer, checked_last_layer, max_layer;
414 unsigned level_mask =
415 u_bit_consecutive(first_level, last_level - first_level + 1);
416
417 if (!need_dcc_decompress)
418 level_mask &= rtex->dirty_level_mask;
419 if (!level_mask)
420 return;
421
422 if (rtex->dcc_offset && need_dcc_decompress) {
423 custom_blend = sctx->custom_blend_dcc_decompress;
424
425 /* disable levels without DCC */
426 for (int i = first_level; i <= last_level; i++) {
427 if (!rtex->dcc_offset ||
428 !rtex->surface.level[i].dcc_enabled)
429 level_mask &= ~(1 << i);
430 }
431 } else if (rtex->fmask.size) {
432 custom_blend = sctx->custom_blend_decompress;
433 } else {
434 custom_blend = sctx->custom_blend_fastclear;
435 }
436
437 while (level_mask) {
438 unsigned level = u_bit_scan(&level_mask);
439
440 /* The smaller the mipmap level, the less layers there are
441 * as far as 3D textures are concerned. */
442 max_layer = util_max_layer(&rtex->resource.b.b, level);
443 checked_last_layer = MIN2(last_layer, max_layer);
444
445 for (layer = first_layer; layer <= checked_last_layer; layer++) {
446 struct pipe_surface *cbsurf, surf_tmpl;
447
448 surf_tmpl.format = rtex->resource.b.b.format;
449 surf_tmpl.u.tex.level = level;
450 surf_tmpl.u.tex.first_layer = layer;
451 surf_tmpl.u.tex.last_layer = layer;
452 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
453
454 si_blitter_begin(ctx, SI_DECOMPRESS);
455 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
456 si_blitter_end(ctx);
457
458 pipe_surface_reference(&cbsurf, NULL);
459 }
460
461 /* The texture will always be dirty if some layers aren't flushed.
462 * I don't think this case occurs often though. */
463 if (first_layer == 0 && last_layer >= max_layer) {
464 rtex->dirty_level_mask &= ~(1 << level);
465 }
466 }
467 }
468
469 static void
470 si_decompress_sampler_color_textures(struct si_context *sctx,
471 struct si_textures_info *textures)
472 {
473 unsigned i;
474 unsigned mask = textures->compressed_colortex_mask;
475
476 while (mask) {
477 struct pipe_sampler_view *view;
478 struct r600_texture *tex;
479
480 i = u_bit_scan(&mask);
481
482 view = textures->views.views[i];
483 assert(view);
484
485 tex = (struct r600_texture *)view->texture;
486 assert(tex->cmask.size || tex->fmask.size || tex->dcc_offset);
487
488 si_blit_decompress_color(&sctx->b.b, tex,
489 view->u.tex.first_level, view->u.tex.last_level,
490 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
491 false);
492 }
493 }
494
495 static void
496 si_decompress_image_color_textures(struct si_context *sctx,
497 struct si_images_info *images)
498 {
499 unsigned i;
500 unsigned mask = images->compressed_colortex_mask;
501
502 while (mask) {
503 const struct pipe_image_view *view;
504 struct r600_texture *tex;
505
506 i = u_bit_scan(&mask);
507
508 view = &images->views[i];
509 assert(view->resource->target != PIPE_BUFFER);
510
511 tex = (struct r600_texture *)view->resource;
512 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
513 continue;
514
515 si_blit_decompress_color(&sctx->b.b, tex,
516 view->u.tex.level, view->u.tex.level,
517 0, util_max_layer(&tex->resource.b.b, view->u.tex.level),
518 false);
519 }
520 }
521
522 static void si_check_render_feedback_textures(struct si_context *sctx,
523 struct si_textures_info *textures)
524 {
525 uint32_t mask = textures->views.enabled_mask;
526
527 while (mask) {
528 const struct pipe_sampler_view *view;
529 struct r600_texture *tex;
530 bool render_feedback = false;
531
532 unsigned i = u_bit_scan(&mask);
533
534 view = textures->views.views[i];
535 if(view->texture->target == PIPE_BUFFER)
536 continue;
537
538 tex = (struct r600_texture *)view->texture;
539 if (!tex->dcc_offset)
540 continue;
541
542 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
543 struct r600_surface * surf;
544
545 if (!sctx->framebuffer.state.cbufs[j])
546 continue;
547
548 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
549
550 if (tex == (struct r600_texture*)surf->base.texture &&
551 surf->base.u.tex.level >= view->u.tex.first_level &&
552 surf->base.u.tex.level <= view->u.tex.last_level &&
553 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
554 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
555 render_feedback = true;
556 }
557
558 if (render_feedback) {
559 struct si_screen *screen = sctx->screen;
560 r600_texture_disable_dcc(&screen->b, tex);
561 }
562 }
563 }
564
565 static void si_check_render_feedback_images(struct si_context *sctx,
566 struct si_images_info *images)
567 {
568 uint32_t mask = images->enabled_mask;
569
570 while (mask) {
571 const struct pipe_image_view *view;
572 struct r600_texture *tex;
573 bool render_feedback = false;
574
575 unsigned i = u_bit_scan(&mask);
576
577 view = &images->views[i];
578 if (view->resource->target == PIPE_BUFFER)
579 continue;
580
581 tex = (struct r600_texture *)view->resource;
582 if (!tex->dcc_offset)
583 continue;
584
585 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
586 struct r600_surface * surf;
587
588 if (!sctx->framebuffer.state.cbufs[j])
589 continue;
590
591 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
592
593 if (tex == (struct r600_texture*)surf->base.texture &&
594 surf->base.u.tex.level == view->u.tex.level &&
595 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
596 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
597 render_feedback = true;
598 }
599
600 if (render_feedback) {
601 struct si_screen *screen = sctx->screen;
602 r600_texture_disable_dcc(&screen->b, tex);
603 }
604 }
605 }
606
607 static void si_check_render_feedback(struct si_context *sctx)
608 {
609
610 if (!sctx->need_check_render_feedback)
611 return;
612
613 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
614 si_check_render_feedback_images(sctx, &sctx->images[i]);
615 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
616 }
617 sctx->need_check_render_feedback = false;
618 }
619
620 static void si_decompress_textures(struct si_context *sctx, int shader_start,
621 int shader_end)
622 {
623 unsigned compressed_colortex_counter;
624
625 if (sctx->blitter->running)
626 return;
627
628 /* Update the compressed_colortex_mask if necessary. */
629 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
630 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
631 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
632 si_update_compressed_colortex_masks(sctx);
633 }
634
635 /* Flush depth textures which need to be flushed. */
636 for (int i = shader_start; i < shader_end; i++) {
637 if (sctx->samplers[i].depth_texture_mask) {
638 si_flush_depth_textures(sctx, &sctx->samplers[i]);
639 }
640 if (sctx->samplers[i].compressed_colortex_mask) {
641 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
642 }
643 if (sctx->images[i].compressed_colortex_mask) {
644 si_decompress_image_color_textures(sctx, &sctx->images[i]);
645 }
646 }
647
648 si_check_render_feedback(sctx);
649 }
650
651 void si_decompress_graphics_textures(struct si_context *sctx)
652 {
653 si_decompress_textures(sctx, 0, SI_NUM_GRAPHICS_SHADERS);
654 }
655
656 void si_decompress_compute_textures(struct si_context *sctx)
657 {
658 si_decompress_textures(sctx, SI_NUM_GRAPHICS_SHADERS, SI_NUM_SHADERS);
659 }
660
661 static void si_clear(struct pipe_context *ctx, unsigned buffers,
662 const union pipe_color_union *color,
663 double depth, unsigned stencil)
664 {
665 struct si_context *sctx = (struct si_context *)ctx;
666 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
667 struct pipe_surface *zsbuf = fb->zsbuf;
668 struct r600_texture *zstex =
669 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
670
671 if (buffers & PIPE_CLEAR_COLOR) {
672 evergreen_do_fast_color_clear(&sctx->b, fb,
673 &sctx->framebuffer.atom, &buffers,
674 &sctx->framebuffer.dirty_cbufs,
675 color);
676 if (!buffers)
677 return; /* all buffers have been fast cleared */
678 }
679
680 if (buffers & PIPE_CLEAR_COLOR) {
681 int i;
682
683 /* These buffers cannot use fast clear, make sure to disable expansion. */
684 for (i = 0; i < fb->nr_cbufs; i++) {
685 struct r600_texture *tex;
686
687 /* If not clearing this buffer, skip. */
688 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
689 continue;
690
691 if (!fb->cbufs[i])
692 continue;
693
694 tex = (struct r600_texture *)fb->cbufs[i]->texture;
695 if (tex->fmask.size == 0)
696 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
697 }
698 }
699
700 if (zstex && zstex->htile_buffer &&
701 zsbuf->u.tex.level == 0 &&
702 zsbuf->u.tex.first_layer == 0 &&
703 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
704 if (buffers & PIPE_CLEAR_DEPTH) {
705 /* Need to disable EXPCLEAR temporarily if clearing
706 * to a new value. */
707 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
708 sctx->db_depth_disable_expclear = true;
709 }
710
711 zstex->depth_clear_value = depth;
712 sctx->framebuffer.dirty_zsbuf = true;
713 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
714 sctx->db_depth_clear = true;
715 si_mark_atom_dirty(sctx, &sctx->db_render_state);
716 }
717
718 if (buffers & PIPE_CLEAR_STENCIL) {
719 stencil &= 0xff;
720
721 /* Need to disable EXPCLEAR temporarily if clearing
722 * to a new value. */
723 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
724 sctx->db_stencil_disable_expclear = true;
725 }
726
727 zstex->stencil_clear_value = stencil;
728 sctx->framebuffer.dirty_zsbuf = true;
729 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
730 sctx->db_stencil_clear = true;
731 si_mark_atom_dirty(sctx, &sctx->db_render_state);
732 }
733 }
734
735 si_blitter_begin(ctx, SI_CLEAR);
736 util_blitter_clear(sctx->blitter, fb->width, fb->height,
737 util_framebuffer_get_num_layers(fb),
738 buffers, color, depth, stencil);
739 si_blitter_end(ctx);
740
741 if (sctx->db_depth_clear) {
742 sctx->db_depth_clear = false;
743 sctx->db_depth_disable_expclear = false;
744 zstex->depth_cleared = true;
745 si_mark_atom_dirty(sctx, &sctx->db_render_state);
746 }
747
748 if (sctx->db_stencil_clear) {
749 sctx->db_stencil_clear = false;
750 sctx->db_stencil_disable_expclear = false;
751 zstex->stencil_cleared = true;
752 si_mark_atom_dirty(sctx, &sctx->db_render_state);
753 }
754 }
755
756 static void si_clear_render_target(struct pipe_context *ctx,
757 struct pipe_surface *dst,
758 const union pipe_color_union *color,
759 unsigned dstx, unsigned dsty,
760 unsigned width, unsigned height)
761 {
762 struct si_context *sctx = (struct si_context *)ctx;
763
764 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
765 util_blitter_clear_render_target(sctx->blitter, dst, color,
766 dstx, dsty, width, height);
767 si_blitter_end(ctx);
768 }
769
770 static void si_clear_depth_stencil(struct pipe_context *ctx,
771 struct pipe_surface *dst,
772 unsigned clear_flags,
773 double depth,
774 unsigned stencil,
775 unsigned dstx, unsigned dsty,
776 unsigned width, unsigned height)
777 {
778 struct si_context *sctx = (struct si_context *)ctx;
779
780 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
781 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
782 dstx, dsty, width, height);
783 si_blitter_end(ctx);
784 }
785
786 /* Helper for decompressing a portion of a color or depth resource before
787 * blitting if any decompression is needed.
788 * The driver doesn't decompress resources automatically while u_blitter is
789 * rendering. */
790 static void si_decompress_subresource(struct pipe_context *ctx,
791 struct pipe_resource *tex,
792 unsigned planes, unsigned level,
793 unsigned first_layer, unsigned last_layer)
794 {
795 struct si_context *sctx = (struct si_context *)ctx;
796 struct r600_texture *rtex = (struct r600_texture*)tex;
797
798 if (rtex->db_compatible) {
799 planes &= PIPE_MASK_Z | PIPE_MASK_S;
800
801 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
802 planes &= ~PIPE_MASK_S;
803
804 si_flush_depth_texture(sctx, rtex, planes,
805 level, level,
806 first_layer, last_layer);
807 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
808 si_blit_decompress_color(ctx, rtex, level, level,
809 first_layer, last_layer, false);
810 }
811 }
812
813 struct texture_orig_info {
814 unsigned format;
815 unsigned width0;
816 unsigned height0;
817 unsigned npix_x;
818 unsigned npix_y;
819 unsigned npix0_x;
820 unsigned npix0_y;
821 };
822
823 void si_resource_copy_region(struct pipe_context *ctx,
824 struct pipe_resource *dst,
825 unsigned dst_level,
826 unsigned dstx, unsigned dsty, unsigned dstz,
827 struct pipe_resource *src,
828 unsigned src_level,
829 const struct pipe_box *src_box)
830 {
831 struct si_context *sctx = (struct si_context *)ctx;
832 struct pipe_surface *dst_view, dst_templ;
833 struct pipe_sampler_view src_templ, *src_view;
834 unsigned dst_width, dst_height, src_width0, src_height0;
835 unsigned src_force_level = 0;
836 struct pipe_box sbox, dstbox;
837
838 /* Handle buffers first. */
839 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
840 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
841 return;
842 }
843
844 assert(u_max_sample(dst) == u_max_sample(src));
845
846 /* The driver doesn't decompress resources automatically while
847 * u_blitter is rendering. */
848 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
849 src_box->z, src_box->z + src_box->depth - 1);
850
851 dst_width = u_minify(dst->width0, dst_level);
852 dst_height = u_minify(dst->height0, dst_level);
853 src_width0 = src->width0;
854 src_height0 = src->height0;
855
856 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
857 util_blitter_default_src_texture(&src_templ, src, src_level);
858
859 if (util_format_is_compressed(src->format) ||
860 util_format_is_compressed(dst->format)) {
861 unsigned blocksize = util_format_get_blocksize(src->format);
862
863 if (blocksize == 8)
864 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
865 else
866 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
867 dst_templ.format = src_templ.format;
868
869 dst_width = util_format_get_nblocksx(dst->format, dst_width);
870 dst_height = util_format_get_nblocksy(dst->format, dst_height);
871 src_width0 = util_format_get_nblocksx(src->format, src_width0);
872 src_height0 = util_format_get_nblocksy(src->format, src_height0);
873
874 dstx = util_format_get_nblocksx(dst->format, dstx);
875 dsty = util_format_get_nblocksy(dst->format, dsty);
876
877 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
878 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
879 sbox.z = src_box->z;
880 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
881 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
882 sbox.depth = src_box->depth;
883 src_box = &sbox;
884
885 src_force_level = src_level;
886 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src) ||
887 /* also *8_SNORM has precision issues, use UNORM instead */
888 util_format_is_snorm8(src->format)) {
889 if (util_format_is_subsampled_422(src->format)) {
890 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
891 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
892
893 dst_width = util_format_get_nblocksx(dst->format, dst_width);
894 src_width0 = util_format_get_nblocksx(src->format, src_width0);
895
896 dstx = util_format_get_nblocksx(dst->format, dstx);
897
898 sbox = *src_box;
899 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
900 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
901 src_box = &sbox;
902 } else {
903 unsigned blocksize = util_format_get_blocksize(src->format);
904
905 switch (blocksize) {
906 case 1:
907 dst_templ.format = PIPE_FORMAT_R8_UNORM;
908 src_templ.format = PIPE_FORMAT_R8_UNORM;
909 break;
910 case 2:
911 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
912 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
913 break;
914 case 4:
915 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
916 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
917 break;
918 case 8:
919 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
920 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
921 break;
922 case 16:
923 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
924 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
925 break;
926 default:
927 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
928 util_format_short_name(src->format), blocksize);
929 assert(0);
930 }
931 }
932 }
933
934 /* Initialize the surface. */
935 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
936 dst_width, dst_height);
937
938 /* Initialize the sampler view. */
939 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
940 src_width0, src_height0,
941 src_force_level);
942
943 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
944 abs(src_box->depth), &dstbox);
945
946 /* Copy. */
947 si_blitter_begin(ctx, SI_COPY);
948 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
949 src_view, src_box, src_width0, src_height0,
950 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
951 false);
952 si_blitter_end(ctx);
953
954 pipe_surface_reference(&dst_view, NULL);
955 pipe_sampler_view_reference(&src_view, NULL);
956 }
957
958 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
959 const struct pipe_blit_info *info)
960 {
961 struct si_context *sctx = (struct si_context*)ctx;
962 struct r600_texture *src = (struct r600_texture*)info->src.resource;
963 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
964 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
965 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
966 enum pipe_format format = info->src.format;
967 unsigned sample_mask = ~0;
968 struct pipe_resource *tmp, templ;
969 struct pipe_blit_info blit;
970
971 /* Check basic requirements for hw resolve. */
972 if (!(info->src.resource->nr_samples > 1 &&
973 info->dst.resource->nr_samples <= 1 &&
974 !util_format_is_pure_integer(format) &&
975 !util_format_is_depth_or_stencil(format) &&
976 util_max_layer(info->src.resource, 0) == 0))
977 return false;
978
979 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
980 * the format is R16G16. Use R16A16, which does work.
981 */
982 if (format == PIPE_FORMAT_R16G16_UNORM)
983 format = PIPE_FORMAT_R16A16_UNORM;
984 if (format == PIPE_FORMAT_R16G16_SNORM)
985 format = PIPE_FORMAT_R16A16_SNORM;
986
987 /* Check the remaining requirements for hw resolve. */
988 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
989 !info->scissor_enable &&
990 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
991 util_is_format_compatible(util_format_description(info->src.format),
992 util_format_description(info->dst.format)) &&
993 dst_width == info->src.resource->width0 &&
994 dst_height == info->src.resource->height0 &&
995 info->dst.box.x == 0 &&
996 info->dst.box.y == 0 &&
997 info->dst.box.width == dst_width &&
998 info->dst.box.height == dst_height &&
999 info->dst.box.depth == 1 &&
1000 info->src.box.x == 0 &&
1001 info->src.box.y == 0 &&
1002 info->src.box.width == dst_width &&
1003 info->src.box.height == dst_height &&
1004 info->src.box.depth == 1 &&
1005 dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
1006 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1007 /* Check the last constraint. */
1008 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1009 /* The next fast clear will switch to this mode to
1010 * get direct hw resolve next time if the mode is
1011 * different now.
1012 */
1013 src->last_msaa_resolve_target_micro_mode =
1014 dst->surface.micro_tile_mode;
1015 goto resolve_to_temp;
1016 }
1017
1018 /* Resolving into a surface with DCC is unsupported. Since
1019 * it's being overwritten anyway, clear it to uncompressed.
1020 * This is still the fastest codepath even with this clear.
1021 */
1022 if (dst->dcc_offset &&
1023 dst->surface.level[info->dst.level].dcc_enabled) {
1024 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1025 0xFFFFFFFF);
1026 dst->dirty_level_mask &= ~(1 << info->dst.level);
1027 }
1028
1029 /* Resolve directly from src to dst. */
1030 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1031 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1032 util_blitter_custom_resolve_color(sctx->blitter,
1033 info->dst.resource, info->dst.level,
1034 info->dst.box.z,
1035 info->src.resource, info->src.box.z,
1036 sample_mask, sctx->custom_blend_resolve,
1037 format);
1038 si_blitter_end(ctx);
1039 return true;
1040 }
1041
1042 resolve_to_temp:
1043 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1044 * a temporary texture and blit.
1045 */
1046 memset(&templ, 0, sizeof(templ));
1047 templ.target = PIPE_TEXTURE_2D;
1048 templ.format = info->src.resource->format;
1049 templ.width0 = info->src.resource->width0;
1050 templ.height0 = info->src.resource->height0;
1051 templ.depth0 = 1;
1052 templ.array_size = 1;
1053 templ.usage = PIPE_USAGE_DEFAULT;
1054 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1055 R600_RESOURCE_FLAG_DISABLE_DCC;
1056
1057 /* The src and dst microtile modes must be the same. */
1058 if (src->surface.micro_tile_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING)
1059 templ.bind = PIPE_BIND_SCANOUT;
1060 else
1061 templ.bind = 0;
1062
1063 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1064 if (!tmp)
1065 return false;
1066
1067 assert(src->surface.micro_tile_mode ==
1068 ((struct r600_texture*)tmp)->surface.micro_tile_mode);
1069
1070 /* resolve */
1071 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1072 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1073 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
1074 info->src.resource, info->src.box.z,
1075 sample_mask, sctx->custom_blend_resolve,
1076 format);
1077 si_blitter_end(ctx);
1078
1079 /* blit */
1080 blit = *info;
1081 blit.src.resource = tmp;
1082 blit.src.box.z = 0;
1083
1084 si_blitter_begin(ctx, SI_BLIT |
1085 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1086 util_blitter_blit(sctx->blitter, &blit);
1087 si_blitter_end(ctx);
1088
1089 pipe_resource_reference(&tmp, NULL);
1090 return true;
1091 }
1092
1093 static void si_blit(struct pipe_context *ctx,
1094 const struct pipe_blit_info *info)
1095 {
1096 struct si_context *sctx = (struct si_context*)ctx;
1097
1098 if (do_hardware_msaa_resolve(ctx, info)) {
1099 return;
1100 }
1101
1102 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1103
1104 /* The driver doesn't decompress resources automatically while
1105 * u_blitter is rendering. */
1106 si_decompress_subresource(ctx, info->src.resource, info->mask,
1107 info->src.level,
1108 info->src.box.z,
1109 info->src.box.z + info->src.box.depth - 1);
1110
1111 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1112 util_try_blit_via_copy_region(ctx, info))
1113 return;
1114
1115 si_blitter_begin(ctx, SI_BLIT |
1116 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1117 util_blitter_blit(sctx->blitter, info);
1118 si_blitter_end(ctx);
1119 }
1120
1121 static boolean si_generate_mipmap(struct pipe_context *ctx,
1122 struct pipe_resource *tex,
1123 enum pipe_format format,
1124 unsigned base_level, unsigned last_level,
1125 unsigned first_layer, unsigned last_layer)
1126 {
1127 struct si_context *sctx = (struct si_context*)ctx;
1128 struct r600_texture *rtex = (struct r600_texture *)tex;
1129
1130 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1131 return false;
1132
1133 /* The driver doesn't decompress resources automatically while
1134 * u_blitter is rendering. */
1135 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1136 base_level, first_layer, last_layer);
1137
1138 /* Clear dirty_level_mask for the levels that will be overwritten. */
1139 assert(base_level < last_level);
1140 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1141 last_level - base_level);
1142
1143 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1144 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1145 base_level, last_level,
1146 first_layer, last_layer);
1147 si_blitter_end(ctx);
1148 return true;
1149 }
1150
1151 static void si_flush_resource(struct pipe_context *ctx,
1152 struct pipe_resource *res)
1153 {
1154 struct r600_texture *rtex = (struct r600_texture*)res;
1155
1156 assert(res->target != PIPE_BUFFER);
1157 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1158
1159 /* st/dri calls flush twice per frame (not a bug), this prevents double
1160 * decompression. */
1161 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1162 return;
1163
1164 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1165 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1166 0, util_max_layer(res, 0),
1167 rtex->dcc_separate_buffer != NULL);
1168 }
1169
1170 /* Always do the analysis even if DCC is disabled at the moment. */
1171 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1172 rtex->separate_dcc_dirty = false;
1173 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1174 }
1175 }
1176
1177 static void si_decompress_dcc(struct pipe_context *ctx,
1178 struct r600_texture *rtex)
1179 {
1180 if (!rtex->dcc_offset)
1181 return;
1182
1183 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1184 0, util_max_layer(&rtex->resource.b.b, 0),
1185 true);
1186 }
1187
1188 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1189 struct pipe_resource *dst,
1190 unsigned offset, unsigned size,
1191 const void *clear_value_ptr,
1192 int clear_value_size)
1193 {
1194 struct si_context *sctx = (struct si_context*)ctx;
1195 uint32_t dword_value;
1196 unsigned i;
1197
1198 assert(offset % clear_value_size == 0);
1199 assert(size % clear_value_size == 0);
1200
1201 if (clear_value_size > 4) {
1202 const uint32_t *u32 = clear_value_ptr;
1203 bool clear_dword_duplicated = true;
1204
1205 /* See if we can lower large fills to dword fills. */
1206 for (i = 1; i < clear_value_size / 4; i++)
1207 if (u32[0] != u32[i]) {
1208 clear_dword_duplicated = false;
1209 break;
1210 }
1211
1212 if (!clear_dword_duplicated) {
1213 /* Use transform feedback for 64-bit, 96-bit, and
1214 * 128-bit fills.
1215 */
1216 union pipe_color_union clear_value;
1217
1218 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1219 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1220 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1221 size, clear_value_size / 4,
1222 &clear_value);
1223 si_blitter_end(ctx);
1224 return;
1225 }
1226 }
1227
1228 /* Expand the clear value to a dword. */
1229 switch (clear_value_size) {
1230 case 1:
1231 dword_value = *(uint8_t*)clear_value_ptr;
1232 dword_value |= (dword_value << 8) |
1233 (dword_value << 16) |
1234 (dword_value << 24);
1235 break;
1236 case 2:
1237 dword_value = *(uint16_t*)clear_value_ptr;
1238 dword_value |= dword_value << 16;
1239 break;
1240 default:
1241 dword_value = *(uint32_t*)clear_value_ptr;
1242 }
1243
1244 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1245 R600_COHERENCY_SHADER);
1246 }
1247
1248 void si_init_blit_functions(struct si_context *sctx)
1249 {
1250 sctx->b.b.clear = si_clear;
1251 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1252 sctx->b.b.clear_render_target = si_clear_render_target;
1253 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1254 sctx->b.b.resource_copy_region = si_resource_copy_region;
1255 sctx->b.b.blit = si_blit;
1256 sctx->b.b.flush_resource = si_flush_resource;
1257 sctx->b.b.generate_mipmap = si_generate_mipmap;
1258 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1259 sctx->b.decompress_dcc = si_decompress_dcc;
1260 }