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radeonsi: extract DB->CB copy logic into its own function
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "util/u_format.h"
27 #include "util/u_surface.h"
28
29 enum si_blitter_op /* bitmask */
30 {
31 SI_SAVE_TEXTURES = 1,
32 SI_SAVE_FRAMEBUFFER = 2,
33 SI_SAVE_FRAGMENT_STATE = 4,
34 SI_DISABLE_RENDER_COND = 8,
35
36 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
37
38 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
39
40 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
41 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
42
43 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
44 SI_SAVE_FRAGMENT_STATE,
45
46 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
47 SI_DISABLE_RENDER_COND,
48
49 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
50 };
51
52 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
53 {
54 struct si_context *sctx = (struct si_context *)ctx;
55
56 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
57 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
58 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
59 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
60 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
61 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
62 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
63 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
64 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
65
66 if (op & SI_SAVE_FRAGMENT_STATE) {
67 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
68 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
69 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
70 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
71 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
72 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
73 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
74 }
75
76 if (op & SI_SAVE_FRAMEBUFFER)
77 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
78
79 if (op & SI_SAVE_TEXTURES) {
80 util_blitter_save_fragment_sampler_states(
81 sctx->blitter, 2,
82 sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
83
84 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
85 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
86 }
87
88 if (op & SI_DISABLE_RENDER_COND)
89 sctx->b.render_cond_force_off = true;
90 }
91
92 static void si_blitter_end(struct pipe_context *ctx)
93 {
94 struct si_context *sctx = (struct si_context *)ctx;
95
96 sctx->b.render_cond_force_off = false;
97 }
98
99 static unsigned u_max_sample(struct pipe_resource *r)
100 {
101 return r->nr_samples ? r->nr_samples - 1 : 0;
102 }
103
104 static void
105 si_blit_dbcb_copy(struct si_context *sctx,
106 struct r600_texture *src,
107 struct r600_texture *dst,
108 unsigned planes, unsigned level_mask,
109 unsigned first_layer, unsigned last_layer,
110 unsigned first_sample, unsigned last_sample)
111 {
112 struct pipe_surface surf_tmpl = {{0}};
113 unsigned layer, sample, checked_last_layer, max_layer;
114
115 if (planes & PIPE_MASK_Z)
116 sctx->dbcb_depth_copy_enabled = true;
117 if (planes & PIPE_MASK_S)
118 sctx->dbcb_stencil_copy_enabled = true;
119 si_mark_atom_dirty(sctx, &sctx->db_render_state);
120
121 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
122
123 while (level_mask) {
124 unsigned level = u_bit_scan(&level_mask);
125
126 /* The smaller the mipmap level, the less layers there are
127 * as far as 3D textures are concerned. */
128 max_layer = util_max_layer(&src->resource.b.b, level);
129 checked_last_layer = MIN2(last_layer, max_layer);
130
131 surf_tmpl.u.tex.level = level;
132
133 for (layer = first_layer; layer <= checked_last_layer; layer++) {
134 struct pipe_surface *zsurf, *cbsurf;
135
136 surf_tmpl.format = src->resource.b.b.format;
137 surf_tmpl.u.tex.first_layer = layer;
138 surf_tmpl.u.tex.last_layer = layer;
139
140 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
141
142 surf_tmpl.format = dst->resource.b.b.format;
143 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
144
145 for (sample = first_sample; sample <= last_sample; sample++) {
146 if (sample != sctx->dbcb_copy_sample) {
147 sctx->dbcb_copy_sample = sample;
148 si_mark_atom_dirty(sctx, &sctx->db_render_state);
149 }
150
151 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
152 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
153 sctx->custom_dsa_flush, 1.0f);
154 si_blitter_end(&sctx->b.b);
155 }
156
157 pipe_surface_reference(&zsurf, NULL);
158 pipe_surface_reference(&cbsurf, NULL);
159 }
160 }
161
162 sctx->dbcb_depth_copy_enabled = false;
163 sctx->dbcb_stencil_copy_enabled = false;
164 si_mark_atom_dirty(sctx, &sctx->db_render_state);
165 }
166
167 static void si_blit_decompress_depth(struct pipe_context *ctx,
168 struct r600_texture *texture,
169 struct r600_texture *staging,
170 unsigned first_level, unsigned last_level,
171 unsigned first_layer, unsigned last_layer,
172 unsigned first_sample, unsigned last_sample)
173 {
174 const struct util_format_description *desc;
175 unsigned planes = 0;
176
177 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
178
179 desc = util_format_description(staging->resource.b.b.format);
180
181 if (util_format_has_depth(desc))
182 planes |= PIPE_MASK_Z;
183 if (util_format_has_stencil(desc))
184 planes |= PIPE_MASK_S;
185
186 si_blit_dbcb_copy(
187 (struct si_context *)ctx, texture, staging, planes,
188 u_bit_consecutive(first_level, last_level - first_level + 1),
189 first_layer, last_layer, first_sample, last_sample);
190 }
191
192 /* Helper function for si_blit_decompress_zs_in_place.
193 */
194 static void
195 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
196 struct r600_texture *texture,
197 unsigned planes, unsigned level_mask,
198 unsigned first_layer, unsigned last_layer)
199 {
200 struct pipe_surface *zsurf, surf_tmpl = {{0}};
201 unsigned layer, max_layer, checked_last_layer;
202 unsigned fully_decompressed_mask = 0;
203
204 if (!level_mask)
205 return;
206
207 if (planes & PIPE_MASK_S)
208 sctx->db_flush_stencil_inplace = true;
209 if (planes & PIPE_MASK_Z)
210 sctx->db_flush_depth_inplace = true;
211 si_mark_atom_dirty(sctx, &sctx->db_render_state);
212
213 surf_tmpl.format = texture->resource.b.b.format;
214
215 while (level_mask) {
216 unsigned level = u_bit_scan(&level_mask);
217
218 surf_tmpl.u.tex.level = level;
219
220 /* The smaller the mipmap level, the less layers there are
221 * as far as 3D textures are concerned. */
222 max_layer = util_max_layer(&texture->resource.b.b, level);
223 checked_last_layer = MIN2(last_layer, max_layer);
224
225 for (layer = first_layer; layer <= checked_last_layer; layer++) {
226 surf_tmpl.u.tex.first_layer = layer;
227 surf_tmpl.u.tex.last_layer = layer;
228
229 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
230
231 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
232 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
233 sctx->custom_dsa_flush,
234 1.0f);
235 si_blitter_end(&sctx->b.b);
236
237 pipe_surface_reference(&zsurf, NULL);
238 }
239
240 /* The texture will always be dirty if some layers aren't flushed.
241 * I don't think this case occurs often though. */
242 if (first_layer == 0 && last_layer >= max_layer) {
243 fully_decompressed_mask |= 1u << level;
244 }
245 }
246
247 if (planes & PIPE_MASK_Z)
248 texture->dirty_level_mask &= ~fully_decompressed_mask;
249 if (planes & PIPE_MASK_S)
250 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
251
252 sctx->db_flush_depth_inplace = false;
253 sctx->db_flush_stencil_inplace = false;
254 si_mark_atom_dirty(sctx, &sctx->db_render_state);
255 }
256
257 /* Decompress Z and/or S planes in place, depending on mask.
258 */
259 static void
260 si_blit_decompress_zs_in_place(struct si_context *sctx,
261 struct r600_texture *texture,
262 unsigned planes,
263 unsigned first_level, unsigned last_level,
264 unsigned first_layer, unsigned last_layer)
265 {
266 unsigned level_mask =
267 u_bit_consecutive(first_level, last_level - first_level + 1);
268 unsigned cur_level_mask;
269
270 /* First, do combined Z & S decompresses for levels that need it. */
271 if (planes == (PIPE_MASK_Z | PIPE_MASK_S)) {
272 cur_level_mask =
273 level_mask &
274 texture->dirty_level_mask &
275 texture->stencil_dirty_level_mask;
276 si_blit_decompress_zs_planes_in_place(
277 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
278 cur_level_mask,
279 first_layer, last_layer);
280 level_mask &= ~cur_level_mask;
281 }
282
283 /* Now do separate Z and S decompresses. */
284 if (planes & PIPE_MASK_Z) {
285 cur_level_mask = level_mask & texture->dirty_level_mask;
286 si_blit_decompress_zs_planes_in_place(
287 sctx, texture, PIPE_MASK_Z,
288 cur_level_mask,
289 first_layer, last_layer);
290 level_mask &= ~cur_level_mask;
291 }
292
293 if (planes & PIPE_MASK_S) {
294 cur_level_mask = level_mask & texture->stencil_dirty_level_mask;
295 si_blit_decompress_zs_planes_in_place(
296 sctx, texture, PIPE_MASK_S,
297 cur_level_mask,
298 first_layer, last_layer);
299 }
300 }
301
302 static void
303 si_flush_depth_textures(struct si_context *sctx,
304 struct si_textures_info *textures)
305 {
306 unsigned i;
307 unsigned mask = textures->depth_texture_mask;
308
309 while (mask) {
310 struct pipe_sampler_view *view;
311 struct si_sampler_view *sview;
312 struct r600_texture *tex;
313
314 i = u_bit_scan(&mask);
315
316 view = textures->views.views[i];
317 assert(view);
318 sview = (struct si_sampler_view*)view;
319
320 tex = (struct r600_texture *)view->texture;
321 assert(tex->db_compatible);
322
323 si_blit_decompress_zs_in_place(sctx, tex,
324 sview->is_stencil_sampler ? PIPE_MASK_S
325 : PIPE_MASK_Z,
326 view->u.tex.first_level, view->u.tex.last_level,
327 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
328 }
329 }
330
331 static void si_blit_decompress_color(struct pipe_context *ctx,
332 struct r600_texture *rtex,
333 unsigned first_level, unsigned last_level,
334 unsigned first_layer, unsigned last_layer,
335 bool need_dcc_decompress)
336 {
337 struct si_context *sctx = (struct si_context *)ctx;
338 void* custom_blend;
339 unsigned layer, checked_last_layer, max_layer;
340 unsigned level_mask =
341 u_bit_consecutive(first_level, last_level - first_level + 1);
342
343 if (!need_dcc_decompress)
344 level_mask &= rtex->dirty_level_mask;
345 if (!level_mask)
346 return;
347
348 if (rtex->dcc_offset && need_dcc_decompress) {
349 custom_blend = sctx->custom_blend_dcc_decompress;
350
351 /* disable levels without DCC */
352 for (int i = first_level; i <= last_level; i++) {
353 if (!rtex->dcc_offset ||
354 !rtex->surface.level[i].dcc_enabled)
355 level_mask &= ~(1 << i);
356 }
357 } else if (rtex->fmask.size) {
358 custom_blend = sctx->custom_blend_decompress;
359 } else {
360 custom_blend = sctx->custom_blend_fastclear;
361 }
362
363 while (level_mask) {
364 unsigned level = u_bit_scan(&level_mask);
365
366 /* The smaller the mipmap level, the less layers there are
367 * as far as 3D textures are concerned. */
368 max_layer = util_max_layer(&rtex->resource.b.b, level);
369 checked_last_layer = MIN2(last_layer, max_layer);
370
371 for (layer = first_layer; layer <= checked_last_layer; layer++) {
372 struct pipe_surface *cbsurf, surf_tmpl;
373
374 surf_tmpl.format = rtex->resource.b.b.format;
375 surf_tmpl.u.tex.level = level;
376 surf_tmpl.u.tex.first_layer = layer;
377 surf_tmpl.u.tex.last_layer = layer;
378 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
379
380 si_blitter_begin(ctx, SI_DECOMPRESS);
381 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
382 si_blitter_end(ctx);
383
384 pipe_surface_reference(&cbsurf, NULL);
385 }
386
387 /* The texture will always be dirty if some layers aren't flushed.
388 * I don't think this case occurs often though. */
389 if (first_layer == 0 && last_layer >= max_layer) {
390 rtex->dirty_level_mask &= ~(1 << level);
391 }
392 }
393 }
394
395 static void
396 si_decompress_sampler_color_textures(struct si_context *sctx,
397 struct si_textures_info *textures)
398 {
399 unsigned i;
400 unsigned mask = textures->compressed_colortex_mask;
401
402 while (mask) {
403 struct pipe_sampler_view *view;
404 struct r600_texture *tex;
405
406 i = u_bit_scan(&mask);
407
408 view = textures->views.views[i];
409 assert(view);
410
411 tex = (struct r600_texture *)view->texture;
412 assert(tex->cmask.size || tex->fmask.size || tex->dcc_offset);
413
414 si_blit_decompress_color(&sctx->b.b, tex,
415 view->u.tex.first_level, view->u.tex.last_level,
416 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
417 false);
418 }
419 }
420
421 static void
422 si_decompress_image_color_textures(struct si_context *sctx,
423 struct si_images_info *images)
424 {
425 unsigned i;
426 unsigned mask = images->compressed_colortex_mask;
427
428 while (mask) {
429 const struct pipe_image_view *view;
430 struct r600_texture *tex;
431
432 i = u_bit_scan(&mask);
433
434 view = &images->views[i];
435 assert(view->resource->target != PIPE_BUFFER);
436
437 tex = (struct r600_texture *)view->resource;
438 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
439 continue;
440
441 si_blit_decompress_color(&sctx->b.b, tex,
442 view->u.tex.level, view->u.tex.level,
443 0, util_max_layer(&tex->resource.b.b, view->u.tex.level),
444 false);
445 }
446 }
447
448 static void si_check_render_feedback_textures(struct si_context *sctx,
449 struct si_textures_info *textures)
450 {
451 uint32_t mask = textures->views.enabled_mask;
452
453 while (mask) {
454 const struct pipe_sampler_view *view;
455 struct r600_texture *tex;
456 bool render_feedback = false;
457
458 unsigned i = u_bit_scan(&mask);
459
460 view = textures->views.views[i];
461 if(view->texture->target == PIPE_BUFFER)
462 continue;
463
464 tex = (struct r600_texture *)view->texture;
465 if (!tex->dcc_offset)
466 continue;
467
468 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
469 struct r600_surface * surf;
470
471 if (!sctx->framebuffer.state.cbufs[j])
472 continue;
473
474 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
475
476 if (tex == (struct r600_texture*)surf->base.texture &&
477 surf->base.u.tex.level >= view->u.tex.first_level &&
478 surf->base.u.tex.level <= view->u.tex.last_level &&
479 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
480 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
481 render_feedback = true;
482 }
483
484 if (render_feedback) {
485 struct si_screen *screen = sctx->screen;
486 r600_texture_disable_dcc(&screen->b, tex);
487 }
488 }
489 }
490
491 static void si_check_render_feedback_images(struct si_context *sctx,
492 struct si_images_info *images)
493 {
494 uint32_t mask = images->enabled_mask;
495
496 while (mask) {
497 const struct pipe_image_view *view;
498 struct r600_texture *tex;
499 bool render_feedback = false;
500
501 unsigned i = u_bit_scan(&mask);
502
503 view = &images->views[i];
504 if (view->resource->target == PIPE_BUFFER)
505 continue;
506
507 tex = (struct r600_texture *)view->resource;
508 if (!tex->dcc_offset)
509 continue;
510
511 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
512 struct r600_surface * surf;
513
514 if (!sctx->framebuffer.state.cbufs[j])
515 continue;
516
517 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
518
519 if (tex == (struct r600_texture*)surf->base.texture &&
520 surf->base.u.tex.level == view->u.tex.level &&
521 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
522 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
523 render_feedback = true;
524 }
525
526 if (render_feedback) {
527 struct si_screen *screen = sctx->screen;
528 r600_texture_disable_dcc(&screen->b, tex);
529 }
530 }
531 }
532
533 static void si_check_render_feedback(struct si_context *sctx)
534 {
535
536 if (!sctx->need_check_render_feedback)
537 return;
538
539 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
540 si_check_render_feedback_images(sctx, &sctx->images[i]);
541 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
542 }
543 sctx->need_check_render_feedback = false;
544 }
545
546 static void si_decompress_textures(struct si_context *sctx, int shader_start,
547 int shader_end)
548 {
549 unsigned compressed_colortex_counter;
550
551 if (sctx->blitter->running)
552 return;
553
554 /* Update the compressed_colortex_mask if necessary. */
555 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
556 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
557 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
558 si_update_compressed_colortex_masks(sctx);
559 }
560
561 /* Flush depth textures which need to be flushed. */
562 for (int i = shader_start; i < shader_end; i++) {
563 if (sctx->samplers[i].depth_texture_mask) {
564 si_flush_depth_textures(sctx, &sctx->samplers[i]);
565 }
566 if (sctx->samplers[i].compressed_colortex_mask) {
567 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
568 }
569 if (sctx->images[i].compressed_colortex_mask) {
570 si_decompress_image_color_textures(sctx, &sctx->images[i]);
571 }
572 }
573
574 si_check_render_feedback(sctx);
575 }
576
577 void si_decompress_graphics_textures(struct si_context *sctx)
578 {
579 si_decompress_textures(sctx, 0, SI_NUM_GRAPHICS_SHADERS);
580 }
581
582 void si_decompress_compute_textures(struct si_context *sctx)
583 {
584 si_decompress_textures(sctx, SI_NUM_GRAPHICS_SHADERS, SI_NUM_SHADERS);
585 }
586
587 static void si_clear(struct pipe_context *ctx, unsigned buffers,
588 const union pipe_color_union *color,
589 double depth, unsigned stencil)
590 {
591 struct si_context *sctx = (struct si_context *)ctx;
592 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
593 struct pipe_surface *zsbuf = fb->zsbuf;
594 struct r600_texture *zstex =
595 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
596
597 if (buffers & PIPE_CLEAR_COLOR) {
598 evergreen_do_fast_color_clear(&sctx->b, fb,
599 &sctx->framebuffer.atom, &buffers,
600 &sctx->framebuffer.dirty_cbufs,
601 color);
602 if (!buffers)
603 return; /* all buffers have been fast cleared */
604 }
605
606 if (buffers & PIPE_CLEAR_COLOR) {
607 int i;
608
609 /* These buffers cannot use fast clear, make sure to disable expansion. */
610 for (i = 0; i < fb->nr_cbufs; i++) {
611 struct r600_texture *tex;
612
613 /* If not clearing this buffer, skip. */
614 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
615 continue;
616
617 if (!fb->cbufs[i])
618 continue;
619
620 tex = (struct r600_texture *)fb->cbufs[i]->texture;
621 if (tex->fmask.size == 0)
622 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
623 }
624 }
625
626 if (zstex && zstex->htile_buffer &&
627 zsbuf->u.tex.level == 0 &&
628 zsbuf->u.tex.first_layer == 0 &&
629 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
630 if (buffers & PIPE_CLEAR_DEPTH) {
631 /* Need to disable EXPCLEAR temporarily if clearing
632 * to a new value. */
633 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
634 sctx->db_depth_disable_expclear = true;
635 }
636
637 zstex->depth_clear_value = depth;
638 sctx->framebuffer.dirty_zsbuf = true;
639 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
640 sctx->db_depth_clear = true;
641 si_mark_atom_dirty(sctx, &sctx->db_render_state);
642 }
643
644 if (buffers & PIPE_CLEAR_STENCIL) {
645 stencil &= 0xff;
646
647 /* Need to disable EXPCLEAR temporarily if clearing
648 * to a new value. */
649 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
650 sctx->db_stencil_disable_expclear = true;
651 }
652
653 zstex->stencil_clear_value = stencil;
654 sctx->framebuffer.dirty_zsbuf = true;
655 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
656 sctx->db_stencil_clear = true;
657 si_mark_atom_dirty(sctx, &sctx->db_render_state);
658 }
659 }
660
661 si_blitter_begin(ctx, SI_CLEAR);
662 util_blitter_clear(sctx->blitter, fb->width, fb->height,
663 util_framebuffer_get_num_layers(fb),
664 buffers, color, depth, stencil);
665 si_blitter_end(ctx);
666
667 if (sctx->db_depth_clear) {
668 sctx->db_depth_clear = false;
669 sctx->db_depth_disable_expclear = false;
670 zstex->depth_cleared = true;
671 si_mark_atom_dirty(sctx, &sctx->db_render_state);
672 }
673
674 if (sctx->db_stencil_clear) {
675 sctx->db_stencil_clear = false;
676 sctx->db_stencil_disable_expclear = false;
677 zstex->stencil_cleared = true;
678 si_mark_atom_dirty(sctx, &sctx->db_render_state);
679 }
680 }
681
682 static void si_clear_render_target(struct pipe_context *ctx,
683 struct pipe_surface *dst,
684 const union pipe_color_union *color,
685 unsigned dstx, unsigned dsty,
686 unsigned width, unsigned height)
687 {
688 struct si_context *sctx = (struct si_context *)ctx;
689
690 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
691 util_blitter_clear_render_target(sctx->blitter, dst, color,
692 dstx, dsty, width, height);
693 si_blitter_end(ctx);
694 }
695
696 static void si_clear_depth_stencil(struct pipe_context *ctx,
697 struct pipe_surface *dst,
698 unsigned clear_flags,
699 double depth,
700 unsigned stencil,
701 unsigned dstx, unsigned dsty,
702 unsigned width, unsigned height)
703 {
704 struct si_context *sctx = (struct si_context *)ctx;
705
706 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
707 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
708 dstx, dsty, width, height);
709 si_blitter_end(ctx);
710 }
711
712 /* Helper for decompressing a portion of a color or depth resource before
713 * blitting if any decompression is needed.
714 * The driver doesn't decompress resources automatically while u_blitter is
715 * rendering. */
716 static void si_decompress_subresource(struct pipe_context *ctx,
717 struct pipe_resource *tex,
718 unsigned planes, unsigned level,
719 unsigned first_layer, unsigned last_layer)
720 {
721 struct si_context *sctx = (struct si_context *)ctx;
722 struct r600_texture *rtex = (struct r600_texture*)tex;
723
724 if (rtex->db_compatible) {
725 planes &= PIPE_MASK_Z | PIPE_MASK_S;
726
727 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
728 planes &= ~PIPE_MASK_S;
729
730 si_blit_decompress_zs_in_place(sctx, rtex, planes,
731 level, level,
732 first_layer, last_layer);
733 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
734 si_blit_decompress_color(ctx, rtex, level, level,
735 first_layer, last_layer, false);
736 }
737 }
738
739 struct texture_orig_info {
740 unsigned format;
741 unsigned width0;
742 unsigned height0;
743 unsigned npix_x;
744 unsigned npix_y;
745 unsigned npix0_x;
746 unsigned npix0_y;
747 };
748
749 void si_resource_copy_region(struct pipe_context *ctx,
750 struct pipe_resource *dst,
751 unsigned dst_level,
752 unsigned dstx, unsigned dsty, unsigned dstz,
753 struct pipe_resource *src,
754 unsigned src_level,
755 const struct pipe_box *src_box)
756 {
757 struct si_context *sctx = (struct si_context *)ctx;
758 struct pipe_surface *dst_view, dst_templ;
759 struct pipe_sampler_view src_templ, *src_view;
760 unsigned dst_width, dst_height, src_width0, src_height0;
761 unsigned src_force_level = 0;
762 struct pipe_box sbox, dstbox;
763
764 /* Handle buffers first. */
765 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
766 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
767 return;
768 }
769
770 assert(u_max_sample(dst) == u_max_sample(src));
771
772 /* The driver doesn't decompress resources automatically while
773 * u_blitter is rendering. */
774 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
775 src_box->z, src_box->z + src_box->depth - 1);
776
777 dst_width = u_minify(dst->width0, dst_level);
778 dst_height = u_minify(dst->height0, dst_level);
779 src_width0 = src->width0;
780 src_height0 = src->height0;
781
782 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
783 util_blitter_default_src_texture(&src_templ, src, src_level);
784
785 if (util_format_is_compressed(src->format) ||
786 util_format_is_compressed(dst->format)) {
787 unsigned blocksize = util_format_get_blocksize(src->format);
788
789 if (blocksize == 8)
790 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
791 else
792 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
793 dst_templ.format = src_templ.format;
794
795 dst_width = util_format_get_nblocksx(dst->format, dst_width);
796 dst_height = util_format_get_nblocksy(dst->format, dst_height);
797 src_width0 = util_format_get_nblocksx(src->format, src_width0);
798 src_height0 = util_format_get_nblocksy(src->format, src_height0);
799
800 dstx = util_format_get_nblocksx(dst->format, dstx);
801 dsty = util_format_get_nblocksy(dst->format, dsty);
802
803 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
804 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
805 sbox.z = src_box->z;
806 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
807 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
808 sbox.depth = src_box->depth;
809 src_box = &sbox;
810
811 src_force_level = src_level;
812 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src) ||
813 /* also *8_SNORM has precision issues, use UNORM instead */
814 util_format_is_snorm8(src->format)) {
815 if (util_format_is_subsampled_422(src->format)) {
816 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
817 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
818
819 dst_width = util_format_get_nblocksx(dst->format, dst_width);
820 src_width0 = util_format_get_nblocksx(src->format, src_width0);
821
822 dstx = util_format_get_nblocksx(dst->format, dstx);
823
824 sbox = *src_box;
825 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
826 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
827 src_box = &sbox;
828 } else {
829 unsigned blocksize = util_format_get_blocksize(src->format);
830
831 switch (blocksize) {
832 case 1:
833 dst_templ.format = PIPE_FORMAT_R8_UNORM;
834 src_templ.format = PIPE_FORMAT_R8_UNORM;
835 break;
836 case 2:
837 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
838 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
839 break;
840 case 4:
841 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
842 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
843 break;
844 case 8:
845 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
846 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
847 break;
848 case 16:
849 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
850 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
851 break;
852 default:
853 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
854 util_format_short_name(src->format), blocksize);
855 assert(0);
856 }
857 }
858 }
859
860 /* Initialize the surface. */
861 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
862 dst_width, dst_height);
863
864 /* Initialize the sampler view. */
865 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
866 src_width0, src_height0,
867 src_force_level);
868
869 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
870 abs(src_box->depth), &dstbox);
871
872 /* Copy. */
873 si_blitter_begin(ctx, SI_COPY);
874 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
875 src_view, src_box, src_width0, src_height0,
876 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
877 false);
878 si_blitter_end(ctx);
879
880 pipe_surface_reference(&dst_view, NULL);
881 pipe_sampler_view_reference(&src_view, NULL);
882 }
883
884 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
885 const struct pipe_blit_info *info)
886 {
887 struct si_context *sctx = (struct si_context*)ctx;
888 struct r600_texture *src = (struct r600_texture*)info->src.resource;
889 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
890 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
891 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
892 enum pipe_format format = info->src.format;
893 unsigned sample_mask = ~0;
894 struct pipe_resource *tmp, templ;
895 struct pipe_blit_info blit;
896
897 /* Check basic requirements for hw resolve. */
898 if (!(info->src.resource->nr_samples > 1 &&
899 info->dst.resource->nr_samples <= 1 &&
900 !util_format_is_pure_integer(format) &&
901 !util_format_is_depth_or_stencil(format) &&
902 util_max_layer(info->src.resource, 0) == 0))
903 return false;
904
905 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
906 * the format is R16G16. Use R16A16, which does work.
907 */
908 if (format == PIPE_FORMAT_R16G16_UNORM)
909 format = PIPE_FORMAT_R16A16_UNORM;
910 if (format == PIPE_FORMAT_R16G16_SNORM)
911 format = PIPE_FORMAT_R16A16_SNORM;
912
913 /* Check the remaining requirements for hw resolve. */
914 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
915 !info->scissor_enable &&
916 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
917 util_is_format_compatible(util_format_description(info->src.format),
918 util_format_description(info->dst.format)) &&
919 dst_width == info->src.resource->width0 &&
920 dst_height == info->src.resource->height0 &&
921 info->dst.box.x == 0 &&
922 info->dst.box.y == 0 &&
923 info->dst.box.width == dst_width &&
924 info->dst.box.height == dst_height &&
925 info->dst.box.depth == 1 &&
926 info->src.box.x == 0 &&
927 info->src.box.y == 0 &&
928 info->src.box.width == dst_width &&
929 info->src.box.height == dst_height &&
930 info->src.box.depth == 1 &&
931 dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
932 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
933 /* Check the last constraint. */
934 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
935 /* The next fast clear will switch to this mode to
936 * get direct hw resolve next time if the mode is
937 * different now.
938 */
939 src->last_msaa_resolve_target_micro_mode =
940 dst->surface.micro_tile_mode;
941 goto resolve_to_temp;
942 }
943
944 /* Resolving into a surface with DCC is unsupported. Since
945 * it's being overwritten anyway, clear it to uncompressed.
946 * This is still the fastest codepath even with this clear.
947 */
948 if (dst->dcc_offset &&
949 dst->surface.level[info->dst.level].dcc_enabled) {
950 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
951 0xFFFFFFFF);
952 dst->dirty_level_mask &= ~(1 << info->dst.level);
953 }
954
955 /* Resolve directly from src to dst. */
956 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
957 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
958 util_blitter_custom_resolve_color(sctx->blitter,
959 info->dst.resource, info->dst.level,
960 info->dst.box.z,
961 info->src.resource, info->src.box.z,
962 sample_mask, sctx->custom_blend_resolve,
963 format);
964 si_blitter_end(ctx);
965 return true;
966 }
967
968 resolve_to_temp:
969 /* Shader-based resolve is VERY SLOW. Instead, resolve into
970 * a temporary texture and blit.
971 */
972 memset(&templ, 0, sizeof(templ));
973 templ.target = PIPE_TEXTURE_2D;
974 templ.format = info->src.resource->format;
975 templ.width0 = info->src.resource->width0;
976 templ.height0 = info->src.resource->height0;
977 templ.depth0 = 1;
978 templ.array_size = 1;
979 templ.usage = PIPE_USAGE_DEFAULT;
980 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
981 R600_RESOURCE_FLAG_DISABLE_DCC;
982
983 /* The src and dst microtile modes must be the same. */
984 if (src->surface.micro_tile_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING)
985 templ.bind = PIPE_BIND_SCANOUT;
986 else
987 templ.bind = 0;
988
989 tmp = ctx->screen->resource_create(ctx->screen, &templ);
990 if (!tmp)
991 return false;
992
993 assert(src->surface.micro_tile_mode ==
994 ((struct r600_texture*)tmp)->surface.micro_tile_mode);
995
996 /* resolve */
997 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
998 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
999 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
1000 info->src.resource, info->src.box.z,
1001 sample_mask, sctx->custom_blend_resolve,
1002 format);
1003 si_blitter_end(ctx);
1004
1005 /* blit */
1006 blit = *info;
1007 blit.src.resource = tmp;
1008 blit.src.box.z = 0;
1009
1010 si_blitter_begin(ctx, SI_BLIT |
1011 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1012 util_blitter_blit(sctx->blitter, &blit);
1013 si_blitter_end(ctx);
1014
1015 pipe_resource_reference(&tmp, NULL);
1016 return true;
1017 }
1018
1019 static void si_blit(struct pipe_context *ctx,
1020 const struct pipe_blit_info *info)
1021 {
1022 struct si_context *sctx = (struct si_context*)ctx;
1023
1024 if (do_hardware_msaa_resolve(ctx, info)) {
1025 return;
1026 }
1027
1028 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1029
1030 /* The driver doesn't decompress resources automatically while
1031 * u_blitter is rendering. */
1032 si_decompress_subresource(ctx, info->src.resource, info->mask,
1033 info->src.level,
1034 info->src.box.z,
1035 info->src.box.z + info->src.box.depth - 1);
1036
1037 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1038 util_try_blit_via_copy_region(ctx, info))
1039 return;
1040
1041 si_blitter_begin(ctx, SI_BLIT |
1042 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1043 util_blitter_blit(sctx->blitter, info);
1044 si_blitter_end(ctx);
1045 }
1046
1047 static boolean si_generate_mipmap(struct pipe_context *ctx,
1048 struct pipe_resource *tex,
1049 enum pipe_format format,
1050 unsigned base_level, unsigned last_level,
1051 unsigned first_layer, unsigned last_layer)
1052 {
1053 struct si_context *sctx = (struct si_context*)ctx;
1054 struct r600_texture *rtex = (struct r600_texture *)tex;
1055
1056 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1057 return false;
1058
1059 /* The driver doesn't decompress resources automatically while
1060 * u_blitter is rendering. */
1061 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1062 base_level, first_layer, last_layer);
1063
1064 /* Clear dirty_level_mask for the levels that will be overwritten. */
1065 assert(base_level < last_level);
1066 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1067 last_level - base_level);
1068
1069 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1070 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1071 base_level, last_level,
1072 first_layer, last_layer);
1073 si_blitter_end(ctx);
1074 return true;
1075 }
1076
1077 static void si_flush_resource(struct pipe_context *ctx,
1078 struct pipe_resource *res)
1079 {
1080 struct r600_texture *rtex = (struct r600_texture*)res;
1081
1082 assert(res->target != PIPE_BUFFER);
1083 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1084
1085 /* st/dri calls flush twice per frame (not a bug), this prevents double
1086 * decompression. */
1087 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1088 return;
1089
1090 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1091 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1092 0, util_max_layer(res, 0),
1093 rtex->dcc_separate_buffer != NULL);
1094 }
1095
1096 /* Always do the analysis even if DCC is disabled at the moment. */
1097 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1098 rtex->separate_dcc_dirty = false;
1099 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1100 }
1101 }
1102
1103 static void si_decompress_dcc(struct pipe_context *ctx,
1104 struct r600_texture *rtex)
1105 {
1106 if (!rtex->dcc_offset)
1107 return;
1108
1109 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1110 0, util_max_layer(&rtex->resource.b.b, 0),
1111 true);
1112 }
1113
1114 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1115 struct pipe_resource *dst,
1116 unsigned offset, unsigned size,
1117 const void *clear_value_ptr,
1118 int clear_value_size)
1119 {
1120 struct si_context *sctx = (struct si_context*)ctx;
1121 uint32_t dword_value;
1122 unsigned i;
1123
1124 assert(offset % clear_value_size == 0);
1125 assert(size % clear_value_size == 0);
1126
1127 if (clear_value_size > 4) {
1128 const uint32_t *u32 = clear_value_ptr;
1129 bool clear_dword_duplicated = true;
1130
1131 /* See if we can lower large fills to dword fills. */
1132 for (i = 1; i < clear_value_size / 4; i++)
1133 if (u32[0] != u32[i]) {
1134 clear_dword_duplicated = false;
1135 break;
1136 }
1137
1138 if (!clear_dword_duplicated) {
1139 /* Use transform feedback for 64-bit, 96-bit, and
1140 * 128-bit fills.
1141 */
1142 union pipe_color_union clear_value;
1143
1144 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1145 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1146 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1147 size, clear_value_size / 4,
1148 &clear_value);
1149 si_blitter_end(ctx);
1150 return;
1151 }
1152 }
1153
1154 /* Expand the clear value to a dword. */
1155 switch (clear_value_size) {
1156 case 1:
1157 dword_value = *(uint8_t*)clear_value_ptr;
1158 dword_value |= (dword_value << 8) |
1159 (dword_value << 16) |
1160 (dword_value << 24);
1161 break;
1162 case 2:
1163 dword_value = *(uint16_t*)clear_value_ptr;
1164 dword_value |= dword_value << 16;
1165 break;
1166 default:
1167 dword_value = *(uint32_t*)clear_value_ptr;
1168 }
1169
1170 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1171 R600_COHERENCY_SHADER);
1172 }
1173
1174 void si_init_blit_functions(struct si_context *sctx)
1175 {
1176 sctx->b.b.clear = si_clear;
1177 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1178 sctx->b.b.clear_render_target = si_clear_render_target;
1179 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1180 sctx->b.b.resource_copy_region = si_resource_copy_region;
1181 sctx->b.b.blit = si_blit;
1182 sctx->b.b.flush_resource = si_flush_resource;
1183 sctx->b.b.generate_mipmap = si_generate_mipmap;
1184 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1185 sctx->b.decompress_dcc = si_decompress_dcc;
1186 }