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radeonsi: use hw MSAA resolve for non-trivial resolves
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "util/u_format.h"
26 #include "util/u_surface.h"
27
28 enum si_blitter_op /* bitmask */
29 {
30 SI_SAVE_TEXTURES = 1,
31 SI_SAVE_FRAMEBUFFER = 2,
32 SI_SAVE_FRAGMENT_STATE = 4,
33 SI_DISABLE_RENDER_COND = 8,
34
35 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
36
37 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
38
39 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
40 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
41
42 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
43 SI_SAVE_FRAGMENT_STATE,
44
45 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
46 SI_DISABLE_RENDER_COND,
47
48 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
49 };
50
51 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
52 {
53 struct si_context *sctx = (struct si_context *)ctx;
54
55 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
56 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
57 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
58 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
59 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
60 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
61 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
62 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
63 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
64
65 if (op & SI_SAVE_FRAGMENT_STATE) {
66 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
67 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
68 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
69 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
70 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
71 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
72 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
73 }
74
75 if (op & SI_SAVE_FRAMEBUFFER)
76 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
77
78 if (op & SI_SAVE_TEXTURES) {
79 util_blitter_save_fragment_sampler_states(
80 sctx->blitter, 2,
81 sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
82
83 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
84 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
85 }
86
87 if (op & SI_DISABLE_RENDER_COND)
88 sctx->b.render_cond_force_off = true;
89 }
90
91 static void si_blitter_end(struct pipe_context *ctx)
92 {
93 struct si_context *sctx = (struct si_context *)ctx;
94
95 sctx->b.render_cond_force_off = false;
96 }
97
98 static unsigned u_max_sample(struct pipe_resource *r)
99 {
100 return r->nr_samples ? r->nr_samples - 1 : 0;
101 }
102
103 static void si_blit_decompress_depth(struct pipe_context *ctx,
104 struct r600_texture *texture,
105 struct r600_texture *staging,
106 unsigned first_level, unsigned last_level,
107 unsigned first_layer, unsigned last_layer,
108 unsigned first_sample, unsigned last_sample)
109 {
110 struct si_context *sctx = (struct si_context *)ctx;
111 unsigned layer, level, sample, checked_last_layer, max_layer;
112 float depth = 1.0f;
113 const struct util_format_description *desc;
114
115 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
116
117 desc = util_format_description(staging->resource.b.b.format);
118
119 if (util_format_has_depth(desc))
120 sctx->dbcb_depth_copy_enabled = true;
121 if (util_format_has_stencil(desc))
122 sctx->dbcb_stencil_copy_enabled = true;
123
124 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
125
126 for (level = first_level; level <= last_level; level++) {
127 /* The smaller the mipmap level, the less layers there are
128 * as far as 3D textures are concerned. */
129 max_layer = util_max_layer(&texture->resource.b.b, level);
130 checked_last_layer = MIN2(last_layer, max_layer);
131
132 for (layer = first_layer; layer <= checked_last_layer; layer++) {
133 for (sample = first_sample; sample <= last_sample; sample++) {
134 struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
135
136 sctx->dbcb_copy_sample = sample;
137 si_mark_atom_dirty(sctx, &sctx->db_render_state);
138
139 surf_tmpl.format = texture->resource.b.b.format;
140 surf_tmpl.u.tex.level = level;
141 surf_tmpl.u.tex.first_layer = layer;
142 surf_tmpl.u.tex.last_layer = layer;
143
144 zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl);
145
146 surf_tmpl.format = staging->resource.b.b.format;
147 cbsurf = ctx->create_surface(ctx,
148 (struct pipe_resource*)staging, &surf_tmpl);
149
150 si_blitter_begin(ctx, SI_DECOMPRESS);
151 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
152 sctx->custom_dsa_flush, depth);
153 si_blitter_end(ctx);
154
155 pipe_surface_reference(&zsurf, NULL);
156 pipe_surface_reference(&cbsurf, NULL);
157 }
158 }
159 }
160
161 sctx->dbcb_depth_copy_enabled = false;
162 sctx->dbcb_stencil_copy_enabled = false;
163 si_mark_atom_dirty(sctx, &sctx->db_render_state);
164 }
165
166 /* Helper function for si_blit_decompress_zs_in_place.
167 */
168 static void
169 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
170 struct r600_texture *texture,
171 unsigned planes, unsigned level_mask,
172 unsigned first_layer, unsigned last_layer)
173 {
174 struct pipe_surface *zsurf, surf_tmpl = {{0}};
175 unsigned layer, max_layer, checked_last_layer;
176 unsigned fully_decompressed_mask = 0;
177
178 if (!level_mask)
179 return;
180
181 if (planes & PIPE_MASK_S)
182 sctx->db_flush_stencil_inplace = true;
183 if (planes & PIPE_MASK_Z)
184 sctx->db_flush_depth_inplace = true;
185 si_mark_atom_dirty(sctx, &sctx->db_render_state);
186
187 surf_tmpl.format = texture->resource.b.b.format;
188
189 while (level_mask) {
190 unsigned level = u_bit_scan(&level_mask);
191
192 surf_tmpl.u.tex.level = level;
193
194 /* The smaller the mipmap level, the less layers there are
195 * as far as 3D textures are concerned. */
196 max_layer = util_max_layer(&texture->resource.b.b, level);
197 checked_last_layer = MIN2(last_layer, max_layer);
198
199 for (layer = first_layer; layer <= checked_last_layer; layer++) {
200 surf_tmpl.u.tex.first_layer = layer;
201 surf_tmpl.u.tex.last_layer = layer;
202
203 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
204
205 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
206 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
207 sctx->custom_dsa_flush,
208 1.0f);
209 si_blitter_end(&sctx->b.b);
210
211 pipe_surface_reference(&zsurf, NULL);
212 }
213
214 /* The texture will always be dirty if some layers aren't flushed.
215 * I don't think this case occurs often though. */
216 if (first_layer == 0 && last_layer == max_layer) {
217 fully_decompressed_mask |= 1u << level;
218 }
219 }
220
221 if (planes & PIPE_MASK_Z)
222 texture->dirty_level_mask &= ~fully_decompressed_mask;
223 if (planes & PIPE_MASK_S)
224 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
225
226 sctx->db_flush_depth_inplace = false;
227 sctx->db_flush_stencil_inplace = false;
228 si_mark_atom_dirty(sctx, &sctx->db_render_state);
229 }
230
231 /* Decompress Z and/or S planes in place, depending on mask.
232 */
233 static void
234 si_blit_decompress_zs_in_place(struct si_context *sctx,
235 struct r600_texture *texture,
236 unsigned planes,
237 unsigned first_level, unsigned last_level,
238 unsigned first_layer, unsigned last_layer)
239 {
240 unsigned level_mask =
241 u_bit_consecutive(first_level, last_level - first_level + 1);
242 unsigned cur_level_mask;
243
244 /* First, do combined Z & S decompresses for levels that need it. */
245 if (planes == (PIPE_MASK_Z | PIPE_MASK_S)) {
246 cur_level_mask =
247 level_mask &
248 texture->dirty_level_mask &
249 texture->stencil_dirty_level_mask;
250 si_blit_decompress_zs_planes_in_place(
251 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
252 cur_level_mask,
253 first_layer, last_layer);
254 level_mask &= ~cur_level_mask;
255 }
256
257 /* Now do separate Z and S decompresses. */
258 if (planes & PIPE_MASK_Z) {
259 cur_level_mask = level_mask & texture->dirty_level_mask;
260 si_blit_decompress_zs_planes_in_place(
261 sctx, texture, PIPE_MASK_Z,
262 cur_level_mask,
263 first_layer, last_layer);
264 level_mask &= ~cur_level_mask;
265 }
266
267 if (planes & PIPE_MASK_S) {
268 cur_level_mask = level_mask & texture->stencil_dirty_level_mask;
269 si_blit_decompress_zs_planes_in_place(
270 sctx, texture, PIPE_MASK_S,
271 cur_level_mask,
272 first_layer, last_layer);
273 }
274 }
275
276 static void
277 si_flush_depth_textures(struct si_context *sctx,
278 struct si_textures_info *textures)
279 {
280 unsigned i;
281 unsigned mask = textures->depth_texture_mask;
282
283 while (mask) {
284 struct pipe_sampler_view *view;
285 struct si_sampler_view *sview;
286 struct r600_texture *tex;
287
288 i = u_bit_scan(&mask);
289
290 view = textures->views.views[i];
291 assert(view);
292 sview = (struct si_sampler_view*)view;
293
294 tex = (struct r600_texture *)view->texture;
295 assert(tex->is_depth && !tex->is_flushing_texture);
296
297 si_blit_decompress_zs_in_place(sctx, tex,
298 sview->is_stencil_sampler ? PIPE_MASK_S
299 : PIPE_MASK_Z,
300 view->u.tex.first_level, view->u.tex.last_level,
301 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
302 }
303 }
304
305 static void si_blit_decompress_color(struct pipe_context *ctx,
306 struct r600_texture *rtex,
307 unsigned first_level, unsigned last_level,
308 unsigned first_layer, unsigned last_layer,
309 bool need_dcc_decompress)
310 {
311 struct si_context *sctx = (struct si_context *)ctx;
312 void* custom_blend;
313 unsigned layer, checked_last_layer, max_layer;
314 unsigned level_mask =
315 u_bit_consecutive(first_level, last_level - first_level + 1);
316
317 if (!need_dcc_decompress)
318 level_mask &= rtex->dirty_level_mask;
319 if (!level_mask)
320 return;
321
322 if (rtex->dcc_offset && need_dcc_decompress) {
323 custom_blend = sctx->custom_blend_dcc_decompress;
324 } else if (rtex->fmask.size) {
325 custom_blend = sctx->custom_blend_decompress;
326 } else {
327 custom_blend = sctx->custom_blend_fastclear;
328 }
329
330 while (level_mask) {
331 unsigned level = u_bit_scan(&level_mask);
332
333 /* The smaller the mipmap level, the less layers there are
334 * as far as 3D textures are concerned. */
335 max_layer = util_max_layer(&rtex->resource.b.b, level);
336 checked_last_layer = MIN2(last_layer, max_layer);
337
338 for (layer = first_layer; layer <= checked_last_layer; layer++) {
339 struct pipe_surface *cbsurf, surf_tmpl;
340
341 surf_tmpl.format = rtex->resource.b.b.format;
342 surf_tmpl.u.tex.level = level;
343 surf_tmpl.u.tex.first_layer = layer;
344 surf_tmpl.u.tex.last_layer = layer;
345 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
346
347 si_blitter_begin(ctx, SI_DECOMPRESS);
348 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
349 si_blitter_end(ctx);
350
351 pipe_surface_reference(&cbsurf, NULL);
352 }
353
354 /* The texture will always be dirty if some layers aren't flushed.
355 * I don't think this case occurs often though. */
356 if (first_layer == 0 && last_layer == max_layer) {
357 rtex->dirty_level_mask &= ~(1 << level);
358 }
359 }
360 }
361
362 static void
363 si_decompress_sampler_color_textures(struct si_context *sctx,
364 struct si_textures_info *textures)
365 {
366 unsigned i;
367 unsigned mask = textures->compressed_colortex_mask;
368
369 while (mask) {
370 struct pipe_sampler_view *view;
371 struct r600_texture *tex;
372
373 i = u_bit_scan(&mask);
374
375 view = textures->views.views[i];
376 assert(view);
377
378 tex = (struct r600_texture *)view->texture;
379 assert(tex->cmask.size || tex->fmask.size || tex->dcc_offset);
380
381 si_blit_decompress_color(&sctx->b.b, tex,
382 view->u.tex.first_level, view->u.tex.last_level,
383 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
384 false);
385 }
386 }
387
388 static void
389 si_decompress_image_color_textures(struct si_context *sctx,
390 struct si_images_info *images)
391 {
392 unsigned i;
393 unsigned mask = images->compressed_colortex_mask;
394
395 while (mask) {
396 const struct pipe_image_view *view;
397 struct r600_texture *tex;
398
399 i = u_bit_scan(&mask);
400
401 view = &images->views[i];
402 assert(view->resource->target != PIPE_BUFFER);
403
404 tex = (struct r600_texture *)view->resource;
405 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
406 continue;
407
408 si_blit_decompress_color(&sctx->b.b, tex,
409 view->u.tex.level, view->u.tex.level,
410 0, util_max_layer(&tex->resource.b.b, view->u.tex.level),
411 false);
412 }
413 }
414
415 static void si_check_render_feedback_textures(struct si_context *sctx,
416 struct si_textures_info *textures)
417 {
418 uint32_t mask = textures->views.desc.enabled_mask;
419
420 while (mask) {
421 const struct pipe_sampler_view *view;
422 struct r600_texture *tex;
423 bool render_feedback = false;
424
425 unsigned i = u_bit_scan(&mask);
426
427 view = textures->views.views[i];
428 if(view->texture->target == PIPE_BUFFER)
429 continue;
430
431 tex = (struct r600_texture *)view->texture;
432 if (!tex->dcc_offset)
433 continue;
434
435 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
436 struct r600_surface * surf;
437
438 if (!sctx->framebuffer.state.cbufs[j])
439 continue;
440
441 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
442
443 if (tex == (struct r600_texture*)surf->base.texture &&
444 surf->base.u.tex.level >= view->u.tex.first_level &&
445 surf->base.u.tex.level <= view->u.tex.last_level &&
446 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
447 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
448 render_feedback = true;
449 }
450
451 if (render_feedback) {
452 struct si_screen *screen = sctx->screen;
453 r600_texture_disable_dcc(&screen->b, tex);
454 }
455 }
456 }
457
458 static void si_check_render_feedback_images(struct si_context *sctx,
459 struct si_images_info *images)
460 {
461 uint32_t mask = images->desc.enabled_mask;
462
463 while (mask) {
464 const struct pipe_image_view *view;
465 struct r600_texture *tex;
466 bool render_feedback = false;
467
468 unsigned i = u_bit_scan(&mask);
469
470 view = &images->views[i];
471 if (view->resource->target == PIPE_BUFFER)
472 continue;
473
474 tex = (struct r600_texture *)view->resource;
475 if (!tex->dcc_offset)
476 continue;
477
478 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
479 struct r600_surface * surf;
480
481 if (!sctx->framebuffer.state.cbufs[j])
482 continue;
483
484 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
485
486 if (tex == (struct r600_texture*)surf->base.texture &&
487 surf->base.u.tex.level == view->u.tex.level &&
488 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
489 surf->base.u.tex.last_layer >= view->u.tex.first_layer)
490 render_feedback = true;
491 }
492
493 if (render_feedback) {
494 struct si_screen *screen = sctx->screen;
495 r600_texture_disable_dcc(&screen->b, tex);
496 }
497 }
498 }
499
500 static void si_check_render_feedback(struct si_context *sctx)
501 {
502
503 if (!sctx->need_check_render_feedback)
504 return;
505
506 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
507 si_check_render_feedback_images(sctx, &sctx->images[i]);
508 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
509 }
510 sctx->need_check_render_feedback = false;
511 }
512
513 static void si_decompress_textures(struct si_context *sctx, int shader_start,
514 int shader_end)
515 {
516 unsigned compressed_colortex_counter;
517
518 if (sctx->blitter->running)
519 return;
520
521 /* Update the compressed_colortex_mask if necessary. */
522 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
523 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
524 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
525 si_update_compressed_colortex_masks(sctx);
526 }
527
528 /* Flush depth textures which need to be flushed. */
529 for (int i = shader_start; i < shader_end; i++) {
530 if (sctx->samplers[i].depth_texture_mask) {
531 si_flush_depth_textures(sctx, &sctx->samplers[i]);
532 }
533 if (sctx->samplers[i].compressed_colortex_mask) {
534 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
535 }
536 if (sctx->images[i].compressed_colortex_mask) {
537 si_decompress_image_color_textures(sctx, &sctx->images[i]);
538 }
539 }
540
541 si_check_render_feedback(sctx);
542 }
543
544 void si_decompress_graphics_textures(struct si_context *sctx)
545 {
546 si_decompress_textures(sctx, 0, SI_NUM_GRAPHICS_SHADERS);
547 }
548
549 void si_decompress_compute_textures(struct si_context *sctx)
550 {
551 si_decompress_textures(sctx, SI_NUM_GRAPHICS_SHADERS, SI_NUM_SHADERS);
552 }
553
554 static void si_clear(struct pipe_context *ctx, unsigned buffers,
555 const union pipe_color_union *color,
556 double depth, unsigned stencil)
557 {
558 struct si_context *sctx = (struct si_context *)ctx;
559 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
560 struct pipe_surface *zsbuf = fb->zsbuf;
561 struct r600_texture *zstex =
562 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
563
564 if (buffers & PIPE_CLEAR_COLOR) {
565 evergreen_do_fast_color_clear(&sctx->b, fb,
566 &sctx->framebuffer.atom, &buffers,
567 &sctx->framebuffer.dirty_cbufs,
568 color);
569 if (!buffers)
570 return; /* all buffers have been fast cleared */
571 }
572
573 if (buffers & PIPE_CLEAR_COLOR) {
574 int i;
575
576 /* These buffers cannot use fast clear, make sure to disable expansion. */
577 for (i = 0; i < fb->nr_cbufs; i++) {
578 struct r600_texture *tex;
579
580 /* If not clearing this buffer, skip. */
581 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
582 continue;
583
584 if (!fb->cbufs[i])
585 continue;
586
587 tex = (struct r600_texture *)fb->cbufs[i]->texture;
588 if (tex->fmask.size == 0)
589 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
590 }
591 }
592
593 if (zstex && zstex->htile_buffer &&
594 zsbuf->u.tex.level == 0 &&
595 zsbuf->u.tex.first_layer == 0 &&
596 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
597 if (buffers & PIPE_CLEAR_DEPTH) {
598 /* Need to disable EXPCLEAR temporarily if clearing
599 * to a new value. */
600 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
601 sctx->db_depth_disable_expclear = true;
602 }
603
604 zstex->depth_clear_value = depth;
605 sctx->framebuffer.dirty_zsbuf = true;
606 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
607 sctx->db_depth_clear = true;
608 si_mark_atom_dirty(sctx, &sctx->db_render_state);
609 }
610
611 if (buffers & PIPE_CLEAR_STENCIL) {
612 stencil &= 0xff;
613
614 /* Need to disable EXPCLEAR temporarily if clearing
615 * to a new value. */
616 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
617 sctx->db_stencil_disable_expclear = true;
618 }
619
620 zstex->stencil_clear_value = stencil;
621 sctx->framebuffer.dirty_zsbuf = true;
622 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
623 sctx->db_stencil_clear = true;
624 si_mark_atom_dirty(sctx, &sctx->db_render_state);
625 }
626 }
627
628 si_blitter_begin(ctx, SI_CLEAR);
629 util_blitter_clear(sctx->blitter, fb->width, fb->height,
630 util_framebuffer_get_num_layers(fb),
631 buffers, color, depth, stencil);
632 si_blitter_end(ctx);
633
634 if (sctx->db_depth_clear) {
635 sctx->db_depth_clear = false;
636 sctx->db_depth_disable_expclear = false;
637 zstex->depth_cleared = true;
638 si_mark_atom_dirty(sctx, &sctx->db_render_state);
639 }
640
641 if (sctx->db_stencil_clear) {
642 sctx->db_stencil_clear = false;
643 sctx->db_stencil_disable_expclear = false;
644 zstex->stencil_cleared = true;
645 si_mark_atom_dirty(sctx, &sctx->db_render_state);
646 }
647 }
648
649 static void si_clear_render_target(struct pipe_context *ctx,
650 struct pipe_surface *dst,
651 const union pipe_color_union *color,
652 unsigned dstx, unsigned dsty,
653 unsigned width, unsigned height)
654 {
655 struct si_context *sctx = (struct si_context *)ctx;
656
657 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
658 util_blitter_clear_render_target(sctx->blitter, dst, color,
659 dstx, dsty, width, height);
660 si_blitter_end(ctx);
661 }
662
663 static void si_clear_depth_stencil(struct pipe_context *ctx,
664 struct pipe_surface *dst,
665 unsigned clear_flags,
666 double depth,
667 unsigned stencil,
668 unsigned dstx, unsigned dsty,
669 unsigned width, unsigned height)
670 {
671 struct si_context *sctx = (struct si_context *)ctx;
672
673 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
674 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
675 dstx, dsty, width, height);
676 si_blitter_end(ctx);
677 }
678
679 /* Helper for decompressing a portion of a color or depth resource before
680 * blitting if any decompression is needed.
681 * The driver doesn't decompress resources automatically while u_blitter is
682 * rendering. */
683 static void si_decompress_subresource(struct pipe_context *ctx,
684 struct pipe_resource *tex,
685 unsigned planes, unsigned level,
686 unsigned first_layer, unsigned last_layer)
687 {
688 struct si_context *sctx = (struct si_context *)ctx;
689 struct r600_texture *rtex = (struct r600_texture*)tex;
690
691 if (rtex->is_depth && !rtex->is_flushing_texture) {
692 planes &= PIPE_MASK_Z | PIPE_MASK_S;
693
694 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
695 planes &= ~PIPE_MASK_S;
696
697 si_blit_decompress_zs_in_place(sctx, rtex, planes,
698 level, level,
699 first_layer, last_layer);
700 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
701 si_blit_decompress_color(ctx, rtex, level, level,
702 first_layer, last_layer, false);
703 }
704 }
705
706 struct texture_orig_info {
707 unsigned format;
708 unsigned width0;
709 unsigned height0;
710 unsigned npix_x;
711 unsigned npix_y;
712 unsigned npix0_x;
713 unsigned npix0_y;
714 };
715
716 void si_resource_copy_region(struct pipe_context *ctx,
717 struct pipe_resource *dst,
718 unsigned dst_level,
719 unsigned dstx, unsigned dsty, unsigned dstz,
720 struct pipe_resource *src,
721 unsigned src_level,
722 const struct pipe_box *src_box)
723 {
724 struct si_context *sctx = (struct si_context *)ctx;
725 struct pipe_surface *dst_view, dst_templ;
726 struct pipe_sampler_view src_templ, *src_view;
727 unsigned dst_width, dst_height, src_width0, src_height0;
728 unsigned src_force_level = 0;
729 struct pipe_box sbox, dstbox;
730
731 /* Handle buffers first. */
732 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
733 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
734 return;
735 }
736
737 assert(u_max_sample(dst) == u_max_sample(src));
738
739 /* The driver doesn't decompress resources automatically while
740 * u_blitter is rendering. */
741 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
742 src_box->z, src_box->z + src_box->depth - 1);
743
744 dst_width = u_minify(dst->width0, dst_level);
745 dst_height = u_minify(dst->height0, dst_level);
746 src_width0 = src->width0;
747 src_height0 = src->height0;
748
749 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
750 util_blitter_default_src_texture(&src_templ, src, src_level);
751
752 if (util_format_is_compressed(src->format) ||
753 util_format_is_compressed(dst->format)) {
754 unsigned blocksize = util_format_get_blocksize(src->format);
755
756 if (blocksize == 8)
757 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
758 else
759 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
760 dst_templ.format = src_templ.format;
761
762 dst_width = util_format_get_nblocksx(dst->format, dst_width);
763 dst_height = util_format_get_nblocksy(dst->format, dst_height);
764 src_width0 = util_format_get_nblocksx(src->format, src_width0);
765 src_height0 = util_format_get_nblocksy(src->format, src_height0);
766
767 dstx = util_format_get_nblocksx(dst->format, dstx);
768 dsty = util_format_get_nblocksy(dst->format, dsty);
769
770 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
771 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
772 sbox.z = src_box->z;
773 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
774 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
775 sbox.depth = src_box->depth;
776 src_box = &sbox;
777
778 src_force_level = src_level;
779 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src) ||
780 /* also *8_SNORM has precision issues, use UNORM instead */
781 util_format_is_snorm8(src->format)) {
782 if (util_format_is_subsampled_422(src->format)) {
783 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
784 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
785
786 dst_width = util_format_get_nblocksx(dst->format, dst_width);
787 src_width0 = util_format_get_nblocksx(src->format, src_width0);
788
789 dstx = util_format_get_nblocksx(dst->format, dstx);
790
791 sbox = *src_box;
792 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
793 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
794 src_box = &sbox;
795 } else {
796 unsigned blocksize = util_format_get_blocksize(src->format);
797
798 switch (blocksize) {
799 case 1:
800 dst_templ.format = PIPE_FORMAT_R8_UNORM;
801 src_templ.format = PIPE_FORMAT_R8_UNORM;
802 break;
803 case 2:
804 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
805 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
806 break;
807 case 4:
808 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
809 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
810 break;
811 case 8:
812 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
813 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
814 break;
815 case 16:
816 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
817 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
818 break;
819 default:
820 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
821 util_format_short_name(src->format), blocksize);
822 assert(0);
823 }
824 }
825 }
826
827 /* Initialize the surface. */
828 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
829 dst_width, dst_height);
830
831 /* Initialize the sampler view. */
832 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
833 src_width0, src_height0,
834 src_force_level);
835
836 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
837 abs(src_box->depth), &dstbox);
838
839 /* Copy. */
840 si_blitter_begin(ctx, SI_COPY);
841 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
842 src_view, src_box, src_width0, src_height0,
843 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
844 FALSE);
845 si_blitter_end(ctx);
846
847 pipe_surface_reference(&dst_view, NULL);
848 pipe_sampler_view_reference(&src_view, NULL);
849 }
850
851 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
852 const struct pipe_blit_info *info)
853 {
854 struct si_context *sctx = (struct si_context*)ctx;
855 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
856 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
857 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
858 enum pipe_format format = info->src.format;
859 unsigned sample_mask = ~0;
860 struct pipe_resource *tmp, templ;
861 struct pipe_blit_info blit;
862
863 /* Check basic requirements for hw resolve. */
864 if (!(info->src.resource->nr_samples > 1 &&
865 info->dst.resource->nr_samples <= 1 &&
866 !util_format_is_pure_integer(format) &&
867 !util_format_is_depth_or_stencil(format) &&
868 util_max_layer(info->src.resource, 0) == 0))
869 return false;
870
871 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
872 * the format is R16G16. Use R16A16, which does work.
873 */
874 if (format == PIPE_FORMAT_R16G16_UNORM)
875 format = PIPE_FORMAT_R16A16_UNORM;
876 if (format == PIPE_FORMAT_R16G16_SNORM)
877 format = PIPE_FORMAT_R16A16_SNORM;
878
879 /* Check the remaining requirements for hw resolve. */
880 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
881 !info->scissor_enable &&
882 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
883 util_is_format_compatible(util_format_description(info->src.format),
884 util_format_description(info->dst.format)) &&
885 dst_width == info->src.resource->width0 &&
886 dst_height == info->src.resource->height0 &&
887 info->dst.box.x == 0 &&
888 info->dst.box.y == 0 &&
889 info->dst.box.width == dst_width &&
890 info->dst.box.height == dst_height &&
891 info->dst.box.depth == 1 &&
892 info->src.box.x == 0 &&
893 info->src.box.y == 0 &&
894 info->src.box.width == dst_width &&
895 info->src.box.height == dst_height &&
896 info->src.box.depth == 1 &&
897 dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
898 !(dst->surface.flags & RADEON_SURF_SCANOUT) &&
899 (!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be fast-cleared */
900 !dst->dcc_offset) {
901 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
902 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
903 util_blitter_custom_resolve_color(sctx->blitter,
904 info->dst.resource, info->dst.level,
905 info->dst.box.z,
906 info->src.resource, info->src.box.z,
907 sample_mask, sctx->custom_blend_resolve,
908 format);
909 si_blitter_end(ctx);
910 return true;
911 }
912
913 /* Shader-based resolve is VERY SLOW. Instead, resolve into
914 * a temporary texture and blit.
915 */
916 memset(&templ, 0, sizeof(templ));
917 templ.target = PIPE_TEXTURE_2D;
918 templ.format = info->src.resource->format;
919 templ.width0 = info->src.resource->width0;
920 templ.height0 = info->src.resource->height0;
921 templ.depth0 = 1;
922 templ.array_size = 1;
923 templ.usage = PIPE_USAGE_DEFAULT;
924 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING;
925
926 tmp = ctx->screen->resource_create(ctx->screen, &templ);
927 if (!tmp)
928 return false;
929
930 /* resolve */
931 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
932 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
933 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
934 info->src.resource, info->src.box.z,
935 sample_mask, sctx->custom_blend_resolve,
936 format);
937 si_blitter_end(ctx);
938
939 /* blit */
940 blit = *info;
941 blit.src.resource = tmp;
942 blit.src.box.z = 0;
943
944 si_blitter_begin(ctx, SI_BLIT |
945 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
946 util_blitter_blit(sctx->blitter, &blit);
947 si_blitter_end(ctx);
948
949 pipe_resource_reference(&tmp, NULL);
950 return true;
951 }
952
953 static void si_blit(struct pipe_context *ctx,
954 const struct pipe_blit_info *info)
955 {
956 struct si_context *sctx = (struct si_context*)ctx;
957
958 if (do_hardware_msaa_resolve(ctx, info)) {
959 return;
960 }
961
962 assert(util_blitter_is_blit_supported(sctx->blitter, info));
963
964 /* The driver doesn't decompress resources automatically while
965 * u_blitter is rendering. */
966 si_decompress_subresource(ctx, info->src.resource, info->mask,
967 info->src.level,
968 info->src.box.z,
969 info->src.box.z + info->src.box.depth - 1);
970
971 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
972 util_try_blit_via_copy_region(ctx, info))
973 return;
974
975 si_blitter_begin(ctx, SI_BLIT |
976 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
977 util_blitter_blit(sctx->blitter, info);
978 si_blitter_end(ctx);
979 }
980
981 static void si_flush_resource(struct pipe_context *ctx,
982 struct pipe_resource *res)
983 {
984 struct r600_texture *rtex = (struct r600_texture*)res;
985
986 assert(res->target != PIPE_BUFFER);
987
988 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
989 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
990 0, util_max_layer(res, 0), false);
991 }
992 }
993
994 static void si_decompress_dcc(struct pipe_context *ctx,
995 struct r600_texture *rtex)
996 {
997 if (!rtex->dcc_offset)
998 return;
999
1000 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1001 0, util_max_layer(&rtex->resource.b.b, 0),
1002 true);
1003 }
1004
1005 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1006 struct pipe_resource *dst,
1007 unsigned offset, unsigned size,
1008 const void *clear_value_ptr,
1009 int clear_value_size)
1010 {
1011 struct si_context *sctx = (struct si_context*)ctx;
1012 uint32_t dword_value;
1013 unsigned i;
1014
1015 assert(offset % clear_value_size == 0);
1016 assert(size % clear_value_size == 0);
1017
1018 if (clear_value_size > 4) {
1019 const uint32_t *u32 = clear_value_ptr;
1020 bool clear_dword_duplicated = true;
1021
1022 /* See if we can lower large fills to dword fills. */
1023 for (i = 1; i < clear_value_size / 4; i++)
1024 if (u32[0] != u32[i]) {
1025 clear_dword_duplicated = false;
1026 break;
1027 }
1028
1029 if (!clear_dword_duplicated) {
1030 /* Use transform feedback for 64-bit, 96-bit, and
1031 * 128-bit fills.
1032 */
1033 union pipe_color_union clear_value;
1034
1035 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1036 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1037 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1038 size, clear_value_size / 4,
1039 &clear_value);
1040 si_blitter_end(ctx);
1041 return;
1042 }
1043 }
1044
1045 /* Expand the clear value to a dword. */
1046 switch (clear_value_size) {
1047 case 1:
1048 dword_value = *(uint8_t*)clear_value_ptr;
1049 dword_value |= (dword_value << 8) |
1050 (dword_value << 16) |
1051 (dword_value << 24);
1052 break;
1053 case 2:
1054 dword_value = *(uint16_t*)clear_value_ptr;
1055 dword_value |= dword_value << 16;
1056 break;
1057 default:
1058 dword_value = *(uint32_t*)clear_value_ptr;
1059 }
1060
1061 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1062 R600_COHERENCY_SHADER);
1063 }
1064
1065 void si_init_blit_functions(struct si_context *sctx)
1066 {
1067 sctx->b.b.clear = si_clear;
1068 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1069 sctx->b.b.clear_render_target = si_clear_render_target;
1070 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1071 sctx->b.b.resource_copy_region = si_resource_copy_region;
1072 sctx->b.b.blit = si_blit;
1073 sctx->b.b.flush_resource = si_flush_resource;
1074 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1075 sctx->b.decompress_dcc = si_decompress_dcc;
1076 }