2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_format.h"
26 #include "util/u_surface.h"
28 enum si_blitter_op
/* bitmask */
31 SI_SAVE_FRAMEBUFFER
= 2,
32 SI_SAVE_FRAGMENT_STATE
= 4,
33 SI_DISABLE_RENDER_COND
= 8,
35 SI_CLEAR
= SI_SAVE_FRAGMENT_STATE
,
37 SI_CLEAR_SURFACE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
,
39 SI_COPY
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
40 SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
42 SI_BLIT
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
43 SI_SAVE_FRAGMENT_STATE
,
45 SI_DECOMPRESS
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
|
46 SI_DISABLE_RENDER_COND
,
48 SI_COLOR_RESOLVE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
51 static void si_blitter_begin(struct pipe_context
*ctx
, enum si_blitter_op op
)
53 struct si_context
*sctx
= (struct si_context
*)ctx
;
55 util_blitter_save_vertex_buffer_slot(sctx
->blitter
, sctx
->vertex_buffer
);
56 util_blitter_save_vertex_elements(sctx
->blitter
, sctx
->vertex_elements
);
57 util_blitter_save_vertex_shader(sctx
->blitter
, sctx
->vs_shader
.cso
);
58 util_blitter_save_tessctrl_shader(sctx
->blitter
, sctx
->tcs_shader
.cso
);
59 util_blitter_save_tesseval_shader(sctx
->blitter
, sctx
->tes_shader
.cso
);
60 util_blitter_save_geometry_shader(sctx
->blitter
, sctx
->gs_shader
.cso
);
61 util_blitter_save_so_targets(sctx
->blitter
, sctx
->b
.streamout
.num_targets
,
62 (struct pipe_stream_output_target
**)sctx
->b
.streamout
.targets
);
63 util_blitter_save_rasterizer(sctx
->blitter
, sctx
->queued
.named
.rasterizer
);
65 if (op
& SI_SAVE_FRAGMENT_STATE
) {
66 util_blitter_save_blend(sctx
->blitter
, sctx
->queued
.named
.blend
);
67 util_blitter_save_depth_stencil_alpha(sctx
->blitter
, sctx
->queued
.named
.dsa
);
68 util_blitter_save_stencil_ref(sctx
->blitter
, &sctx
->stencil_ref
.state
);
69 util_blitter_save_fragment_shader(sctx
->blitter
, sctx
->ps_shader
.cso
);
70 util_blitter_save_sample_mask(sctx
->blitter
, sctx
->sample_mask
.sample_mask
);
71 util_blitter_save_viewport(sctx
->blitter
, &sctx
->b
.viewports
.states
[0]);
72 util_blitter_save_scissor(sctx
->blitter
, &sctx
->b
.scissors
.states
[0]);
75 if (op
& SI_SAVE_FRAMEBUFFER
)
76 util_blitter_save_framebuffer(sctx
->blitter
, &sctx
->framebuffer
.state
);
78 if (op
& SI_SAVE_TEXTURES
) {
79 util_blitter_save_fragment_sampler_states(
81 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.sampler_states
);
83 util_blitter_save_fragment_sampler_views(sctx
->blitter
, 2,
84 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.views
);
87 if (op
& SI_DISABLE_RENDER_COND
)
88 sctx
->b
.render_cond_force_off
= true;
91 static void si_blitter_end(struct pipe_context
*ctx
)
93 struct si_context
*sctx
= (struct si_context
*)ctx
;
95 sctx
->b
.render_cond_force_off
= false;
98 static unsigned u_max_sample(struct pipe_resource
*r
)
100 return r
->nr_samples
? r
->nr_samples
- 1 : 0;
103 static void si_blit_decompress_depth(struct pipe_context
*ctx
,
104 struct r600_texture
*texture
,
105 struct r600_texture
*staging
,
106 unsigned first_level
, unsigned last_level
,
107 unsigned first_layer
, unsigned last_layer
,
108 unsigned first_sample
, unsigned last_sample
)
110 struct si_context
*sctx
= (struct si_context
*)ctx
;
111 unsigned layer
, level
, sample
, checked_last_layer
, max_layer
;
113 const struct util_format_description
*desc
;
115 assert(staging
!= NULL
&& "use si_blit_decompress_zs_in_place instead");
117 desc
= util_format_description(staging
->resource
.b
.b
.format
);
119 if (util_format_has_depth(desc
))
120 sctx
->dbcb_depth_copy_enabled
= true;
121 if (util_format_has_stencil(desc
))
122 sctx
->dbcb_stencil_copy_enabled
= true;
124 assert(sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
);
126 for (level
= first_level
; level
<= last_level
; level
++) {
127 /* The smaller the mipmap level, the less layers there are
128 * as far as 3D textures are concerned. */
129 max_layer
= util_max_layer(&texture
->resource
.b
.b
, level
);
130 checked_last_layer
= MIN2(last_layer
, max_layer
);
132 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
133 for (sample
= first_sample
; sample
<= last_sample
; sample
++) {
134 struct pipe_surface
*zsurf
, *cbsurf
, surf_tmpl
;
136 sctx
->dbcb_copy_sample
= sample
;
137 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
139 surf_tmpl
.format
= texture
->resource
.b
.b
.format
;
140 surf_tmpl
.u
.tex
.level
= level
;
141 surf_tmpl
.u
.tex
.first_layer
= layer
;
142 surf_tmpl
.u
.tex
.last_layer
= layer
;
144 zsurf
= ctx
->create_surface(ctx
, &texture
->resource
.b
.b
, &surf_tmpl
);
146 surf_tmpl
.format
= staging
->resource
.b
.b
.format
;
147 cbsurf
= ctx
->create_surface(ctx
,
148 (struct pipe_resource
*)staging
, &surf_tmpl
);
150 si_blitter_begin(ctx
, SI_DECOMPRESS
);
151 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, cbsurf
, 1 << sample
,
152 sctx
->custom_dsa_flush
, depth
);
155 pipe_surface_reference(&zsurf
, NULL
);
156 pipe_surface_reference(&cbsurf
, NULL
);
161 sctx
->dbcb_depth_copy_enabled
= false;
162 sctx
->dbcb_stencil_copy_enabled
= false;
163 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
166 /* Helper function for si_blit_decompress_zs_in_place.
169 si_blit_decompress_zs_planes_in_place(struct si_context
*sctx
,
170 struct r600_texture
*texture
,
171 unsigned planes
, unsigned level_mask
,
172 unsigned first_layer
, unsigned last_layer
)
174 struct pipe_surface
*zsurf
, surf_tmpl
= {{0}};
175 unsigned layer
, max_layer
, checked_last_layer
;
176 unsigned fully_decompressed_mask
= 0;
181 if (planes
& PIPE_MASK_S
)
182 sctx
->db_flush_stencil_inplace
= true;
183 if (planes
& PIPE_MASK_Z
)
184 sctx
->db_flush_depth_inplace
= true;
185 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
187 surf_tmpl
.format
= texture
->resource
.b
.b
.format
;
190 unsigned level
= u_bit_scan(&level_mask
);
192 surf_tmpl
.u
.tex
.level
= level
;
194 /* The smaller the mipmap level, the less layers there are
195 * as far as 3D textures are concerned. */
196 max_layer
= util_max_layer(&texture
->resource
.b
.b
, level
);
197 checked_last_layer
= MIN2(last_layer
, max_layer
);
199 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
200 surf_tmpl
.u
.tex
.first_layer
= layer
;
201 surf_tmpl
.u
.tex
.last_layer
= layer
;
203 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &texture
->resource
.b
.b
, &surf_tmpl
);
205 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
206 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, NULL
, ~0,
207 sctx
->custom_dsa_flush
,
209 si_blitter_end(&sctx
->b
.b
);
211 pipe_surface_reference(&zsurf
, NULL
);
214 /* The texture will always be dirty if some layers aren't flushed.
215 * I don't think this case occurs often though. */
216 if (first_layer
== 0 && last_layer
== max_layer
) {
217 fully_decompressed_mask
|= 1u << level
;
221 if (planes
& PIPE_MASK_Z
)
222 texture
->dirty_level_mask
&= ~fully_decompressed_mask
;
223 if (planes
& PIPE_MASK_S
)
224 texture
->stencil_dirty_level_mask
&= ~fully_decompressed_mask
;
226 sctx
->db_flush_depth_inplace
= false;
227 sctx
->db_flush_stencil_inplace
= false;
228 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
231 /* Decompress Z and/or S planes in place, depending on mask.
234 si_blit_decompress_zs_in_place(struct si_context
*sctx
,
235 struct r600_texture
*texture
,
237 unsigned first_level
, unsigned last_level
,
238 unsigned first_layer
, unsigned last_layer
)
240 unsigned level_mask
=
241 u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
242 unsigned cur_level_mask
;
244 /* First, do combined Z & S decompresses for levels that need it. */
245 if (planes
== (PIPE_MASK_Z
| PIPE_MASK_S
)) {
248 texture
->dirty_level_mask
&
249 texture
->stencil_dirty_level_mask
;
250 si_blit_decompress_zs_planes_in_place(
251 sctx
, texture
, PIPE_MASK_Z
| PIPE_MASK_S
,
253 first_layer
, last_layer
);
254 level_mask
&= ~cur_level_mask
;
257 /* Now do separate Z and S decompresses. */
258 if (planes
& PIPE_MASK_Z
) {
259 cur_level_mask
= level_mask
& texture
->dirty_level_mask
;
260 si_blit_decompress_zs_planes_in_place(
261 sctx
, texture
, PIPE_MASK_Z
,
263 first_layer
, last_layer
);
264 level_mask
&= ~cur_level_mask
;
267 if (planes
& PIPE_MASK_S
) {
268 cur_level_mask
= level_mask
& texture
->stencil_dirty_level_mask
;
269 si_blit_decompress_zs_planes_in_place(
270 sctx
, texture
, PIPE_MASK_S
,
272 first_layer
, last_layer
);
277 si_flush_depth_textures(struct si_context
*sctx
,
278 struct si_textures_info
*textures
)
281 unsigned mask
= textures
->depth_texture_mask
;
284 struct pipe_sampler_view
*view
;
285 struct si_sampler_view
*sview
;
286 struct r600_texture
*tex
;
288 i
= u_bit_scan(&mask
);
290 view
= textures
->views
.views
[i
];
292 sview
= (struct si_sampler_view
*)view
;
294 tex
= (struct r600_texture
*)view
->texture
;
295 assert(tex
->is_depth
&& !tex
->is_flushing_texture
);
297 si_blit_decompress_zs_in_place(sctx
, tex
,
298 sview
->is_stencil_sampler
? PIPE_MASK_S
300 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
301 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
305 static void si_blit_decompress_color(struct pipe_context
*ctx
,
306 struct r600_texture
*rtex
,
307 unsigned first_level
, unsigned last_level
,
308 unsigned first_layer
, unsigned last_layer
,
309 bool need_dcc_decompress
)
311 struct si_context
*sctx
= (struct si_context
*)ctx
;
313 unsigned layer
, checked_last_layer
, max_layer
;
314 unsigned level_mask
=
315 u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
317 if (!need_dcc_decompress
)
318 level_mask
&= rtex
->dirty_level_mask
;
322 if (rtex
->dcc_offset
&& need_dcc_decompress
) {
323 custom_blend
= sctx
->custom_blend_dcc_decompress
;
325 /* disable levels without DCC */
326 for (int i
= first_level
; i
<= last_level
; i
++) {
327 if (!rtex
->dcc_offset
||
328 !rtex
->surface
.level
[i
].dcc_enabled
)
329 level_mask
&= ~(1 << i
);
331 } else if (rtex
->fmask
.size
) {
332 custom_blend
= sctx
->custom_blend_decompress
;
334 custom_blend
= sctx
->custom_blend_fastclear
;
338 unsigned level
= u_bit_scan(&level_mask
);
340 /* The smaller the mipmap level, the less layers there are
341 * as far as 3D textures are concerned. */
342 max_layer
= util_max_layer(&rtex
->resource
.b
.b
, level
);
343 checked_last_layer
= MIN2(last_layer
, max_layer
);
345 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
346 struct pipe_surface
*cbsurf
, surf_tmpl
;
348 surf_tmpl
.format
= rtex
->resource
.b
.b
.format
;
349 surf_tmpl
.u
.tex
.level
= level
;
350 surf_tmpl
.u
.tex
.first_layer
= layer
;
351 surf_tmpl
.u
.tex
.last_layer
= layer
;
352 cbsurf
= ctx
->create_surface(ctx
, &rtex
->resource
.b
.b
, &surf_tmpl
);
354 si_blitter_begin(ctx
, SI_DECOMPRESS
);
355 util_blitter_custom_color(sctx
->blitter
, cbsurf
, custom_blend
);
358 pipe_surface_reference(&cbsurf
, NULL
);
361 /* The texture will always be dirty if some layers aren't flushed.
362 * I don't think this case occurs often though. */
363 if (first_layer
== 0 && last_layer
== max_layer
) {
364 rtex
->dirty_level_mask
&= ~(1 << level
);
370 si_decompress_sampler_color_textures(struct si_context
*sctx
,
371 struct si_textures_info
*textures
)
374 unsigned mask
= textures
->compressed_colortex_mask
;
377 struct pipe_sampler_view
*view
;
378 struct r600_texture
*tex
;
380 i
= u_bit_scan(&mask
);
382 view
= textures
->views
.views
[i
];
385 tex
= (struct r600_texture
*)view
->texture
;
386 assert(tex
->cmask
.size
|| tex
->fmask
.size
|| tex
->dcc_offset
);
388 si_blit_decompress_color(&sctx
->b
.b
, tex
,
389 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
390 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
),
396 si_decompress_image_color_textures(struct si_context
*sctx
,
397 struct si_images_info
*images
)
400 unsigned mask
= images
->compressed_colortex_mask
;
403 const struct pipe_image_view
*view
;
404 struct r600_texture
*tex
;
406 i
= u_bit_scan(&mask
);
408 view
= &images
->views
[i
];
409 assert(view
->resource
->target
!= PIPE_BUFFER
);
411 tex
= (struct r600_texture
*)view
->resource
;
412 if (!tex
->cmask
.size
&& !tex
->fmask
.size
&& !tex
->dcc_offset
)
415 si_blit_decompress_color(&sctx
->b
.b
, tex
,
416 view
->u
.tex
.level
, view
->u
.tex
.level
,
417 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.level
),
422 static void si_check_render_feedback_textures(struct si_context
*sctx
,
423 struct si_textures_info
*textures
)
425 uint32_t mask
= textures
->views
.enabled_mask
;
428 const struct pipe_sampler_view
*view
;
429 struct r600_texture
*tex
;
430 bool render_feedback
= false;
432 unsigned i
= u_bit_scan(&mask
);
434 view
= textures
->views
.views
[i
];
435 if(view
->texture
->target
== PIPE_BUFFER
)
438 tex
= (struct r600_texture
*)view
->texture
;
439 if (!tex
->dcc_offset
)
442 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
443 struct r600_surface
* surf
;
445 if (!sctx
->framebuffer
.state
.cbufs
[j
])
448 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
450 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
451 surf
->base
.u
.tex
.level
>= view
->u
.tex
.first_level
&&
452 surf
->base
.u
.tex
.level
<= view
->u
.tex
.last_level
&&
453 surf
->base
.u
.tex
.first_layer
<= view
->u
.tex
.last_layer
&&
454 surf
->base
.u
.tex
.last_layer
>= view
->u
.tex
.first_layer
)
455 render_feedback
= true;
458 if (render_feedback
) {
459 struct si_screen
*screen
= sctx
->screen
;
460 r600_texture_disable_dcc(&screen
->b
, tex
);
465 static void si_check_render_feedback_images(struct si_context
*sctx
,
466 struct si_images_info
*images
)
468 uint32_t mask
= images
->enabled_mask
;
471 const struct pipe_image_view
*view
;
472 struct r600_texture
*tex
;
473 bool render_feedback
= false;
475 unsigned i
= u_bit_scan(&mask
);
477 view
= &images
->views
[i
];
478 if (view
->resource
->target
== PIPE_BUFFER
)
481 tex
= (struct r600_texture
*)view
->resource
;
482 if (!tex
->dcc_offset
)
485 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
486 struct r600_surface
* surf
;
488 if (!sctx
->framebuffer
.state
.cbufs
[j
])
491 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
493 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
494 surf
->base
.u
.tex
.level
== view
->u
.tex
.level
&&
495 surf
->base
.u
.tex
.first_layer
<= view
->u
.tex
.last_layer
&&
496 surf
->base
.u
.tex
.last_layer
>= view
->u
.tex
.first_layer
)
497 render_feedback
= true;
500 if (render_feedback
) {
501 struct si_screen
*screen
= sctx
->screen
;
502 r600_texture_disable_dcc(&screen
->b
, tex
);
507 static void si_check_render_feedback(struct si_context
*sctx
)
510 if (!sctx
->need_check_render_feedback
)
513 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
514 si_check_render_feedback_images(sctx
, &sctx
->images
[i
]);
515 si_check_render_feedback_textures(sctx
, &sctx
->samplers
[i
]);
517 sctx
->need_check_render_feedback
= false;
520 static void si_decompress_textures(struct si_context
*sctx
, int shader_start
,
523 unsigned compressed_colortex_counter
;
525 if (sctx
->blitter
->running
)
528 /* Update the compressed_colortex_mask if necessary. */
529 compressed_colortex_counter
= p_atomic_read(&sctx
->screen
->b
.compressed_colortex_counter
);
530 if (compressed_colortex_counter
!= sctx
->b
.last_compressed_colortex_counter
) {
531 sctx
->b
.last_compressed_colortex_counter
= compressed_colortex_counter
;
532 si_update_compressed_colortex_masks(sctx
);
535 /* Flush depth textures which need to be flushed. */
536 for (int i
= shader_start
; i
< shader_end
; i
++) {
537 if (sctx
->samplers
[i
].depth_texture_mask
) {
538 si_flush_depth_textures(sctx
, &sctx
->samplers
[i
]);
540 if (sctx
->samplers
[i
].compressed_colortex_mask
) {
541 si_decompress_sampler_color_textures(sctx
, &sctx
->samplers
[i
]);
543 if (sctx
->images
[i
].compressed_colortex_mask
) {
544 si_decompress_image_color_textures(sctx
, &sctx
->images
[i
]);
548 si_check_render_feedback(sctx
);
551 void si_decompress_graphics_textures(struct si_context
*sctx
)
553 si_decompress_textures(sctx
, 0, SI_NUM_GRAPHICS_SHADERS
);
556 void si_decompress_compute_textures(struct si_context
*sctx
)
558 si_decompress_textures(sctx
, SI_NUM_GRAPHICS_SHADERS
, SI_NUM_SHADERS
);
561 static void si_clear(struct pipe_context
*ctx
, unsigned buffers
,
562 const union pipe_color_union
*color
,
563 double depth
, unsigned stencil
)
565 struct si_context
*sctx
= (struct si_context
*)ctx
;
566 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
567 struct pipe_surface
*zsbuf
= fb
->zsbuf
;
568 struct r600_texture
*zstex
=
569 zsbuf
? (struct r600_texture
*)zsbuf
->texture
: NULL
;
571 if (buffers
& PIPE_CLEAR_COLOR
) {
572 evergreen_do_fast_color_clear(&sctx
->b
, fb
,
573 &sctx
->framebuffer
.atom
, &buffers
,
574 &sctx
->framebuffer
.dirty_cbufs
,
577 return; /* all buffers have been fast cleared */
580 if (buffers
& PIPE_CLEAR_COLOR
) {
583 /* These buffers cannot use fast clear, make sure to disable expansion. */
584 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
585 struct r600_texture
*tex
;
587 /* If not clearing this buffer, skip. */
588 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
594 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
595 if (tex
->fmask
.size
== 0)
596 tex
->dirty_level_mask
&= ~(1 << fb
->cbufs
[i
]->u
.tex
.level
);
600 if (zstex
&& zstex
->htile_buffer
&&
601 zsbuf
->u
.tex
.level
== 0 &&
602 zsbuf
->u
.tex
.first_layer
== 0 &&
603 zsbuf
->u
.tex
.last_layer
== util_max_layer(&zstex
->resource
.b
.b
, 0)) {
604 if (buffers
& PIPE_CLEAR_DEPTH
) {
605 /* Need to disable EXPCLEAR temporarily if clearing
607 if (!zstex
->depth_cleared
|| zstex
->depth_clear_value
!= depth
) {
608 sctx
->db_depth_disable_expclear
= true;
611 zstex
->depth_clear_value
= depth
;
612 sctx
->framebuffer
.dirty_zsbuf
= true;
613 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_DEPTH_CLEAR */
614 sctx
->db_depth_clear
= true;
615 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
618 if (buffers
& PIPE_CLEAR_STENCIL
) {
621 /* Need to disable EXPCLEAR temporarily if clearing
623 if (!zstex
->stencil_cleared
|| zstex
->stencil_clear_value
!= stencil
) {
624 sctx
->db_stencil_disable_expclear
= true;
627 zstex
->stencil_clear_value
= stencil
;
628 sctx
->framebuffer
.dirty_zsbuf
= true;
629 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_STENCIL_CLEAR */
630 sctx
->db_stencil_clear
= true;
631 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
635 si_blitter_begin(ctx
, SI_CLEAR
);
636 util_blitter_clear(sctx
->blitter
, fb
->width
, fb
->height
,
637 util_framebuffer_get_num_layers(fb
),
638 buffers
, color
, depth
, stencil
);
641 if (sctx
->db_depth_clear
) {
642 sctx
->db_depth_clear
= false;
643 sctx
->db_depth_disable_expclear
= false;
644 zstex
->depth_cleared
= true;
645 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
648 if (sctx
->db_stencil_clear
) {
649 sctx
->db_stencil_clear
= false;
650 sctx
->db_stencil_disable_expclear
= false;
651 zstex
->stencil_cleared
= true;
652 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
656 static void si_clear_render_target(struct pipe_context
*ctx
,
657 struct pipe_surface
*dst
,
658 const union pipe_color_union
*color
,
659 unsigned dstx
, unsigned dsty
,
660 unsigned width
, unsigned height
)
662 struct si_context
*sctx
= (struct si_context
*)ctx
;
664 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
);
665 util_blitter_clear_render_target(sctx
->blitter
, dst
, color
,
666 dstx
, dsty
, width
, height
);
670 static void si_clear_depth_stencil(struct pipe_context
*ctx
,
671 struct pipe_surface
*dst
,
672 unsigned clear_flags
,
675 unsigned dstx
, unsigned dsty
,
676 unsigned width
, unsigned height
)
678 struct si_context
*sctx
= (struct si_context
*)ctx
;
680 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
);
681 util_blitter_clear_depth_stencil(sctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
682 dstx
, dsty
, width
, height
);
686 /* Helper for decompressing a portion of a color or depth resource before
687 * blitting if any decompression is needed.
688 * The driver doesn't decompress resources automatically while u_blitter is
690 static void si_decompress_subresource(struct pipe_context
*ctx
,
691 struct pipe_resource
*tex
,
692 unsigned planes
, unsigned level
,
693 unsigned first_layer
, unsigned last_layer
)
695 struct si_context
*sctx
= (struct si_context
*)ctx
;
696 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
698 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
699 planes
&= PIPE_MASK_Z
| PIPE_MASK_S
;
701 if (!(rtex
->surface
.flags
& RADEON_SURF_SBUFFER
))
702 planes
&= ~PIPE_MASK_S
;
704 si_blit_decompress_zs_in_place(sctx
, rtex
, planes
,
706 first_layer
, last_layer
);
707 } else if (rtex
->fmask
.size
|| rtex
->cmask
.size
|| rtex
->dcc_offset
) {
708 si_blit_decompress_color(ctx
, rtex
, level
, level
,
709 first_layer
, last_layer
, false);
713 struct texture_orig_info
{
723 void si_resource_copy_region(struct pipe_context
*ctx
,
724 struct pipe_resource
*dst
,
726 unsigned dstx
, unsigned dsty
, unsigned dstz
,
727 struct pipe_resource
*src
,
729 const struct pipe_box
*src_box
)
731 struct si_context
*sctx
= (struct si_context
*)ctx
;
732 struct pipe_surface
*dst_view
, dst_templ
;
733 struct pipe_sampler_view src_templ
, *src_view
;
734 unsigned dst_width
, dst_height
, src_width0
, src_height0
;
735 unsigned src_force_level
= 0;
736 struct pipe_box sbox
, dstbox
;
738 /* Handle buffers first. */
739 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
740 si_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
);
744 assert(u_max_sample(dst
) == u_max_sample(src
));
746 /* The driver doesn't decompress resources automatically while
747 * u_blitter is rendering. */
748 si_decompress_subresource(ctx
, src
, PIPE_MASK_RGBAZS
, src_level
,
749 src_box
->z
, src_box
->z
+ src_box
->depth
- 1);
751 dst_width
= u_minify(dst
->width0
, dst_level
);
752 dst_height
= u_minify(dst
->height0
, dst_level
);
753 src_width0
= src
->width0
;
754 src_height0
= src
->height0
;
756 util_blitter_default_dst_texture(&dst_templ
, dst
, dst_level
, dstz
);
757 util_blitter_default_src_texture(&src_templ
, src
, src_level
);
759 if (util_format_is_compressed(src
->format
) ||
760 util_format_is_compressed(dst
->format
)) {
761 unsigned blocksize
= util_format_get_blocksize(src
->format
);
764 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; /* 64-bit block */
766 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; /* 128-bit block */
767 dst_templ
.format
= src_templ
.format
;
769 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
770 dst_height
= util_format_get_nblocksy(dst
->format
, dst_height
);
771 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
772 src_height0
= util_format_get_nblocksy(src
->format
, src_height0
);
774 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
775 dsty
= util_format_get_nblocksy(dst
->format
, dsty
);
777 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
778 sbox
.y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
780 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
781 sbox
.height
= util_format_get_nblocksy(src
->format
, src_box
->height
);
782 sbox
.depth
= src_box
->depth
;
785 src_force_level
= src_level
;
786 } else if (!util_blitter_is_copy_supported(sctx
->blitter
, dst
, src
) ||
787 /* also *8_SNORM has precision issues, use UNORM instead */
788 util_format_is_snorm8(src
->format
)) {
789 if (util_format_is_subsampled_422(src
->format
)) {
790 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
791 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
793 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
794 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
796 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
799 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
800 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
803 unsigned blocksize
= util_format_get_blocksize(src
->format
);
807 dst_templ
.format
= PIPE_FORMAT_R8_UNORM
;
808 src_templ
.format
= PIPE_FORMAT_R8_UNORM
;
811 dst_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
812 src_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
815 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
816 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
819 dst_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
820 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
823 dst_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
824 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
827 fprintf(stderr
, "Unhandled format %s with blocksize %u\n",
828 util_format_short_name(src
->format
), blocksize
);
834 /* Initialize the surface. */
835 dst_view
= r600_create_surface_custom(ctx
, dst
, &dst_templ
,
836 dst_width
, dst_height
);
838 /* Initialize the sampler view. */
839 src_view
= si_create_sampler_view_custom(ctx
, src
, &src_templ
,
840 src_width0
, src_height0
,
843 u_box_3d(dstx
, dsty
, dstz
, abs(src_box
->width
), abs(src_box
->height
),
844 abs(src_box
->depth
), &dstbox
);
847 si_blitter_begin(ctx
, SI_COPY
);
848 util_blitter_blit_generic(sctx
->blitter
, dst_view
, &dstbox
,
849 src_view
, src_box
, src_width0
, src_height0
,
850 PIPE_MASK_RGBAZS
, PIPE_TEX_FILTER_NEAREST
, NULL
,
854 pipe_surface_reference(&dst_view
, NULL
);
855 pipe_sampler_view_reference(&src_view
, NULL
);
858 static bool do_hardware_msaa_resolve(struct pipe_context
*ctx
,
859 const struct pipe_blit_info
*info
)
861 struct si_context
*sctx
= (struct si_context
*)ctx
;
862 struct r600_texture
*dst
= (struct r600_texture
*)info
->dst
.resource
;
863 unsigned dst_width
= u_minify(info
->dst
.resource
->width0
, info
->dst
.level
);
864 unsigned dst_height
= u_minify(info
->dst
.resource
->height0
, info
->dst
.level
);
865 enum pipe_format format
= info
->src
.format
;
866 unsigned sample_mask
= ~0;
867 struct pipe_resource
*tmp
, templ
;
868 struct pipe_blit_info blit
;
870 /* Check basic requirements for hw resolve. */
871 if (!(info
->src
.resource
->nr_samples
> 1 &&
872 info
->dst
.resource
->nr_samples
<= 1 &&
873 !util_format_is_pure_integer(format
) &&
874 !util_format_is_depth_or_stencil(format
) &&
875 util_max_layer(info
->src
.resource
, 0) == 0))
878 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
879 * the format is R16G16. Use R16A16, which does work.
881 if (format
== PIPE_FORMAT_R16G16_UNORM
)
882 format
= PIPE_FORMAT_R16A16_UNORM
;
883 if (format
== PIPE_FORMAT_R16G16_SNORM
)
884 format
= PIPE_FORMAT_R16A16_SNORM
;
886 /* Check the remaining requirements for hw resolve. */
887 if (util_max_layer(info
->dst
.resource
, info
->dst
.level
) == 0 &&
888 !info
->scissor_enable
&&
889 (info
->mask
& PIPE_MASK_RGBA
) == PIPE_MASK_RGBA
&&
890 util_is_format_compatible(util_format_description(info
->src
.format
),
891 util_format_description(info
->dst
.format
)) &&
892 dst_width
== info
->src
.resource
->width0
&&
893 dst_height
== info
->src
.resource
->height0
&&
894 info
->dst
.box
.x
== 0 &&
895 info
->dst
.box
.y
== 0 &&
896 info
->dst
.box
.width
== dst_width
&&
897 info
->dst
.box
.height
== dst_height
&&
898 info
->dst
.box
.depth
== 1 &&
899 info
->src
.box
.x
== 0 &&
900 info
->src
.box
.y
== 0 &&
901 info
->src
.box
.width
== dst_width
&&
902 info
->src
.box
.height
== dst_height
&&
903 info
->src
.box
.depth
== 1 &&
904 dst
->surface
.level
[info
->dst
.level
].mode
>= RADEON_SURF_MODE_1D
&&
905 (!dst
->cmask
.size
|| !dst
->dirty_level_mask
)) { /* dst cannot be fast-cleared */
906 /* Resolving into a surface with DCC is unsupported. Since
907 * it's being overwritten anyway, clear it to uncompressed.
908 * This is still the fastest codepath even with this clear.
910 if (dst
->dcc_offset
&&
911 dst
->surface
.level
[info
->dst
.level
].dcc_enabled
) {
912 vi_dcc_clear_level(&sctx
->b
, dst
, info
->dst
.level
,
914 dst
->dirty_level_mask
&= ~(1 << info
->dst
.level
);
917 /* Resolve directly from src to dst. */
918 si_blitter_begin(ctx
, SI_COLOR_RESOLVE
|
919 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
920 util_blitter_custom_resolve_color(sctx
->blitter
,
921 info
->dst
.resource
, info
->dst
.level
,
923 info
->src
.resource
, info
->src
.box
.z
,
924 sample_mask
, sctx
->custom_blend_resolve
,
930 /* Shader-based resolve is VERY SLOW. Instead, resolve into
931 * a temporary texture and blit.
933 memset(&templ
, 0, sizeof(templ
));
934 templ
.target
= PIPE_TEXTURE_2D
;
935 templ
.format
= info
->src
.resource
->format
;
936 templ
.width0
= info
->src
.resource
->width0
;
937 templ
.height0
= info
->src
.resource
->height0
;
939 templ
.array_size
= 1;
940 templ
.usage
= PIPE_USAGE_DEFAULT
;
941 templ
.flags
= R600_RESOURCE_FLAG_FORCE_TILING
|
942 R600_RESOURCE_FLAG_DISABLE_DCC
;
944 tmp
= ctx
->screen
->resource_create(ctx
->screen
, &templ
);
949 si_blitter_begin(ctx
, SI_COLOR_RESOLVE
|
950 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
951 util_blitter_custom_resolve_color(sctx
->blitter
, tmp
, 0, 0,
952 info
->src
.resource
, info
->src
.box
.z
,
953 sample_mask
, sctx
->custom_blend_resolve
,
959 blit
.src
.resource
= tmp
;
962 si_blitter_begin(ctx
, SI_BLIT
|
963 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
964 util_blitter_blit(sctx
->blitter
, &blit
);
967 pipe_resource_reference(&tmp
, NULL
);
971 static void si_blit(struct pipe_context
*ctx
,
972 const struct pipe_blit_info
*info
)
974 struct si_context
*sctx
= (struct si_context
*)ctx
;
976 if (do_hardware_msaa_resolve(ctx
, info
)) {
980 assert(util_blitter_is_blit_supported(sctx
->blitter
, info
));
982 /* The driver doesn't decompress resources automatically while
983 * u_blitter is rendering. */
984 si_decompress_subresource(ctx
, info
->src
.resource
, info
->mask
,
987 info
->src
.box
.z
+ info
->src
.box
.depth
- 1);
989 if (sctx
->screen
->b
.debug_flags
& DBG_FORCE_DMA
&&
990 util_try_blit_via_copy_region(ctx
, info
))
993 si_blitter_begin(ctx
, SI_BLIT
|
994 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
995 util_blitter_blit(sctx
->blitter
, info
);
999 static void si_flush_resource(struct pipe_context
*ctx
,
1000 struct pipe_resource
*res
)
1002 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
1004 assert(res
->target
!= PIPE_BUFFER
);
1006 if (!rtex
->is_depth
&& (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
1007 si_blit_decompress_color(ctx
, rtex
, 0, res
->last_level
,
1008 0, util_max_layer(res
, 0), false);
1012 static void si_decompress_dcc(struct pipe_context
*ctx
,
1013 struct r600_texture
*rtex
)
1015 if (!rtex
->dcc_offset
)
1018 si_blit_decompress_color(ctx
, rtex
, 0, rtex
->resource
.b
.b
.last_level
,
1019 0, util_max_layer(&rtex
->resource
.b
.b
, 0),
1023 static void si_pipe_clear_buffer(struct pipe_context
*ctx
,
1024 struct pipe_resource
*dst
,
1025 unsigned offset
, unsigned size
,
1026 const void *clear_value_ptr
,
1027 int clear_value_size
)
1029 struct si_context
*sctx
= (struct si_context
*)ctx
;
1030 uint32_t dword_value
;
1033 assert(offset
% clear_value_size
== 0);
1034 assert(size
% clear_value_size
== 0);
1036 if (clear_value_size
> 4) {
1037 const uint32_t *u32
= clear_value_ptr
;
1038 bool clear_dword_duplicated
= true;
1040 /* See if we can lower large fills to dword fills. */
1041 for (i
= 1; i
< clear_value_size
/ 4; i
++)
1042 if (u32
[0] != u32
[i
]) {
1043 clear_dword_duplicated
= false;
1047 if (!clear_dword_duplicated
) {
1048 /* Use transform feedback for 64-bit, 96-bit, and
1051 union pipe_color_union clear_value
;
1053 memcpy(&clear_value
, clear_value_ptr
, clear_value_size
);
1054 si_blitter_begin(ctx
, SI_DISABLE_RENDER_COND
);
1055 util_blitter_clear_buffer(sctx
->blitter
, dst
, offset
,
1056 size
, clear_value_size
/ 4,
1058 si_blitter_end(ctx
);
1063 /* Expand the clear value to a dword. */
1064 switch (clear_value_size
) {
1066 dword_value
= *(uint8_t*)clear_value_ptr
;
1067 dword_value
|= (dword_value
<< 8) |
1068 (dword_value
<< 16) |
1069 (dword_value
<< 24);
1072 dword_value
= *(uint16_t*)clear_value_ptr
;
1073 dword_value
|= dword_value
<< 16;
1076 dword_value
= *(uint32_t*)clear_value_ptr
;
1079 sctx
->b
.clear_buffer(ctx
, dst
, offset
, size
, dword_value
,
1080 R600_COHERENCY_SHADER
);
1083 void si_init_blit_functions(struct si_context
*sctx
)
1085 sctx
->b
.b
.clear
= si_clear
;
1086 sctx
->b
.b
.clear_buffer
= si_pipe_clear_buffer
;
1087 sctx
->b
.b
.clear_render_target
= si_clear_render_target
;
1088 sctx
->b
.b
.clear_depth_stencil
= si_clear_depth_stencil
;
1089 sctx
->b
.b
.resource_copy_region
= si_resource_copy_region
;
1090 sctx
->b
.b
.blit
= si_blit
;
1091 sctx
->b
.b
.flush_resource
= si_flush_resource
;
1092 sctx
->b
.blit_decompress_depth
= si_blit_decompress_depth
;
1093 sctx
->b
.decompress_dcc
= si_decompress_dcc
;