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radeonsi: add a 'break' in si_check_render_feedback_*()
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "util/u_format.h"
26 #include "util/u_surface.h"
27
28 enum si_blitter_op /* bitmask */
29 {
30 SI_SAVE_TEXTURES = 1,
31 SI_SAVE_FRAMEBUFFER = 2,
32 SI_SAVE_FRAGMENT_STATE = 4,
33 SI_DISABLE_RENDER_COND = 8,
34
35 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
36
37 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
38
39 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
40 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
41
42 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
43 SI_SAVE_FRAGMENT_STATE,
44
45 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
46 SI_DISABLE_RENDER_COND,
47
48 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
49 };
50
51 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
52 {
53 struct si_context *sctx = (struct si_context *)ctx;
54
55 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
56 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
57 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
58 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
59 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
60 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
61 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
62 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
63 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
64
65 if (op & SI_SAVE_FRAGMENT_STATE) {
66 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
67 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
68 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
69 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
70 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
71 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
72 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
73 }
74
75 if (op & SI_SAVE_FRAMEBUFFER)
76 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
77
78 if (op & SI_SAVE_TEXTURES) {
79 util_blitter_save_fragment_sampler_states(
80 sctx->blitter, 2,
81 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
82
83 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
84 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
85 }
86
87 if (op & SI_DISABLE_RENDER_COND)
88 sctx->b.render_cond_force_off = true;
89 }
90
91 static void si_blitter_end(struct pipe_context *ctx)
92 {
93 struct si_context *sctx = (struct si_context *)ctx;
94
95 sctx->b.render_cond_force_off = false;
96 }
97
98 static unsigned u_max_sample(struct pipe_resource *r)
99 {
100 return r->nr_samples ? r->nr_samples - 1 : 0;
101 }
102
103 static unsigned
104 si_blit_dbcb_copy(struct si_context *sctx,
105 struct r600_texture *src,
106 struct r600_texture *dst,
107 unsigned planes, unsigned level_mask,
108 unsigned first_layer, unsigned last_layer,
109 unsigned first_sample, unsigned last_sample)
110 {
111 struct pipe_surface surf_tmpl = {{0}};
112 unsigned layer, sample, checked_last_layer, max_layer;
113 unsigned fully_copied_levels = 0;
114
115 if (planes & PIPE_MASK_Z)
116 sctx->dbcb_depth_copy_enabled = true;
117 if (planes & PIPE_MASK_S)
118 sctx->dbcb_stencil_copy_enabled = true;
119 si_mark_atom_dirty(sctx, &sctx->db_render_state);
120
121 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
122
123 while (level_mask) {
124 unsigned level = u_bit_scan(&level_mask);
125
126 /* The smaller the mipmap level, the less layers there are
127 * as far as 3D textures are concerned. */
128 max_layer = util_max_layer(&src->resource.b.b, level);
129 checked_last_layer = MIN2(last_layer, max_layer);
130
131 surf_tmpl.u.tex.level = level;
132
133 for (layer = first_layer; layer <= checked_last_layer; layer++) {
134 struct pipe_surface *zsurf, *cbsurf;
135
136 surf_tmpl.format = src->resource.b.b.format;
137 surf_tmpl.u.tex.first_layer = layer;
138 surf_tmpl.u.tex.last_layer = layer;
139
140 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
141
142 surf_tmpl.format = dst->resource.b.b.format;
143 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
144
145 for (sample = first_sample; sample <= last_sample; sample++) {
146 if (sample != sctx->dbcb_copy_sample) {
147 sctx->dbcb_copy_sample = sample;
148 si_mark_atom_dirty(sctx, &sctx->db_render_state);
149 }
150
151 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
152 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
153 sctx->custom_dsa_flush, 1.0f);
154 si_blitter_end(&sctx->b.b);
155 }
156
157 pipe_surface_reference(&zsurf, NULL);
158 pipe_surface_reference(&cbsurf, NULL);
159 }
160
161 if (first_layer == 0 && last_layer >= max_layer &&
162 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
163 fully_copied_levels |= 1u << level;
164 }
165
166 sctx->dbcb_depth_copy_enabled = false;
167 sctx->dbcb_stencil_copy_enabled = false;
168 si_mark_atom_dirty(sctx, &sctx->db_render_state);
169
170 return fully_copied_levels;
171 }
172
173 static void si_blit_decompress_depth(struct pipe_context *ctx,
174 struct r600_texture *texture,
175 struct r600_texture *staging,
176 unsigned first_level, unsigned last_level,
177 unsigned first_layer, unsigned last_layer,
178 unsigned first_sample, unsigned last_sample)
179 {
180 const struct util_format_description *desc;
181 unsigned planes = 0;
182
183 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
184
185 desc = util_format_description(staging->resource.b.b.format);
186
187 if (util_format_has_depth(desc))
188 planes |= PIPE_MASK_Z;
189 if (util_format_has_stencil(desc))
190 planes |= PIPE_MASK_S;
191
192 si_blit_dbcb_copy(
193 (struct si_context *)ctx, texture, staging, planes,
194 u_bit_consecutive(first_level, last_level - first_level + 1),
195 first_layer, last_layer, first_sample, last_sample);
196 }
197
198 /* Helper function for si_blit_decompress_zs_in_place.
199 */
200 static void
201 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
202 struct r600_texture *texture,
203 unsigned planes, unsigned level_mask,
204 unsigned first_layer, unsigned last_layer)
205 {
206 struct pipe_surface *zsurf, surf_tmpl = {{0}};
207 unsigned layer, max_layer, checked_last_layer;
208 unsigned fully_decompressed_mask = 0;
209
210 if (!level_mask)
211 return;
212
213 if (planes & PIPE_MASK_S)
214 sctx->db_flush_stencil_inplace = true;
215 if (planes & PIPE_MASK_Z)
216 sctx->db_flush_depth_inplace = true;
217 si_mark_atom_dirty(sctx, &sctx->db_render_state);
218
219 surf_tmpl.format = texture->resource.b.b.format;
220
221 while (level_mask) {
222 unsigned level = u_bit_scan(&level_mask);
223
224 surf_tmpl.u.tex.level = level;
225
226 /* The smaller the mipmap level, the less layers there are
227 * as far as 3D textures are concerned. */
228 max_layer = util_max_layer(&texture->resource.b.b, level);
229 checked_last_layer = MIN2(last_layer, max_layer);
230
231 for (layer = first_layer; layer <= checked_last_layer; layer++) {
232 surf_tmpl.u.tex.first_layer = layer;
233 surf_tmpl.u.tex.last_layer = layer;
234
235 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
236
237 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
238 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
239 sctx->custom_dsa_flush,
240 1.0f);
241 si_blitter_end(&sctx->b.b);
242
243 pipe_surface_reference(&zsurf, NULL);
244 }
245
246 /* The texture will always be dirty if some layers aren't flushed.
247 * I don't think this case occurs often though. */
248 if (first_layer == 0 && last_layer >= max_layer) {
249 fully_decompressed_mask |= 1u << level;
250 }
251 }
252
253 if (planes & PIPE_MASK_Z)
254 texture->dirty_level_mask &= ~fully_decompressed_mask;
255 if (planes & PIPE_MASK_S)
256 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
257
258 sctx->db_flush_depth_inplace = false;
259 sctx->db_flush_stencil_inplace = false;
260 si_mark_atom_dirty(sctx, &sctx->db_render_state);
261 }
262
263 /* Helper function of si_flush_depth_texture: decompress the given levels
264 * of Z and/or S planes in place.
265 */
266 static void
267 si_blit_decompress_zs_in_place(struct si_context *sctx,
268 struct r600_texture *texture,
269 unsigned levels_z, unsigned levels_s,
270 unsigned first_layer, unsigned last_layer)
271 {
272 unsigned both = levels_z & levels_s;
273
274 /* First, do combined Z & S decompresses for levels that need it. */
275 if (both) {
276 si_blit_decompress_zs_planes_in_place(
277 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
278 both,
279 first_layer, last_layer);
280 levels_z &= ~both;
281 levels_s &= ~both;
282 }
283
284 /* Now do separate Z and S decompresses. */
285 if (levels_z) {
286 si_blit_decompress_zs_planes_in_place(
287 sctx, texture, PIPE_MASK_Z,
288 levels_z,
289 first_layer, last_layer);
290 }
291
292 if (levels_s) {
293 si_blit_decompress_zs_planes_in_place(
294 sctx, texture, PIPE_MASK_S,
295 levels_s,
296 first_layer, last_layer);
297 }
298 }
299
300 static void
301 si_flush_depth_texture(struct si_context *sctx,
302 struct r600_texture *tex,
303 unsigned required_planes,
304 unsigned first_level, unsigned last_level,
305 unsigned first_layer, unsigned last_layer)
306 {
307 unsigned inplace_planes = 0;
308 unsigned copy_planes = 0;
309 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
310 unsigned levels_z = 0;
311 unsigned levels_s = 0;
312
313 if (required_planes & PIPE_MASK_Z) {
314 levels_z = level_mask & tex->dirty_level_mask;
315
316 if (levels_z) {
317 if (r600_can_sample_zs(tex, false))
318 inplace_planes |= PIPE_MASK_Z;
319 else
320 copy_planes |= PIPE_MASK_Z;
321 }
322 }
323 if (required_planes & PIPE_MASK_S) {
324 levels_s = level_mask & tex->stencil_dirty_level_mask;
325
326 if (levels_s) {
327 if (r600_can_sample_zs(tex, true))
328 inplace_planes |= PIPE_MASK_S;
329 else
330 copy_planes |= PIPE_MASK_S;
331 }
332 }
333
334 assert(!tex->tc_compatible_htile || levels_z == 0);
335
336 /* We may have to allocate the flushed texture here when called from
337 * si_decompress_subresource.
338 */
339 if (copy_planes &&
340 (tex->flushed_depth_texture ||
341 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
342 struct r600_texture *dst = tex->flushed_depth_texture;
343 unsigned fully_copied_levels;
344 unsigned levels = 0;
345
346 assert(tex->flushed_depth_texture);
347
348 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
349 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
350
351 if (copy_planes & PIPE_MASK_Z) {
352 levels |= levels_z;
353 levels_z = 0;
354 }
355 if (copy_planes & PIPE_MASK_S) {
356 levels |= levels_s;
357 levels_s = 0;
358 }
359
360 fully_copied_levels = si_blit_dbcb_copy(
361 sctx, tex, dst, copy_planes, levels,
362 first_layer, last_layer,
363 0, u_max_sample(&tex->resource.b.b));
364
365 if (copy_planes & PIPE_MASK_Z)
366 tex->dirty_level_mask &= ~fully_copied_levels;
367 if (copy_planes & PIPE_MASK_S)
368 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
369 }
370
371 if (inplace_planes) {
372 si_blit_decompress_zs_in_place(
373 sctx, tex,
374 levels_z, levels_s,
375 first_layer, last_layer);
376 }
377 }
378
379 static void
380 si_flush_depth_textures(struct si_context *sctx,
381 struct si_textures_info *textures)
382 {
383 unsigned i;
384 unsigned mask = textures->depth_texture_mask;
385
386 while (mask) {
387 struct pipe_sampler_view *view;
388 struct si_sampler_view *sview;
389 struct r600_texture *tex;
390
391 i = u_bit_scan(&mask);
392
393 view = textures->views.views[i];
394 assert(view);
395 sview = (struct si_sampler_view*)view;
396
397 tex = (struct r600_texture *)view->texture;
398 assert(tex->db_compatible);
399
400 si_flush_depth_texture(
401 sctx, tex,
402 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
403 view->u.tex.first_level, view->u.tex.last_level,
404 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
405 }
406 }
407
408 static void si_blit_decompress_color(struct pipe_context *ctx,
409 struct r600_texture *rtex,
410 unsigned first_level, unsigned last_level,
411 unsigned first_layer, unsigned last_layer,
412 bool need_dcc_decompress)
413 {
414 struct si_context *sctx = (struct si_context *)ctx;
415 void* custom_blend;
416 unsigned layer, checked_last_layer, max_layer;
417 unsigned level_mask =
418 u_bit_consecutive(first_level, last_level - first_level + 1);
419
420 if (!need_dcc_decompress)
421 level_mask &= rtex->dirty_level_mask;
422 if (!level_mask)
423 return;
424
425 if (rtex->dcc_offset && need_dcc_decompress) {
426 custom_blend = sctx->custom_blend_dcc_decompress;
427
428 /* disable levels without DCC */
429 for (int i = first_level; i <= last_level; i++) {
430 if (!vi_dcc_enabled(rtex, i))
431 level_mask &= ~(1 << i);
432 }
433 } else if (rtex->fmask.size) {
434 custom_blend = sctx->custom_blend_decompress;
435 } else {
436 custom_blend = sctx->custom_blend_fastclear;
437 }
438
439 while (level_mask) {
440 unsigned level = u_bit_scan(&level_mask);
441
442 /* The smaller the mipmap level, the less layers there are
443 * as far as 3D textures are concerned. */
444 max_layer = util_max_layer(&rtex->resource.b.b, level);
445 checked_last_layer = MIN2(last_layer, max_layer);
446
447 for (layer = first_layer; layer <= checked_last_layer; layer++) {
448 struct pipe_surface *cbsurf, surf_tmpl;
449
450 surf_tmpl.format = rtex->resource.b.b.format;
451 surf_tmpl.u.tex.level = level;
452 surf_tmpl.u.tex.first_layer = layer;
453 surf_tmpl.u.tex.last_layer = layer;
454 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
455
456 si_blitter_begin(ctx, SI_DECOMPRESS);
457 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
458 si_blitter_end(ctx);
459
460 pipe_surface_reference(&cbsurf, NULL);
461 }
462
463 /* The texture will always be dirty if some layers aren't flushed.
464 * I don't think this case occurs often though. */
465 if (first_layer == 0 && last_layer >= max_layer) {
466 rtex->dirty_level_mask &= ~(1 << level);
467 }
468 }
469 }
470
471 static void
472 si_decompress_sampler_color_textures(struct si_context *sctx,
473 struct si_textures_info *textures)
474 {
475 unsigned i;
476 unsigned mask = textures->compressed_colortex_mask;
477
478 while (mask) {
479 struct pipe_sampler_view *view;
480 struct r600_texture *tex;
481
482 i = u_bit_scan(&mask);
483
484 view = textures->views.views[i];
485 assert(view);
486
487 tex = (struct r600_texture *)view->texture;
488 /* CMASK or DCC can be discarded and we can still end up here. */
489 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
490 continue;
491
492 si_blit_decompress_color(&sctx->b.b, tex,
493 view->u.tex.first_level, view->u.tex.last_level,
494 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
495 false);
496 }
497 }
498
499 static void
500 si_decompress_image_color_textures(struct si_context *sctx,
501 struct si_images_info *images)
502 {
503 unsigned i;
504 unsigned mask = images->compressed_colortex_mask;
505
506 while (mask) {
507 const struct pipe_image_view *view;
508 struct r600_texture *tex;
509
510 i = u_bit_scan(&mask);
511
512 view = &images->views[i];
513 assert(view->resource->target != PIPE_BUFFER);
514
515 tex = (struct r600_texture *)view->resource;
516 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
517 continue;
518
519 si_blit_decompress_color(&sctx->b.b, tex,
520 view->u.tex.level, view->u.tex.level,
521 0, util_max_layer(&tex->resource.b.b, view->u.tex.level),
522 false);
523 }
524 }
525
526 static void si_check_render_feedback_textures(struct si_context *sctx,
527 struct si_textures_info *textures)
528 {
529 uint32_t mask = textures->views.enabled_mask;
530
531 while (mask) {
532 const struct pipe_sampler_view *view;
533 struct r600_texture *tex;
534 bool render_feedback = false;
535
536 unsigned i = u_bit_scan(&mask);
537
538 view = textures->views.views[i];
539 if(view->texture->target == PIPE_BUFFER)
540 continue;
541
542 tex = (struct r600_texture *)view->texture;
543 if (!tex->dcc_offset)
544 continue;
545
546 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
547 struct r600_surface * surf;
548
549 if (!sctx->framebuffer.state.cbufs[j])
550 continue;
551
552 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
553
554 if (tex == (struct r600_texture*)surf->base.texture &&
555 surf->base.u.tex.level >= view->u.tex.first_level &&
556 surf->base.u.tex.level <= view->u.tex.last_level &&
557 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
558 surf->base.u.tex.last_layer >= view->u.tex.first_layer) {
559 render_feedback = true;
560 break;
561 }
562 }
563
564 if (render_feedback)
565 r600_texture_disable_dcc(&sctx->b, tex);
566 }
567 }
568
569 static void si_check_render_feedback_images(struct si_context *sctx,
570 struct si_images_info *images)
571 {
572 uint32_t mask = images->enabled_mask;
573
574 while (mask) {
575 const struct pipe_image_view *view;
576 struct r600_texture *tex;
577 bool render_feedback = false;
578
579 unsigned i = u_bit_scan(&mask);
580
581 view = &images->views[i];
582 if (view->resource->target == PIPE_BUFFER)
583 continue;
584
585 tex = (struct r600_texture *)view->resource;
586 if (!tex->dcc_offset)
587 continue;
588
589 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
590 struct r600_surface * surf;
591
592 if (!sctx->framebuffer.state.cbufs[j])
593 continue;
594
595 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
596
597 if (tex == (struct r600_texture*)surf->base.texture &&
598 surf->base.u.tex.level == view->u.tex.level &&
599 surf->base.u.tex.first_layer <= view->u.tex.last_layer &&
600 surf->base.u.tex.last_layer >= view->u.tex.first_layer) {
601 render_feedback = true;
602 break;
603 }
604 }
605
606 if (render_feedback)
607 r600_texture_disable_dcc(&sctx->b, tex);
608 }
609 }
610
611 static void si_check_render_feedback(struct si_context *sctx)
612 {
613
614 if (!sctx->need_check_render_feedback)
615 return;
616
617 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
618 si_check_render_feedback_images(sctx, &sctx->images[i]);
619 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
620 }
621 sctx->need_check_render_feedback = false;
622 }
623
624 static void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
625 {
626 unsigned compressed_colortex_counter, mask;
627
628 if (sctx->blitter->running)
629 return;
630
631 /* Update the compressed_colortex_mask if necessary. */
632 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
633 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
634 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
635 si_update_compressed_colortex_masks(sctx);
636 }
637
638 /* Decompress color & depth textures if needed. */
639 mask = sctx->compressed_tex_shader_mask & shader_mask;
640 while (mask) {
641 unsigned i = u_bit_scan(&mask);
642
643 if (sctx->samplers[i].depth_texture_mask) {
644 si_flush_depth_textures(sctx, &sctx->samplers[i]);
645 }
646 if (sctx->samplers[i].compressed_colortex_mask) {
647 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
648 }
649 if (sctx->images[i].compressed_colortex_mask) {
650 si_decompress_image_color_textures(sctx, &sctx->images[i]);
651 }
652 }
653
654 si_check_render_feedback(sctx);
655 }
656
657 void si_decompress_graphics_textures(struct si_context *sctx)
658 {
659 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
660 }
661
662 void si_decompress_compute_textures(struct si_context *sctx)
663 {
664 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
665 }
666
667 static void si_clear(struct pipe_context *ctx, unsigned buffers,
668 const union pipe_color_union *color,
669 double depth, unsigned stencil)
670 {
671 struct si_context *sctx = (struct si_context *)ctx;
672 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
673 struct pipe_surface *zsbuf = fb->zsbuf;
674 struct r600_texture *zstex =
675 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
676
677 if (buffers & PIPE_CLEAR_COLOR) {
678 evergreen_do_fast_color_clear(&sctx->b, fb,
679 &sctx->framebuffer.atom, &buffers,
680 &sctx->framebuffer.dirty_cbufs,
681 color);
682 if (!buffers)
683 return; /* all buffers have been fast cleared */
684 }
685
686 if (buffers & PIPE_CLEAR_COLOR) {
687 int i;
688
689 /* These buffers cannot use fast clear, make sure to disable expansion. */
690 for (i = 0; i < fb->nr_cbufs; i++) {
691 struct r600_texture *tex;
692
693 /* If not clearing this buffer, skip. */
694 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
695 continue;
696
697 if (!fb->cbufs[i])
698 continue;
699
700 tex = (struct r600_texture *)fb->cbufs[i]->texture;
701 if (tex->fmask.size == 0)
702 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
703 }
704 }
705
706 if (zstex && zstex->htile_buffer &&
707 zsbuf->u.tex.level == 0 &&
708 zsbuf->u.tex.first_layer == 0 &&
709 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
710 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
711 if (buffers & PIPE_CLEAR_DEPTH &&
712 (!zstex->tc_compatible_htile ||
713 depth == 0 || depth == 1)) {
714 /* Need to disable EXPCLEAR temporarily if clearing
715 * to a new value. */
716 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
717 sctx->db_depth_disable_expclear = true;
718 }
719
720 zstex->depth_clear_value = depth;
721 sctx->framebuffer.dirty_zsbuf = true;
722 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
723 sctx->db_depth_clear = true;
724 si_mark_atom_dirty(sctx, &sctx->db_render_state);
725 }
726
727 /* TC-compatible HTILE only supports stencil clears to 0. */
728 if (buffers & PIPE_CLEAR_STENCIL &&
729 (!zstex->tc_compatible_htile || stencil == 0)) {
730 stencil &= 0xff;
731
732 /* Need to disable EXPCLEAR temporarily if clearing
733 * to a new value. */
734 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
735 sctx->db_stencil_disable_expclear = true;
736 }
737
738 zstex->stencil_clear_value = stencil;
739 sctx->framebuffer.dirty_zsbuf = true;
740 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
741 sctx->db_stencil_clear = true;
742 si_mark_atom_dirty(sctx, &sctx->db_render_state);
743 }
744 }
745
746 si_blitter_begin(ctx, SI_CLEAR);
747 util_blitter_clear(sctx->blitter, fb->width, fb->height,
748 util_framebuffer_get_num_layers(fb),
749 buffers, color, depth, stencil);
750 si_blitter_end(ctx);
751
752 if (sctx->db_depth_clear) {
753 sctx->db_depth_clear = false;
754 sctx->db_depth_disable_expclear = false;
755 zstex->depth_cleared = true;
756 si_mark_atom_dirty(sctx, &sctx->db_render_state);
757 }
758
759 if (sctx->db_stencil_clear) {
760 sctx->db_stencil_clear = false;
761 sctx->db_stencil_disable_expclear = false;
762 zstex->stencil_cleared = true;
763 si_mark_atom_dirty(sctx, &sctx->db_render_state);
764 }
765 }
766
767 static void si_clear_render_target(struct pipe_context *ctx,
768 struct pipe_surface *dst,
769 const union pipe_color_union *color,
770 unsigned dstx, unsigned dsty,
771 unsigned width, unsigned height,
772 bool render_condition_enabled)
773 {
774 struct si_context *sctx = (struct si_context *)ctx;
775
776 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
777 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
778 util_blitter_clear_render_target(sctx->blitter, dst, color,
779 dstx, dsty, width, height);
780 si_blitter_end(ctx);
781 }
782
783 static void si_clear_depth_stencil(struct pipe_context *ctx,
784 struct pipe_surface *dst,
785 unsigned clear_flags,
786 double depth,
787 unsigned stencil,
788 unsigned dstx, unsigned dsty,
789 unsigned width, unsigned height,
790 bool render_condition_enabled)
791 {
792 struct si_context *sctx = (struct si_context *)ctx;
793
794 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
795 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
796 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
797 dstx, dsty, width, height);
798 si_blitter_end(ctx);
799 }
800
801 /* Helper for decompressing a portion of a color or depth resource before
802 * blitting if any decompression is needed.
803 * The driver doesn't decompress resources automatically while u_blitter is
804 * rendering. */
805 static void si_decompress_subresource(struct pipe_context *ctx,
806 struct pipe_resource *tex,
807 unsigned planes, unsigned level,
808 unsigned first_layer, unsigned last_layer)
809 {
810 struct si_context *sctx = (struct si_context *)ctx;
811 struct r600_texture *rtex = (struct r600_texture*)tex;
812
813 if (rtex->db_compatible) {
814 planes &= PIPE_MASK_Z | PIPE_MASK_S;
815
816 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
817 planes &= ~PIPE_MASK_S;
818
819 si_flush_depth_texture(sctx, rtex, planes,
820 level, level,
821 first_layer, last_layer);
822 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
823 si_blit_decompress_color(ctx, rtex, level, level,
824 first_layer, last_layer, false);
825 }
826 }
827
828 struct texture_orig_info {
829 unsigned format;
830 unsigned width0;
831 unsigned height0;
832 unsigned npix_x;
833 unsigned npix_y;
834 unsigned npix0_x;
835 unsigned npix0_y;
836 };
837
838 void si_resource_copy_region(struct pipe_context *ctx,
839 struct pipe_resource *dst,
840 unsigned dst_level,
841 unsigned dstx, unsigned dsty, unsigned dstz,
842 struct pipe_resource *src,
843 unsigned src_level,
844 const struct pipe_box *src_box)
845 {
846 struct si_context *sctx = (struct si_context *)ctx;
847 struct r600_texture *rsrc = (struct r600_texture*)src;
848 struct pipe_surface *dst_view, dst_templ;
849 struct pipe_sampler_view src_templ, *src_view;
850 unsigned dst_width, dst_height, src_width0, src_height0;
851 unsigned dst_width0, dst_height0, src_force_level = 0;
852 struct pipe_box sbox, dstbox;
853
854 /* Handle buffers first. */
855 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
856 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
857 return;
858 }
859
860 assert(u_max_sample(dst) == u_max_sample(src));
861
862 /* The driver doesn't decompress resources automatically while
863 * u_blitter is rendering. */
864 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
865 src_box->z, src_box->z + src_box->depth - 1);
866
867 dst_width = u_minify(dst->width0, dst_level);
868 dst_height = u_minify(dst->height0, dst_level);
869 dst_width0 = dst->width0;
870 dst_height0 = dst->height0;
871 src_width0 = src->width0;
872 src_height0 = src->height0;
873
874 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
875 util_blitter_default_src_texture(&src_templ, src, src_level);
876
877 if (util_format_is_compressed(src->format) ||
878 util_format_is_compressed(dst->format)) {
879 unsigned blocksize = rsrc->surface.bpe;
880
881 if (blocksize == 8)
882 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
883 else
884 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
885 dst_templ.format = src_templ.format;
886
887 dst_width = util_format_get_nblocksx(dst->format, dst_width);
888 dst_height = util_format_get_nblocksy(dst->format, dst_height);
889 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
890 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
891 src_width0 = util_format_get_nblocksx(src->format, src_width0);
892 src_height0 = util_format_get_nblocksy(src->format, src_height0);
893
894 dstx = util_format_get_nblocksx(dst->format, dstx);
895 dsty = util_format_get_nblocksy(dst->format, dsty);
896
897 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
898 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
899 sbox.z = src_box->z;
900 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
901 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
902 sbox.depth = src_box->depth;
903 src_box = &sbox;
904
905 src_force_level = src_level;
906 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
907 if (util_format_is_subsampled_422(src->format)) {
908 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
909 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
910
911 dst_width = util_format_get_nblocksx(dst->format, dst_width);
912 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
913 src_width0 = util_format_get_nblocksx(src->format, src_width0);
914
915 dstx = util_format_get_nblocksx(dst->format, dstx);
916
917 sbox = *src_box;
918 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
919 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
920 src_box = &sbox;
921 } else {
922 unsigned blocksize = rsrc->surface.bpe;
923
924 switch (blocksize) {
925 case 1:
926 dst_templ.format = PIPE_FORMAT_R8_UNORM;
927 src_templ.format = PIPE_FORMAT_R8_UNORM;
928 break;
929 case 2:
930 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
931 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
932 break;
933 case 4:
934 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
935 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
936 break;
937 case 8:
938 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
939 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
940 break;
941 case 16:
942 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
943 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
944 break;
945 default:
946 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
947 util_format_short_name(src->format), blocksize);
948 assert(0);
949 }
950 }
951 }
952
953 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
954 dst_templ.format);
955 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
956 src_templ.format);
957
958 /* Initialize the surface. */
959 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
960 dst_width0, dst_height0,
961 dst_width, dst_height);
962
963 /* Initialize the sampler view. */
964 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
965 src_width0, src_height0,
966 src_force_level);
967
968 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
969 abs(src_box->depth), &dstbox);
970
971 /* Copy. */
972 si_blitter_begin(ctx, SI_COPY);
973 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
974 src_view, src_box, src_width0, src_height0,
975 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
976 false);
977 si_blitter_end(ctx);
978
979 pipe_surface_reference(&dst_view, NULL);
980 pipe_sampler_view_reference(&src_view, NULL);
981 }
982
983 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
984 const struct pipe_blit_info *info)
985 {
986 struct si_context *sctx = (struct si_context*)ctx;
987 struct r600_texture *src = (struct r600_texture*)info->src.resource;
988 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
989 MAYBE_UNUSED struct r600_texture *rtmp;
990 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
991 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
992 enum pipe_format format = info->src.format;
993 unsigned sample_mask = ~0;
994 struct pipe_resource *tmp, templ;
995 struct pipe_blit_info blit;
996
997 /* Check basic requirements for hw resolve. */
998 if (!(info->src.resource->nr_samples > 1 &&
999 info->dst.resource->nr_samples <= 1 &&
1000 !util_format_is_pure_integer(format) &&
1001 !util_format_is_depth_or_stencil(format) &&
1002 util_max_layer(info->src.resource, 0) == 0))
1003 return false;
1004
1005 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1006 * the format is R16G16. Use R16A16, which does work.
1007 */
1008 if (format == PIPE_FORMAT_R16G16_UNORM)
1009 format = PIPE_FORMAT_R16A16_UNORM;
1010 if (format == PIPE_FORMAT_R16G16_SNORM)
1011 format = PIPE_FORMAT_R16A16_SNORM;
1012
1013 /* Check the remaining requirements for hw resolve. */
1014 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1015 !info->scissor_enable &&
1016 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1017 util_is_format_compatible(util_format_description(info->src.format),
1018 util_format_description(info->dst.format)) &&
1019 dst_width == info->src.resource->width0 &&
1020 dst_height == info->src.resource->height0 &&
1021 info->dst.box.x == 0 &&
1022 info->dst.box.y == 0 &&
1023 info->dst.box.width == dst_width &&
1024 info->dst.box.height == dst_height &&
1025 info->dst.box.depth == 1 &&
1026 info->src.box.x == 0 &&
1027 info->src.box.y == 0 &&
1028 info->src.box.width == dst_width &&
1029 info->src.box.height == dst_height &&
1030 info->src.box.depth == 1 &&
1031 !dst->surface.is_linear &&
1032 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1033 /* Check the last constraint. */
1034 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1035 /* The next fast clear will switch to this mode to
1036 * get direct hw resolve next time if the mode is
1037 * different now.
1038 */
1039 src->last_msaa_resolve_target_micro_mode =
1040 dst->surface.micro_tile_mode;
1041 goto resolve_to_temp;
1042 }
1043
1044 /* Resolving into a surface with DCC is unsupported. Since
1045 * it's being overwritten anyway, clear it to uncompressed.
1046 * This is still the fastest codepath even with this clear.
1047 */
1048 if (vi_dcc_enabled(dst, info->dst.level)) {
1049 /* TODO: Implement per-level DCC clears for GFX9. */
1050 if (sctx->b.chip_class >= GFX9 &&
1051 info->dst.resource->last_level != 0)
1052 goto resolve_to_temp;
1053
1054 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1055 0xFFFFFFFF);
1056 dst->dirty_level_mask &= ~(1 << info->dst.level);
1057 }
1058
1059 /* Resolve directly from src to dst. */
1060 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1061 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1062 util_blitter_custom_resolve_color(sctx->blitter,
1063 info->dst.resource, info->dst.level,
1064 info->dst.box.z,
1065 info->src.resource, info->src.box.z,
1066 sample_mask, sctx->custom_blend_resolve,
1067 format);
1068 si_blitter_end(ctx);
1069 return true;
1070 }
1071
1072 resolve_to_temp:
1073 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1074 * a temporary texture and blit.
1075 */
1076 memset(&templ, 0, sizeof(templ));
1077 templ.target = PIPE_TEXTURE_2D;
1078 templ.format = info->src.resource->format;
1079 templ.width0 = info->src.resource->width0;
1080 templ.height0 = info->src.resource->height0;
1081 templ.depth0 = 1;
1082 templ.array_size = 1;
1083 templ.usage = PIPE_USAGE_DEFAULT;
1084 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1085 R600_RESOURCE_FLAG_DISABLE_DCC;
1086
1087 /* The src and dst microtile modes must be the same. */
1088 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1089 templ.bind = PIPE_BIND_SCANOUT;
1090 else
1091 templ.bind = 0;
1092
1093 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1094 if (!tmp)
1095 return false;
1096 rtmp = (struct r600_texture*)tmp;
1097
1098 assert(!rtmp->surface.is_linear);
1099 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1100
1101 /* resolve */
1102 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1103 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1104 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
1105 info->src.resource, info->src.box.z,
1106 sample_mask, sctx->custom_blend_resolve,
1107 format);
1108 si_blitter_end(ctx);
1109
1110 /* blit */
1111 blit = *info;
1112 blit.src.resource = tmp;
1113 blit.src.box.z = 0;
1114
1115 si_blitter_begin(ctx, SI_BLIT |
1116 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1117 util_blitter_blit(sctx->blitter, &blit);
1118 si_blitter_end(ctx);
1119
1120 pipe_resource_reference(&tmp, NULL);
1121 return true;
1122 }
1123
1124 static void si_blit(struct pipe_context *ctx,
1125 const struct pipe_blit_info *info)
1126 {
1127 struct si_context *sctx = (struct si_context*)ctx;
1128 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1129
1130 if (do_hardware_msaa_resolve(ctx, info)) {
1131 return;
1132 }
1133
1134 /* Using SDMA for copying to a linear texture in GTT is much faster.
1135 * This improves DRI PRIME performance.
1136 *
1137 * resource_copy_region can't do this yet, because dma_copy calls it
1138 * on failure (recursion).
1139 */
1140 if (rdst->surface.is_linear &&
1141 sctx->b.dma_copy &&
1142 util_can_blit_via_copy_region(info, false)) {
1143 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1144 info->dst.box.x, info->dst.box.y,
1145 info->dst.box.z,
1146 info->src.resource, info->src.level,
1147 &info->src.box);
1148 return;
1149 }
1150
1151 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1152
1153 /* The driver doesn't decompress resources automatically while
1154 * u_blitter is rendering. */
1155 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1156 info->src.level,
1157 info->src.format);
1158 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1159 info->dst.level,
1160 info->dst.format);
1161 si_decompress_subresource(ctx, info->src.resource, info->mask,
1162 info->src.level,
1163 info->src.box.z,
1164 info->src.box.z + info->src.box.depth - 1);
1165
1166 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1167 util_try_blit_via_copy_region(ctx, info))
1168 return;
1169
1170 si_blitter_begin(ctx, SI_BLIT |
1171 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1172 util_blitter_blit(sctx->blitter, info);
1173 si_blitter_end(ctx);
1174 }
1175
1176 static boolean si_generate_mipmap(struct pipe_context *ctx,
1177 struct pipe_resource *tex,
1178 enum pipe_format format,
1179 unsigned base_level, unsigned last_level,
1180 unsigned first_layer, unsigned last_layer)
1181 {
1182 struct si_context *sctx = (struct si_context*)ctx;
1183 struct r600_texture *rtex = (struct r600_texture *)tex;
1184
1185 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1186 return false;
1187
1188 /* The driver doesn't decompress resources automatically while
1189 * u_blitter is rendering. */
1190 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1191 format);
1192 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1193 base_level, first_layer, last_layer);
1194
1195 /* Clear dirty_level_mask for the levels that will be overwritten. */
1196 assert(base_level < last_level);
1197 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1198 last_level - base_level);
1199
1200 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1201 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1202 base_level, last_level,
1203 first_layer, last_layer);
1204 si_blitter_end(ctx);
1205 return true;
1206 }
1207
1208 static void si_flush_resource(struct pipe_context *ctx,
1209 struct pipe_resource *res)
1210 {
1211 struct r600_texture *rtex = (struct r600_texture*)res;
1212
1213 assert(res->target != PIPE_BUFFER);
1214 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1215
1216 /* st/dri calls flush twice per frame (not a bug), this prevents double
1217 * decompression. */
1218 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1219 return;
1220
1221 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1222 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1223 0, util_max_layer(res, 0),
1224 rtex->dcc_separate_buffer != NULL);
1225 }
1226
1227 /* Always do the analysis even if DCC is disabled at the moment. */
1228 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1229 rtex->separate_dcc_dirty = false;
1230 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1231 }
1232 }
1233
1234 static void si_decompress_dcc(struct pipe_context *ctx,
1235 struct r600_texture *rtex)
1236 {
1237 if (!rtex->dcc_offset)
1238 return;
1239
1240 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1241 0, util_max_layer(&rtex->resource.b.b, 0),
1242 true);
1243 }
1244
1245 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1246 struct pipe_resource *dst,
1247 unsigned offset, unsigned size,
1248 const void *clear_value_ptr,
1249 int clear_value_size)
1250 {
1251 struct si_context *sctx = (struct si_context*)ctx;
1252 uint32_t dword_value;
1253 unsigned i;
1254
1255 assert(offset % clear_value_size == 0);
1256 assert(size % clear_value_size == 0);
1257
1258 if (clear_value_size > 4) {
1259 const uint32_t *u32 = clear_value_ptr;
1260 bool clear_dword_duplicated = true;
1261
1262 /* See if we can lower large fills to dword fills. */
1263 for (i = 1; i < clear_value_size / 4; i++)
1264 if (u32[0] != u32[i]) {
1265 clear_dword_duplicated = false;
1266 break;
1267 }
1268
1269 if (!clear_dword_duplicated) {
1270 /* Use transform feedback for 64-bit, 96-bit, and
1271 * 128-bit fills.
1272 */
1273 union pipe_color_union clear_value;
1274
1275 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1276 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1277 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1278 size, clear_value_size / 4,
1279 &clear_value);
1280 si_blitter_end(ctx);
1281 return;
1282 }
1283 }
1284
1285 /* Expand the clear value to a dword. */
1286 switch (clear_value_size) {
1287 case 1:
1288 dword_value = *(uint8_t*)clear_value_ptr;
1289 dword_value |= (dword_value << 8) |
1290 (dword_value << 16) |
1291 (dword_value << 24);
1292 break;
1293 case 2:
1294 dword_value = *(uint16_t*)clear_value_ptr;
1295 dword_value |= dword_value << 16;
1296 break;
1297 default:
1298 dword_value = *(uint32_t*)clear_value_ptr;
1299 }
1300
1301 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1302 R600_COHERENCY_SHADER);
1303 }
1304
1305 void si_init_blit_functions(struct si_context *sctx)
1306 {
1307 sctx->b.b.clear = si_clear;
1308 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1309 sctx->b.b.clear_render_target = si_clear_render_target;
1310 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1311 sctx->b.b.resource_copy_region = si_resource_copy_region;
1312 sctx->b.b.blit = si_blit;
1313 sctx->b.b.flush_resource = si_flush_resource;
1314 sctx->b.b.generate_mipmap = si_generate_mipmap;
1315 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1316 sctx->b.decompress_dcc = si_decompress_dcc;
1317 }