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radeonsi: decompress resident textures/images before graphics/compute
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_surface.h"
28
29 enum si_blitter_op /* bitmask */
30 {
31 SI_SAVE_TEXTURES = 1,
32 SI_SAVE_FRAMEBUFFER = 2,
33 SI_SAVE_FRAGMENT_STATE = 4,
34 SI_DISABLE_RENDER_COND = 8,
35
36 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
37
38 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
39
40 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
41 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
42
43 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
44 SI_SAVE_FRAGMENT_STATE,
45
46 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
47 SI_DISABLE_RENDER_COND,
48
49 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
50 };
51
52 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
53 {
54 struct si_context *sctx = (struct si_context *)ctx;
55
56 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
57 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
58 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
59 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
60 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
61 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
62 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
63 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
64 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
65
66 if (op & SI_SAVE_FRAGMENT_STATE) {
67 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
68 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
69 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
70 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
71 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
72 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
73 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
74 }
75
76 if (op & SI_SAVE_FRAMEBUFFER)
77 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
78
79 if (op & SI_SAVE_TEXTURES) {
80 util_blitter_save_fragment_sampler_states(
81 sctx->blitter, 2,
82 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
83
84 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
85 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
86 }
87
88 if (op & SI_DISABLE_RENDER_COND)
89 sctx->b.render_cond_force_off = true;
90 }
91
92 static void si_blitter_end(struct pipe_context *ctx)
93 {
94 struct si_context *sctx = (struct si_context *)ctx;
95
96 sctx->b.render_cond_force_off = false;
97 }
98
99 static unsigned u_max_sample(struct pipe_resource *r)
100 {
101 return r->nr_samples ? r->nr_samples - 1 : 0;
102 }
103
104 static unsigned
105 si_blit_dbcb_copy(struct si_context *sctx,
106 struct r600_texture *src,
107 struct r600_texture *dst,
108 unsigned planes, unsigned level_mask,
109 unsigned first_layer, unsigned last_layer,
110 unsigned first_sample, unsigned last_sample)
111 {
112 struct pipe_surface surf_tmpl = {{0}};
113 unsigned layer, sample, checked_last_layer, max_layer;
114 unsigned fully_copied_levels = 0;
115
116 if (planes & PIPE_MASK_Z)
117 sctx->dbcb_depth_copy_enabled = true;
118 if (planes & PIPE_MASK_S)
119 sctx->dbcb_stencil_copy_enabled = true;
120 si_mark_atom_dirty(sctx, &sctx->db_render_state);
121
122 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
123
124 bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
125 sctx->decompression_enabled = true;
126 sctx->framebuffer.do_update_surf_dirtiness = false;
127
128 while (level_mask) {
129 unsigned level = u_bit_scan(&level_mask);
130
131 /* The smaller the mipmap level, the less layers there are
132 * as far as 3D textures are concerned. */
133 max_layer = util_max_layer(&src->resource.b.b, level);
134 checked_last_layer = MIN2(last_layer, max_layer);
135
136 surf_tmpl.u.tex.level = level;
137
138 for (layer = first_layer; layer <= checked_last_layer; layer++) {
139 struct pipe_surface *zsurf, *cbsurf;
140
141 surf_tmpl.format = src->resource.b.b.format;
142 surf_tmpl.u.tex.first_layer = layer;
143 surf_tmpl.u.tex.last_layer = layer;
144
145 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
146
147 surf_tmpl.format = dst->resource.b.b.format;
148 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
149
150 for (sample = first_sample; sample <= last_sample; sample++) {
151 if (sample != sctx->dbcb_copy_sample) {
152 sctx->dbcb_copy_sample = sample;
153 si_mark_atom_dirty(sctx, &sctx->db_render_state);
154 }
155
156 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
157 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
158 sctx->custom_dsa_flush, 1.0f);
159 si_blitter_end(&sctx->b.b);
160 }
161
162 pipe_surface_reference(&zsurf, NULL);
163 pipe_surface_reference(&cbsurf, NULL);
164 }
165
166 if (first_layer == 0 && last_layer >= max_layer &&
167 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
168 fully_copied_levels |= 1u << level;
169 }
170
171 sctx->decompression_enabled = false;
172 sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
173 sctx->dbcb_depth_copy_enabled = false;
174 sctx->dbcb_stencil_copy_enabled = false;
175 si_mark_atom_dirty(sctx, &sctx->db_render_state);
176
177 return fully_copied_levels;
178 }
179
180 static void si_blit_decompress_depth(struct pipe_context *ctx,
181 struct r600_texture *texture,
182 struct r600_texture *staging,
183 unsigned first_level, unsigned last_level,
184 unsigned first_layer, unsigned last_layer,
185 unsigned first_sample, unsigned last_sample)
186 {
187 const struct util_format_description *desc;
188 unsigned planes = 0;
189
190 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
191
192 desc = util_format_description(staging->resource.b.b.format);
193
194 if (util_format_has_depth(desc))
195 planes |= PIPE_MASK_Z;
196 if (util_format_has_stencil(desc))
197 planes |= PIPE_MASK_S;
198
199 si_blit_dbcb_copy(
200 (struct si_context *)ctx, texture, staging, planes,
201 u_bit_consecutive(first_level, last_level - first_level + 1),
202 first_layer, last_layer, first_sample, last_sample);
203 }
204
205 /* Helper function for si_blit_decompress_zs_in_place.
206 */
207 static void
208 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
209 struct r600_texture *texture,
210 unsigned planes, unsigned level_mask,
211 unsigned first_layer, unsigned last_layer)
212 {
213 struct pipe_surface *zsurf, surf_tmpl = {{0}};
214 unsigned layer, max_layer, checked_last_layer;
215 unsigned fully_decompressed_mask = 0;
216
217 if (!level_mask)
218 return;
219
220 if (planes & PIPE_MASK_S)
221 sctx->db_flush_stencil_inplace = true;
222 if (planes & PIPE_MASK_Z)
223 sctx->db_flush_depth_inplace = true;
224 si_mark_atom_dirty(sctx, &sctx->db_render_state);
225
226 surf_tmpl.format = texture->resource.b.b.format;
227
228 bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
229 sctx->decompression_enabled = true;
230 sctx->framebuffer.do_update_surf_dirtiness = false;
231
232 while (level_mask) {
233 unsigned level = u_bit_scan(&level_mask);
234
235 surf_tmpl.u.tex.level = level;
236
237 /* The smaller the mipmap level, the less layers there are
238 * as far as 3D textures are concerned. */
239 max_layer = util_max_layer(&texture->resource.b.b, level);
240 checked_last_layer = MIN2(last_layer, max_layer);
241
242 for (layer = first_layer; layer <= checked_last_layer; layer++) {
243 surf_tmpl.u.tex.first_layer = layer;
244 surf_tmpl.u.tex.last_layer = layer;
245
246 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
247
248 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
249 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
250 sctx->custom_dsa_flush,
251 1.0f);
252 si_blitter_end(&sctx->b.b);
253
254 pipe_surface_reference(&zsurf, NULL);
255 }
256
257 /* The texture will always be dirty if some layers aren't flushed.
258 * I don't think this case occurs often though. */
259 if (first_layer == 0 && last_layer >= max_layer) {
260 fully_decompressed_mask |= 1u << level;
261 }
262 }
263
264 if (planes & PIPE_MASK_Z)
265 texture->dirty_level_mask &= ~fully_decompressed_mask;
266 if (planes & PIPE_MASK_S)
267 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
268
269 sctx->decompression_enabled = false;
270 sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
271 sctx->db_flush_depth_inplace = false;
272 sctx->db_flush_stencil_inplace = false;
273 si_mark_atom_dirty(sctx, &sctx->db_render_state);
274 }
275
276 /* Helper function of si_flush_depth_texture: decompress the given levels
277 * of Z and/or S planes in place.
278 */
279 static void
280 si_blit_decompress_zs_in_place(struct si_context *sctx,
281 struct r600_texture *texture,
282 unsigned levels_z, unsigned levels_s,
283 unsigned first_layer, unsigned last_layer)
284 {
285 unsigned both = levels_z & levels_s;
286
287 /* First, do combined Z & S decompresses for levels that need it. */
288 if (both) {
289 si_blit_decompress_zs_planes_in_place(
290 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
291 both,
292 first_layer, last_layer);
293 levels_z &= ~both;
294 levels_s &= ~both;
295 }
296
297 /* Now do separate Z and S decompresses. */
298 if (levels_z) {
299 si_blit_decompress_zs_planes_in_place(
300 sctx, texture, PIPE_MASK_Z,
301 levels_z,
302 first_layer, last_layer);
303 }
304
305 if (levels_s) {
306 si_blit_decompress_zs_planes_in_place(
307 sctx, texture, PIPE_MASK_S,
308 levels_s,
309 first_layer, last_layer);
310 }
311 }
312
313 static void
314 si_decompress_depth(struct si_context *sctx,
315 struct r600_texture *tex,
316 unsigned required_planes,
317 unsigned first_level, unsigned last_level,
318 unsigned first_layer, unsigned last_layer)
319 {
320 unsigned inplace_planes = 0;
321 unsigned copy_planes = 0;
322 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
323 unsigned levels_z = 0;
324 unsigned levels_s = 0;
325
326 if (required_planes & PIPE_MASK_Z) {
327 levels_z = level_mask & tex->dirty_level_mask;
328
329 if (levels_z) {
330 if (r600_can_sample_zs(tex, false))
331 inplace_planes |= PIPE_MASK_Z;
332 else
333 copy_planes |= PIPE_MASK_Z;
334 }
335 }
336 if (required_planes & PIPE_MASK_S) {
337 levels_s = level_mask & tex->stencil_dirty_level_mask;
338
339 if (levels_s) {
340 if (r600_can_sample_zs(tex, true))
341 inplace_planes |= PIPE_MASK_S;
342 else
343 copy_planes |= PIPE_MASK_S;
344 }
345 }
346
347 assert(!tex->tc_compatible_htile || levels_z == 0);
348 assert(!tex->tc_compatible_htile || levels_s == 0 ||
349 !r600_can_sample_zs(tex, true));
350
351 /* We may have to allocate the flushed texture here when called from
352 * si_decompress_subresource.
353 */
354 if (copy_planes &&
355 (tex->flushed_depth_texture ||
356 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
357 struct r600_texture *dst = tex->flushed_depth_texture;
358 unsigned fully_copied_levels;
359 unsigned levels = 0;
360
361 assert(tex->flushed_depth_texture);
362
363 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
364 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
365
366 if (copy_planes & PIPE_MASK_Z) {
367 levels |= levels_z;
368 levels_z = 0;
369 }
370 if (copy_planes & PIPE_MASK_S) {
371 levels |= levels_s;
372 levels_s = 0;
373 }
374
375 fully_copied_levels = si_blit_dbcb_copy(
376 sctx, tex, dst, copy_planes, levels,
377 first_layer, last_layer,
378 0, u_max_sample(&tex->resource.b.b));
379
380 if (copy_planes & PIPE_MASK_Z)
381 tex->dirty_level_mask &= ~fully_copied_levels;
382 if (copy_planes & PIPE_MASK_S)
383 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
384 }
385
386 if (inplace_planes) {
387 si_blit_decompress_zs_in_place(
388 sctx, tex,
389 levels_z, levels_s,
390 first_layer, last_layer);
391 }
392 }
393
394 static void
395 si_decompress_sampler_depth_textures(struct si_context *sctx,
396 struct si_textures_info *textures)
397 {
398 unsigned i;
399 unsigned mask = textures->needs_depth_decompress_mask;
400
401 while (mask) {
402 struct pipe_sampler_view *view;
403 struct si_sampler_view *sview;
404 struct r600_texture *tex;
405
406 i = u_bit_scan(&mask);
407
408 view = textures->views.views[i];
409 assert(view);
410 sview = (struct si_sampler_view*)view;
411
412 tex = (struct r600_texture *)view->texture;
413 assert(tex->db_compatible);
414
415 si_decompress_depth(sctx, tex,
416 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
417 view->u.tex.first_level, view->u.tex.last_level,
418 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
419 }
420 }
421
422 static void si_blit_decompress_color(struct pipe_context *ctx,
423 struct r600_texture *rtex,
424 unsigned first_level, unsigned last_level,
425 unsigned first_layer, unsigned last_layer,
426 bool need_dcc_decompress)
427 {
428 struct si_context *sctx = (struct si_context *)ctx;
429 void* custom_blend;
430 unsigned layer, checked_last_layer, max_layer;
431 unsigned level_mask =
432 u_bit_consecutive(first_level, last_level - first_level + 1);
433
434 if (!need_dcc_decompress)
435 level_mask &= rtex->dirty_level_mask;
436 if (!level_mask)
437 return;
438
439 if (rtex->dcc_offset && need_dcc_decompress) {
440 custom_blend = sctx->custom_blend_dcc_decompress;
441
442 /* disable levels without DCC */
443 for (int i = first_level; i <= last_level; i++) {
444 if (!vi_dcc_enabled(rtex, i))
445 level_mask &= ~(1 << i);
446 }
447 } else if (rtex->fmask.size) {
448 custom_blend = sctx->custom_blend_fmask_decompress;
449 } else {
450 custom_blend = sctx->custom_blend_eliminate_fastclear;
451 }
452
453 bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
454 sctx->decompression_enabled = true;
455 sctx->framebuffer.do_update_surf_dirtiness = false;
456
457 while (level_mask) {
458 unsigned level = u_bit_scan(&level_mask);
459
460 /* The smaller the mipmap level, the less layers there are
461 * as far as 3D textures are concerned. */
462 max_layer = util_max_layer(&rtex->resource.b.b, level);
463 checked_last_layer = MIN2(last_layer, max_layer);
464
465 for (layer = first_layer; layer <= checked_last_layer; layer++) {
466 struct pipe_surface *cbsurf, surf_tmpl;
467
468 surf_tmpl.format = rtex->resource.b.b.format;
469 surf_tmpl.u.tex.level = level;
470 surf_tmpl.u.tex.first_layer = layer;
471 surf_tmpl.u.tex.last_layer = layer;
472 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
473
474 si_blitter_begin(ctx, SI_DECOMPRESS);
475 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
476 si_blitter_end(ctx);
477
478 pipe_surface_reference(&cbsurf, NULL);
479 }
480
481 /* The texture will always be dirty if some layers aren't flushed.
482 * I don't think this case occurs often though. */
483 if (first_layer == 0 && last_layer >= max_layer) {
484 rtex->dirty_level_mask &= ~(1 << level);
485 }
486 }
487
488 sctx->decompression_enabled = false;
489 sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
490 }
491
492 static void
493 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
494 unsigned first_level, unsigned last_level)
495 {
496 /* CMASK or DCC can be discarded and we can still end up here. */
497 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
498 return;
499
500 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
501 util_max_layer(&tex->resource.b.b, first_level),
502 false);
503 }
504
505 static void
506 si_decompress_sampler_color_textures(struct si_context *sctx,
507 struct si_textures_info *textures)
508 {
509 unsigned i;
510 unsigned mask = textures->needs_color_decompress_mask;
511
512 while (mask) {
513 struct pipe_sampler_view *view;
514 struct r600_texture *tex;
515
516 i = u_bit_scan(&mask);
517
518 view = textures->views.views[i];
519 assert(view);
520
521 tex = (struct r600_texture *)view->texture;
522
523 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
524 view->u.tex.last_level);
525 }
526 }
527
528 static void
529 si_decompress_image_color_textures(struct si_context *sctx,
530 struct si_images_info *images)
531 {
532 unsigned i;
533 unsigned mask = images->needs_color_decompress_mask;
534
535 while (mask) {
536 const struct pipe_image_view *view;
537 struct r600_texture *tex;
538
539 i = u_bit_scan(&mask);
540
541 view = &images->views[i];
542 assert(view->resource->target != PIPE_BUFFER);
543
544 tex = (struct r600_texture *)view->resource;
545
546 si_decompress_color_texture(sctx, tex, view->u.tex.level,
547 view->u.tex.level);
548 }
549 }
550
551 static void si_check_render_feedback_texture(struct si_context *sctx,
552 struct r600_texture *tex,
553 unsigned first_level,
554 unsigned last_level,
555 unsigned first_layer,
556 unsigned last_layer)
557 {
558 bool render_feedback = false;
559
560 if (!tex->dcc_offset)
561 return;
562
563 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
564 struct r600_surface * surf;
565
566 if (!sctx->framebuffer.state.cbufs[j])
567 continue;
568
569 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
570
571 if (tex == (struct r600_texture *)surf->base.texture &&
572 surf->base.u.tex.level >= first_level &&
573 surf->base.u.tex.level <= last_level &&
574 surf->base.u.tex.first_layer <= last_layer &&
575 surf->base.u.tex.last_layer >= first_layer) {
576 render_feedback = true;
577 break;
578 }
579 }
580
581 if (render_feedback)
582 r600_texture_disable_dcc(&sctx->b, tex);
583 }
584
585 static void si_check_render_feedback_textures(struct si_context *sctx,
586 struct si_textures_info *textures)
587 {
588 uint32_t mask = textures->views.enabled_mask;
589
590 while (mask) {
591 const struct pipe_sampler_view *view;
592 struct r600_texture *tex;
593
594 unsigned i = u_bit_scan(&mask);
595
596 view = textures->views.views[i];
597 if(view->texture->target == PIPE_BUFFER)
598 continue;
599
600 tex = (struct r600_texture *)view->texture;
601
602 si_check_render_feedback_texture(sctx, tex,
603 view->u.tex.first_level,
604 view->u.tex.last_level,
605 view->u.tex.first_layer,
606 view->u.tex.last_layer);
607 }
608 }
609
610 static void si_check_render_feedback_images(struct si_context *sctx,
611 struct si_images_info *images)
612 {
613 uint32_t mask = images->enabled_mask;
614
615 while (mask) {
616 const struct pipe_image_view *view;
617 struct r600_texture *tex;
618
619 unsigned i = u_bit_scan(&mask);
620
621 view = &images->views[i];
622 if (view->resource->target == PIPE_BUFFER)
623 continue;
624
625 tex = (struct r600_texture *)view->resource;
626
627 si_check_render_feedback_texture(sctx, tex,
628 view->u.tex.level,
629 view->u.tex.level,
630 view->u.tex.first_layer,
631 view->u.tex.last_layer);
632 }
633 }
634
635 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
636 {
637 unsigned num_resident_tex_handles;
638 unsigned i;
639
640 num_resident_tex_handles = sctx->resident_tex_handles.size /
641 sizeof(struct si_texture_handle *);
642
643 for (i = 0; i < num_resident_tex_handles; i++) {
644 struct si_texture_handle *tex_handle =
645 *util_dynarray_element(&sctx->resident_tex_handles,
646 struct si_texture_handle *, i);
647 struct pipe_sampler_view *view;
648 struct r600_texture *tex;
649
650 view = tex_handle->view;
651 if (view->texture->target == PIPE_BUFFER)
652 continue;
653
654 tex = (struct r600_texture *)view->texture;
655
656 si_check_render_feedback_texture(sctx, tex,
657 view->u.tex.first_level,
658 view->u.tex.last_level,
659 view->u.tex.first_layer,
660 view->u.tex.last_layer);
661 }
662 }
663
664 static void si_check_render_feedback_resident_images(struct si_context *sctx)
665 {
666 unsigned num_resident_img_handles;
667 unsigned i;
668
669 num_resident_img_handles = sctx->resident_img_handles.size /
670 sizeof(struct si_image_handle *);
671
672 for (i = 0; i < num_resident_img_handles; i++) {
673 struct si_image_handle *img_handle =
674 *util_dynarray_element(&sctx->resident_img_handles,
675 struct si_image_handle *, i);
676 struct pipe_image_view *view;
677 struct r600_texture *tex;
678
679 view = &img_handle->view;
680 if (view->resource->target == PIPE_BUFFER)
681 continue;
682
683 tex = (struct r600_texture *)view->resource;
684
685 si_check_render_feedback_texture(sctx, tex,
686 view->u.tex.level,
687 view->u.tex.level,
688 view->u.tex.first_layer,
689 view->u.tex.last_layer);
690 }
691 }
692
693 static void si_check_render_feedback(struct si_context *sctx)
694 {
695
696 if (!sctx->need_check_render_feedback)
697 return;
698
699 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
700 si_check_render_feedback_images(sctx, &sctx->images[i]);
701 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
702 }
703
704 si_check_render_feedback_resident_images(sctx);
705 si_check_render_feedback_resident_textures(sctx);
706
707 sctx->need_check_render_feedback = false;
708 }
709
710 static void si_decompress_resident_textures(struct si_context *sctx)
711 {
712 unsigned num_resident_tex_handles;
713 unsigned i;
714
715 num_resident_tex_handles = sctx->resident_tex_handles.size /
716 sizeof(struct si_texture_handle *);
717
718 for (i = 0; i < num_resident_tex_handles; i++) {
719 struct si_texture_handle *tex_handle =
720 *util_dynarray_element(&sctx->resident_tex_handles,
721 struct si_texture_handle *, i);
722 struct pipe_sampler_view *view = tex_handle->view;
723 struct si_sampler_view *sview = (struct si_sampler_view *)view;
724 struct r600_texture *tex = (struct r600_texture *)view->texture;
725
726 if (view->texture->target == PIPE_BUFFER)
727 continue;
728
729 if (tex_handle->needs_color_decompress)
730 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
731 view->u.tex.last_level);
732
733 if (tex_handle->needs_depth_decompress)
734 si_decompress_depth(sctx, tex,
735 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
736 view->u.tex.first_level, view->u.tex.last_level,
737 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
738 }
739 }
740
741 static void si_decompress_resident_images(struct si_context *sctx)
742 {
743 unsigned num_resident_img_handles;
744 unsigned i;
745
746 num_resident_img_handles = sctx->resident_img_handles.size /
747 sizeof(struct si_image_handle *);
748
749 for (i = 0; i < num_resident_img_handles; i++) {
750 struct si_image_handle *img_handle =
751 *util_dynarray_element(&sctx->resident_img_handles,
752 struct si_image_handle *, i);
753 struct pipe_image_view *view = &img_handle->view;
754 struct r600_texture *tex = (struct r600_texture *)view->resource;
755
756 if (view->resource->target == PIPE_BUFFER)
757 continue;
758
759 if (img_handle->needs_color_decompress)
760 si_decompress_color_texture(sctx, tex, view->u.tex.level,
761 view->u.tex.level);
762 }
763 }
764
765 static void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
766 {
767 unsigned compressed_colortex_counter, mask;
768
769 if (sctx->blitter->running)
770 return;
771
772 /* Update the compressed_colortex_mask if necessary. */
773 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
774 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
775 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
776 si_update_needs_color_decompress_masks(sctx);
777 }
778
779 /* Decompress color & depth textures if needed. */
780 mask = sctx->shader_needs_decompress_mask & shader_mask;
781 while (mask) {
782 unsigned i = u_bit_scan(&mask);
783
784 if (sctx->samplers[i].needs_depth_decompress_mask) {
785 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
786 }
787 if (sctx->samplers[i].needs_color_decompress_mask) {
788 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
789 }
790 if (sctx->images[i].needs_color_decompress_mask) {
791 si_decompress_image_color_textures(sctx, &sctx->images[i]);
792 }
793 }
794
795 si_decompress_resident_textures(sctx);
796 si_decompress_resident_images(sctx);
797
798 si_check_render_feedback(sctx);
799 }
800
801 void si_decompress_graphics_textures(struct si_context *sctx)
802 {
803 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
804 }
805
806 void si_decompress_compute_textures(struct si_context *sctx)
807 {
808 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
809 }
810
811 static void si_clear(struct pipe_context *ctx, unsigned buffers,
812 const union pipe_color_union *color,
813 double depth, unsigned stencil)
814 {
815 struct si_context *sctx = (struct si_context *)ctx;
816 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
817 struct pipe_surface *zsbuf = fb->zsbuf;
818 struct r600_texture *zstex =
819 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
820
821 if (buffers & PIPE_CLEAR_COLOR) {
822 evergreen_do_fast_color_clear(&sctx->b, fb,
823 &sctx->framebuffer.atom, &buffers,
824 &sctx->framebuffer.dirty_cbufs,
825 color);
826 if (!buffers)
827 return; /* all buffers have been fast cleared */
828 }
829
830 if (buffers & PIPE_CLEAR_COLOR) {
831 int i;
832
833 /* These buffers cannot use fast clear, make sure to disable expansion. */
834 for (i = 0; i < fb->nr_cbufs; i++) {
835 struct r600_texture *tex;
836
837 /* If not clearing this buffer, skip. */
838 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
839 continue;
840
841 if (!fb->cbufs[i])
842 continue;
843
844 tex = (struct r600_texture *)fb->cbufs[i]->texture;
845 if (tex->fmask.size == 0)
846 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
847 }
848 }
849
850 if (zstex && zstex->htile_offset &&
851 zsbuf->u.tex.level == 0 &&
852 zsbuf->u.tex.first_layer == 0 &&
853 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
854 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
855 if (buffers & PIPE_CLEAR_DEPTH &&
856 (!zstex->tc_compatible_htile ||
857 depth == 0 || depth == 1)) {
858 /* Need to disable EXPCLEAR temporarily if clearing
859 * to a new value. */
860 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
861 sctx->db_depth_disable_expclear = true;
862 }
863
864 zstex->depth_clear_value = depth;
865 sctx->framebuffer.dirty_zsbuf = true;
866 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
867 sctx->db_depth_clear = true;
868 si_mark_atom_dirty(sctx, &sctx->db_render_state);
869 }
870
871 /* TC-compatible HTILE only supports stencil clears to 0. */
872 if (buffers & PIPE_CLEAR_STENCIL &&
873 (!zstex->tc_compatible_htile || stencil == 0)) {
874 stencil &= 0xff;
875
876 /* Need to disable EXPCLEAR temporarily if clearing
877 * to a new value. */
878 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
879 sctx->db_stencil_disable_expclear = true;
880 }
881
882 zstex->stencil_clear_value = stencil;
883 sctx->framebuffer.dirty_zsbuf = true;
884 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
885 sctx->db_stencil_clear = true;
886 si_mark_atom_dirty(sctx, &sctx->db_render_state);
887 }
888 }
889
890 si_blitter_begin(ctx, SI_CLEAR);
891 util_blitter_clear(sctx->blitter, fb->width, fb->height,
892 util_framebuffer_get_num_layers(fb),
893 buffers, color, depth, stencil);
894 si_blitter_end(ctx);
895
896 if (sctx->db_depth_clear) {
897 sctx->db_depth_clear = false;
898 sctx->db_depth_disable_expclear = false;
899 zstex->depth_cleared = true;
900 si_mark_atom_dirty(sctx, &sctx->db_render_state);
901 }
902
903 if (sctx->db_stencil_clear) {
904 sctx->db_stencil_clear = false;
905 sctx->db_stencil_disable_expclear = false;
906 zstex->stencil_cleared = true;
907 si_mark_atom_dirty(sctx, &sctx->db_render_state);
908 }
909 }
910
911 static void si_clear_render_target(struct pipe_context *ctx,
912 struct pipe_surface *dst,
913 const union pipe_color_union *color,
914 unsigned dstx, unsigned dsty,
915 unsigned width, unsigned height,
916 bool render_condition_enabled)
917 {
918 struct si_context *sctx = (struct si_context *)ctx;
919
920 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
921 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
922 util_blitter_clear_render_target(sctx->blitter, dst, color,
923 dstx, dsty, width, height);
924 si_blitter_end(ctx);
925 }
926
927 static void si_clear_depth_stencil(struct pipe_context *ctx,
928 struct pipe_surface *dst,
929 unsigned clear_flags,
930 double depth,
931 unsigned stencil,
932 unsigned dstx, unsigned dsty,
933 unsigned width, unsigned height,
934 bool render_condition_enabled)
935 {
936 struct si_context *sctx = (struct si_context *)ctx;
937
938 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
939 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
940 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
941 dstx, dsty, width, height);
942 si_blitter_end(ctx);
943 }
944
945 /* Helper for decompressing a portion of a color or depth resource before
946 * blitting if any decompression is needed.
947 * The driver doesn't decompress resources automatically while u_blitter is
948 * rendering. */
949 static void si_decompress_subresource(struct pipe_context *ctx,
950 struct pipe_resource *tex,
951 unsigned planes, unsigned level,
952 unsigned first_layer, unsigned last_layer)
953 {
954 struct si_context *sctx = (struct si_context *)ctx;
955 struct r600_texture *rtex = (struct r600_texture*)tex;
956
957 if (rtex->db_compatible) {
958 planes &= PIPE_MASK_Z | PIPE_MASK_S;
959
960 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
961 planes &= ~PIPE_MASK_S;
962
963 si_decompress_depth(sctx, rtex, planes,
964 level, level,
965 first_layer, last_layer);
966 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
967 si_blit_decompress_color(ctx, rtex, level, level,
968 first_layer, last_layer, false);
969 }
970 }
971
972 struct texture_orig_info {
973 unsigned format;
974 unsigned width0;
975 unsigned height0;
976 unsigned npix_x;
977 unsigned npix_y;
978 unsigned npix0_x;
979 unsigned npix0_y;
980 };
981
982 void si_resource_copy_region(struct pipe_context *ctx,
983 struct pipe_resource *dst,
984 unsigned dst_level,
985 unsigned dstx, unsigned dsty, unsigned dstz,
986 struct pipe_resource *src,
987 unsigned src_level,
988 const struct pipe_box *src_box)
989 {
990 struct si_context *sctx = (struct si_context *)ctx;
991 struct r600_texture *rsrc = (struct r600_texture*)src;
992 struct pipe_surface *dst_view, dst_templ;
993 struct pipe_sampler_view src_templ, *src_view;
994 unsigned dst_width, dst_height, src_width0, src_height0;
995 unsigned dst_width0, dst_height0, src_force_level = 0;
996 struct pipe_box sbox, dstbox;
997
998 /* Handle buffers first. */
999 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
1000 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
1001 return;
1002 }
1003
1004 assert(u_max_sample(dst) == u_max_sample(src));
1005
1006 /* The driver doesn't decompress resources automatically while
1007 * u_blitter is rendering. */
1008 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
1009 src_box->z, src_box->z + src_box->depth - 1);
1010
1011 dst_width = u_minify(dst->width0, dst_level);
1012 dst_height = u_minify(dst->height0, dst_level);
1013 dst_width0 = dst->width0;
1014 dst_height0 = dst->height0;
1015 src_width0 = src->width0;
1016 src_height0 = src->height0;
1017
1018 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
1019 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
1020
1021 if (util_format_is_compressed(src->format) ||
1022 util_format_is_compressed(dst->format)) {
1023 unsigned blocksize = rsrc->surface.bpe;
1024
1025 if (blocksize == 8)
1026 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
1027 else
1028 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
1029 dst_templ.format = src_templ.format;
1030
1031 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1032 dst_height = util_format_get_nblocksy(dst->format, dst_height);
1033 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1034 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
1035 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1036 src_height0 = util_format_get_nblocksy(src->format, src_height0);
1037
1038 dstx = util_format_get_nblocksx(dst->format, dstx);
1039 dsty = util_format_get_nblocksy(dst->format, dsty);
1040
1041 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1042 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
1043 sbox.z = src_box->z;
1044 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1045 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
1046 sbox.depth = src_box->depth;
1047 src_box = &sbox;
1048
1049 src_force_level = src_level;
1050 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
1051 if (util_format_is_subsampled_422(src->format)) {
1052 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1053 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1054
1055 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1056 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1057 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1058
1059 dstx = util_format_get_nblocksx(dst->format, dstx);
1060
1061 sbox = *src_box;
1062 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1063 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1064 src_box = &sbox;
1065 } else {
1066 unsigned blocksize = rsrc->surface.bpe;
1067
1068 switch (blocksize) {
1069 case 1:
1070 dst_templ.format = PIPE_FORMAT_R8_UNORM;
1071 src_templ.format = PIPE_FORMAT_R8_UNORM;
1072 break;
1073 case 2:
1074 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
1075 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
1076 break;
1077 case 4:
1078 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1079 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1080 break;
1081 case 8:
1082 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1083 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1084 break;
1085 case 16:
1086 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1087 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1088 break;
1089 default:
1090 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1091 util_format_short_name(src->format), blocksize);
1092 assert(0);
1093 }
1094 }
1095 }
1096
1097 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
1098 dst_templ.format);
1099 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
1100 src_templ.format);
1101
1102 /* Initialize the surface. */
1103 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
1104 dst_width0, dst_height0,
1105 dst_width, dst_height);
1106
1107 /* Initialize the sampler view. */
1108 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1109 src_width0, src_height0,
1110 src_force_level);
1111
1112 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1113 abs(src_box->depth), &dstbox);
1114
1115 /* Copy. */
1116 si_blitter_begin(ctx, SI_COPY);
1117 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1118 src_view, src_box, src_width0, src_height0,
1119 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1120 false);
1121 si_blitter_end(ctx);
1122
1123 pipe_surface_reference(&dst_view, NULL);
1124 pipe_sampler_view_reference(&src_view, NULL);
1125 }
1126
1127 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1128 const struct pipe_blit_info *info)
1129 {
1130 struct si_context *sctx = (struct si_context*)ctx;
1131 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1132 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1133 MAYBE_UNUSED struct r600_texture *rtmp;
1134 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1135 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1136 enum pipe_format format = info->src.format;
1137 unsigned sample_mask = ~0;
1138 struct pipe_resource *tmp, templ;
1139 struct pipe_blit_info blit;
1140
1141 /* Check basic requirements for hw resolve. */
1142 if (!(info->src.resource->nr_samples > 1 &&
1143 info->dst.resource->nr_samples <= 1 &&
1144 !util_format_is_pure_integer(format) &&
1145 !util_format_is_depth_or_stencil(format) &&
1146 util_max_layer(info->src.resource, 0) == 0))
1147 return false;
1148
1149 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1150 * the format is R16G16. Use R16A16, which does work.
1151 */
1152 if (format == PIPE_FORMAT_R16G16_UNORM)
1153 format = PIPE_FORMAT_R16A16_UNORM;
1154 if (format == PIPE_FORMAT_R16G16_SNORM)
1155 format = PIPE_FORMAT_R16A16_SNORM;
1156
1157 /* Check the remaining requirements for hw resolve. */
1158 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1159 !info->scissor_enable &&
1160 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1161 util_is_format_compatible(util_format_description(info->src.format),
1162 util_format_description(info->dst.format)) &&
1163 dst_width == info->src.resource->width0 &&
1164 dst_height == info->src.resource->height0 &&
1165 info->dst.box.x == 0 &&
1166 info->dst.box.y == 0 &&
1167 info->dst.box.width == dst_width &&
1168 info->dst.box.height == dst_height &&
1169 info->dst.box.depth == 1 &&
1170 info->src.box.x == 0 &&
1171 info->src.box.y == 0 &&
1172 info->src.box.width == dst_width &&
1173 info->src.box.height == dst_height &&
1174 info->src.box.depth == 1 &&
1175 !dst->surface.is_linear &&
1176 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1177 /* Check the last constraint. */
1178 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1179 /* The next fast clear will switch to this mode to
1180 * get direct hw resolve next time if the mode is
1181 * different now.
1182 */
1183 src->last_msaa_resolve_target_micro_mode =
1184 dst->surface.micro_tile_mode;
1185 goto resolve_to_temp;
1186 }
1187
1188 /* Resolving into a surface with DCC is unsupported. Since
1189 * it's being overwritten anyway, clear it to uncompressed.
1190 * This is still the fastest codepath even with this clear.
1191 */
1192 if (vi_dcc_enabled(dst, info->dst.level)) {
1193 /* TODO: Implement per-level DCC clears for GFX9. */
1194 if (sctx->b.chip_class >= GFX9 &&
1195 info->dst.resource->last_level != 0)
1196 goto resolve_to_temp;
1197
1198 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1199 0xFFFFFFFF);
1200 dst->dirty_level_mask &= ~(1 << info->dst.level);
1201 }
1202
1203 /* Resolve directly from src to dst. */
1204 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1205 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1206 util_blitter_custom_resolve_color(sctx->blitter,
1207 info->dst.resource, info->dst.level,
1208 info->dst.box.z,
1209 info->src.resource, info->src.box.z,
1210 sample_mask, sctx->custom_blend_resolve,
1211 format);
1212 si_blitter_end(ctx);
1213 return true;
1214 }
1215
1216 resolve_to_temp:
1217 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1218 * a temporary texture and blit.
1219 */
1220 memset(&templ, 0, sizeof(templ));
1221 templ.target = PIPE_TEXTURE_2D;
1222 templ.format = info->src.resource->format;
1223 templ.width0 = info->src.resource->width0;
1224 templ.height0 = info->src.resource->height0;
1225 templ.depth0 = 1;
1226 templ.array_size = 1;
1227 templ.usage = PIPE_USAGE_DEFAULT;
1228 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1229 R600_RESOURCE_FLAG_DISABLE_DCC;
1230
1231 /* The src and dst microtile modes must be the same. */
1232 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1233 templ.bind = PIPE_BIND_SCANOUT;
1234 else
1235 templ.bind = 0;
1236
1237 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1238 if (!tmp)
1239 return false;
1240 rtmp = (struct r600_texture*)tmp;
1241
1242 assert(!rtmp->surface.is_linear);
1243 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1244
1245 /* resolve */
1246 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
1247 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1248 util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
1249 info->src.resource, info->src.box.z,
1250 sample_mask, sctx->custom_blend_resolve,
1251 format);
1252 si_blitter_end(ctx);
1253
1254 /* blit */
1255 blit = *info;
1256 blit.src.resource = tmp;
1257 blit.src.box.z = 0;
1258
1259 si_blitter_begin(ctx, SI_BLIT |
1260 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1261 util_blitter_blit(sctx->blitter, &blit);
1262 si_blitter_end(ctx);
1263
1264 pipe_resource_reference(&tmp, NULL);
1265 return true;
1266 }
1267
1268 static void si_blit(struct pipe_context *ctx,
1269 const struct pipe_blit_info *info)
1270 {
1271 struct si_context *sctx = (struct si_context*)ctx;
1272 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1273
1274 if (do_hardware_msaa_resolve(ctx, info)) {
1275 return;
1276 }
1277
1278 /* Using SDMA for copying to a linear texture in GTT is much faster.
1279 * This improves DRI PRIME performance.
1280 *
1281 * resource_copy_region can't do this yet, because dma_copy calls it
1282 * on failure (recursion).
1283 */
1284 if (rdst->surface.is_linear &&
1285 sctx->b.dma_copy &&
1286 util_can_blit_via_copy_region(info, false)) {
1287 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1288 info->dst.box.x, info->dst.box.y,
1289 info->dst.box.z,
1290 info->src.resource, info->src.level,
1291 &info->src.box);
1292 return;
1293 }
1294
1295 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1296
1297 /* The driver doesn't decompress resources automatically while
1298 * u_blitter is rendering. */
1299 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1300 info->src.level,
1301 info->src.format);
1302 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1303 info->dst.level,
1304 info->dst.format);
1305 si_decompress_subresource(ctx, info->src.resource, info->mask,
1306 info->src.level,
1307 info->src.box.z,
1308 info->src.box.z + info->src.box.depth - 1);
1309
1310 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1311 util_try_blit_via_copy_region(ctx, info))
1312 return;
1313
1314 si_blitter_begin(ctx, SI_BLIT |
1315 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1316 util_blitter_blit(sctx->blitter, info);
1317 si_blitter_end(ctx);
1318 }
1319
1320 static boolean si_generate_mipmap(struct pipe_context *ctx,
1321 struct pipe_resource *tex,
1322 enum pipe_format format,
1323 unsigned base_level, unsigned last_level,
1324 unsigned first_layer, unsigned last_layer)
1325 {
1326 struct si_context *sctx = (struct si_context*)ctx;
1327 struct r600_texture *rtex = (struct r600_texture *)tex;
1328
1329 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1330 return false;
1331
1332 /* The driver doesn't decompress resources automatically while
1333 * u_blitter is rendering. */
1334 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1335 format);
1336 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1337 base_level, first_layer, last_layer);
1338
1339 /* Clear dirty_level_mask for the levels that will be overwritten. */
1340 assert(base_level < last_level);
1341 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1342 last_level - base_level);
1343
1344 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1345 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1346 base_level, last_level,
1347 first_layer, last_layer);
1348 si_blitter_end(ctx);
1349 return true;
1350 }
1351
1352 static void si_flush_resource(struct pipe_context *ctx,
1353 struct pipe_resource *res)
1354 {
1355 struct r600_texture *rtex = (struct r600_texture*)res;
1356
1357 assert(res->target != PIPE_BUFFER);
1358 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1359
1360 /* st/dri calls flush twice per frame (not a bug), this prevents double
1361 * decompression. */
1362 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1363 return;
1364
1365 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1366 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1367 0, util_max_layer(res, 0),
1368 rtex->dcc_separate_buffer != NULL);
1369 }
1370
1371 /* Always do the analysis even if DCC is disabled at the moment. */
1372 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1373 rtex->separate_dcc_dirty = false;
1374 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1375 }
1376 }
1377
1378 static void si_decompress_dcc(struct pipe_context *ctx,
1379 struct r600_texture *rtex)
1380 {
1381 if (!rtex->dcc_offset)
1382 return;
1383
1384 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1385 0, util_max_layer(&rtex->resource.b.b, 0),
1386 true);
1387 }
1388
1389 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1390 struct pipe_resource *dst,
1391 unsigned offset, unsigned size,
1392 const void *clear_value_ptr,
1393 int clear_value_size)
1394 {
1395 struct si_context *sctx = (struct si_context*)ctx;
1396 uint32_t dword_value;
1397 unsigned i;
1398
1399 assert(offset % clear_value_size == 0);
1400 assert(size % clear_value_size == 0);
1401
1402 if (clear_value_size > 4) {
1403 const uint32_t *u32 = clear_value_ptr;
1404 bool clear_dword_duplicated = true;
1405
1406 /* See if we can lower large fills to dword fills. */
1407 for (i = 1; i < clear_value_size / 4; i++)
1408 if (u32[0] != u32[i]) {
1409 clear_dword_duplicated = false;
1410 break;
1411 }
1412
1413 if (!clear_dword_duplicated) {
1414 /* Use transform feedback for 64-bit, 96-bit, and
1415 * 128-bit fills.
1416 */
1417 union pipe_color_union clear_value;
1418
1419 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1420 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1421 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1422 size, clear_value_size / 4,
1423 &clear_value);
1424 si_blitter_end(ctx);
1425 return;
1426 }
1427 }
1428
1429 /* Expand the clear value to a dword. */
1430 switch (clear_value_size) {
1431 case 1:
1432 dword_value = *(uint8_t*)clear_value_ptr;
1433 dword_value |= (dword_value << 8) |
1434 (dword_value << 16) |
1435 (dword_value << 24);
1436 break;
1437 case 2:
1438 dword_value = *(uint16_t*)clear_value_ptr;
1439 dword_value |= dword_value << 16;
1440 break;
1441 default:
1442 dword_value = *(uint32_t*)clear_value_ptr;
1443 }
1444
1445 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1446 R600_COHERENCY_SHADER);
1447 }
1448
1449 void si_init_blit_functions(struct si_context *sctx)
1450 {
1451 sctx->b.b.clear = si_clear;
1452 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1453 sctx->b.b.clear_render_target = si_clear_render_target;
1454 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1455 sctx->b.b.resource_copy_region = si_resource_copy_region;
1456 sctx->b.b.blit = si_blit;
1457 sctx->b.b.flush_resource = si_flush_resource;
1458 sctx->b.b.generate_mipmap = si_generate_mipmap;
1459 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1460 sctx->b.decompress_dcc = si_decompress_dcc;
1461 }