radeonsi: disable DCC on handle export if expecting write access
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "util/u_format.h"
26 #include "util/u_surface.h"
27
28 enum si_blitter_op /* bitmask */
29 {
30 SI_SAVE_TEXTURES = 1,
31 SI_SAVE_FRAMEBUFFER = 2,
32 SI_SAVE_FRAGMENT_STATE = 4,
33 SI_DISABLE_RENDER_COND = 8,
34
35 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
36
37 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
38
39 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
40 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
41
42 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
43 SI_SAVE_FRAGMENT_STATE,
44
45 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
46 SI_DISABLE_RENDER_COND,
47
48 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
49 };
50
51 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
52 {
53 struct si_context *sctx = (struct si_context *)ctx;
54
55 r600_suspend_nontimer_queries(&sctx->b);
56
57 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
58 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
59 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
60 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
61 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
62 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
63 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
64 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
65 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
66
67 if (op & SI_SAVE_FRAGMENT_STATE) {
68 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
69 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
70 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
71 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
72 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
73 util_blitter_save_viewport(sctx->blitter, &sctx->viewports.states[0]);
74 util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
75 }
76
77 if (op & SI_SAVE_FRAMEBUFFER)
78 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
79
80 if (op & SI_SAVE_TEXTURES) {
81 util_blitter_save_fragment_sampler_states(
82 sctx->blitter, 2,
83 sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
84
85 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
86 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
87 }
88
89 if (op & SI_DISABLE_RENDER_COND)
90 sctx->b.render_cond_force_off = true;
91 }
92
93 static void si_blitter_end(struct pipe_context *ctx)
94 {
95 struct si_context *sctx = (struct si_context *)ctx;
96
97 sctx->b.render_cond_force_off = false;
98 r600_resume_nontimer_queries(&sctx->b);
99 }
100
101 static unsigned u_max_sample(struct pipe_resource *r)
102 {
103 return r->nr_samples ? r->nr_samples - 1 : 0;
104 }
105
106 static void si_blit_decompress_depth(struct pipe_context *ctx,
107 struct r600_texture *texture,
108 struct r600_texture *staging,
109 unsigned first_level, unsigned last_level,
110 unsigned first_layer, unsigned last_layer,
111 unsigned first_sample, unsigned last_sample)
112 {
113 struct si_context *sctx = (struct si_context *)ctx;
114 unsigned layer, level, sample, checked_last_layer, max_layer, max_sample;
115 float depth = 1.0f;
116 const struct util_format_description *desc;
117 struct r600_texture *flushed_depth_texture = staging ?
118 staging : texture->flushed_depth_texture;
119
120 if (!staging && !texture->dirty_level_mask)
121 return;
122
123 max_sample = u_max_sample(&texture->resource.b.b);
124
125 desc = util_format_description(flushed_depth_texture->resource.b.b.format);
126
127 if (util_format_has_depth(desc))
128 sctx->dbcb_depth_copy_enabled = true;
129 if (util_format_has_stencil(desc))
130 sctx->dbcb_stencil_copy_enabled = true;
131
132 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
133
134 for (level = first_level; level <= last_level; level++) {
135 if (!staging && !(texture->dirty_level_mask & (1 << level)))
136 continue;
137
138 /* The smaller the mipmap level, the less layers there are
139 * as far as 3D textures are concerned. */
140 max_layer = util_max_layer(&texture->resource.b.b, level);
141 checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
142
143 for (layer = first_layer; layer <= checked_last_layer; layer++) {
144 for (sample = first_sample; sample <= last_sample; sample++) {
145 struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
146
147 sctx->dbcb_copy_sample = sample;
148 si_mark_atom_dirty(sctx, &sctx->db_render_state);
149
150 surf_tmpl.format = texture->resource.b.b.format;
151 surf_tmpl.u.tex.level = level;
152 surf_tmpl.u.tex.first_layer = layer;
153 surf_tmpl.u.tex.last_layer = layer;
154
155 zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl);
156
157 surf_tmpl.format = flushed_depth_texture->resource.b.b.format;
158 cbsurf = ctx->create_surface(ctx,
159 (struct pipe_resource*)flushed_depth_texture, &surf_tmpl);
160
161 si_blitter_begin(ctx, SI_DECOMPRESS);
162 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
163 sctx->custom_dsa_flush, depth);
164 si_blitter_end(ctx);
165
166 pipe_surface_reference(&zsurf, NULL);
167 pipe_surface_reference(&cbsurf, NULL);
168 }
169 }
170
171 /* The texture will always be dirty if some layers aren't flushed.
172 * I don't think this case can occur though. */
173 if (!staging &&
174 first_layer == 0 && last_layer == max_layer &&
175 first_sample == 0 && last_sample == max_sample) {
176 texture->dirty_level_mask &= ~(1 << level);
177 }
178 }
179
180 sctx->dbcb_depth_copy_enabled = false;
181 sctx->dbcb_stencil_copy_enabled = false;
182 si_mark_atom_dirty(sctx, &sctx->db_render_state);
183 }
184
185 static void si_blit_decompress_depth_in_place(struct si_context *sctx,
186 struct r600_texture *texture,
187 bool is_stencil_sampler,
188 unsigned first_level, unsigned last_level,
189 unsigned first_layer, unsigned last_layer)
190 {
191 struct pipe_surface *zsurf, surf_tmpl = {{0}};
192 unsigned layer, max_layer, checked_last_layer, level;
193 unsigned *dirty_level_mask;
194
195 if (is_stencil_sampler) {
196 sctx->db_flush_stencil_inplace = true;
197 dirty_level_mask = &texture->stencil_dirty_level_mask;
198 } else {
199 sctx->db_flush_depth_inplace = true;
200 dirty_level_mask = &texture->dirty_level_mask;
201 }
202 si_mark_atom_dirty(sctx, &sctx->db_render_state);
203
204 surf_tmpl.format = texture->resource.b.b.format;
205
206 for (level = first_level; level <= last_level; level++) {
207 if (!(*dirty_level_mask & (1 << level)))
208 continue;
209
210 surf_tmpl.u.tex.level = level;
211
212 /* The smaller the mipmap level, the less layers there are
213 * as far as 3D textures are concerned. */
214 max_layer = util_max_layer(&texture->resource.b.b, level);
215 checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
216
217 for (layer = first_layer; layer <= checked_last_layer; layer++) {
218 surf_tmpl.u.tex.first_layer = layer;
219 surf_tmpl.u.tex.last_layer = layer;
220
221 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
222
223 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
224 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
225 sctx->custom_dsa_flush,
226 1.0f);
227 si_blitter_end(&sctx->b.b);
228
229 pipe_surface_reference(&zsurf, NULL);
230 }
231
232 /* The texture will always be dirty if some layers aren't flushed.
233 * I don't think this case occurs often though. */
234 if (first_layer == 0 && last_layer == max_layer) {
235 *dirty_level_mask &= ~(1 << level);
236 }
237 }
238
239 sctx->db_flush_depth_inplace = false;
240 sctx->db_flush_stencil_inplace = false;
241 si_mark_atom_dirty(sctx, &sctx->db_render_state);
242 }
243
244 void si_flush_depth_textures(struct si_context *sctx,
245 struct si_textures_info *textures)
246 {
247 unsigned i;
248 unsigned mask = textures->depth_texture_mask;
249
250 while (mask) {
251 struct pipe_sampler_view *view;
252 struct si_sampler_view *sview;
253 struct r600_texture *tex;
254
255 i = u_bit_scan(&mask);
256
257 view = textures->views.views[i];
258 assert(view);
259 sview = (struct si_sampler_view*)view;
260
261 tex = (struct r600_texture *)view->texture;
262 assert(tex->is_depth && !tex->is_flushing_texture);
263
264 si_blit_decompress_depth_in_place(sctx, tex,
265 sview->is_stencil_sampler,
266 view->u.tex.first_level, view->u.tex.last_level,
267 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
268 }
269 }
270
271 static void si_blit_decompress_color(struct pipe_context *ctx,
272 struct r600_texture *rtex,
273 unsigned first_level, unsigned last_level,
274 unsigned first_layer, unsigned last_layer,
275 bool need_dcc_decompress)
276 {
277 struct si_context *sctx = (struct si_context *)ctx;
278 unsigned layer, level, checked_last_layer, max_layer;
279
280 if (!rtex->dirty_level_mask && !need_dcc_decompress)
281 return;
282
283 for (level = first_level; level <= last_level; level++) {
284 void* custom_blend;
285
286 if (!(rtex->dirty_level_mask & (1 << level)) && !need_dcc_decompress)
287 continue;
288
289 if (rtex->dcc_offset && need_dcc_decompress) {
290 custom_blend = sctx->custom_blend_dcc_decompress;
291 } else if (rtex->fmask.size) {
292 custom_blend = sctx->custom_blend_decompress;
293 } else {
294 custom_blend = sctx->custom_blend_fastclear;
295 }
296
297 /* The smaller the mipmap level, the less layers there are
298 * as far as 3D textures are concerned. */
299 max_layer = util_max_layer(&rtex->resource.b.b, level);
300 checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
301
302 for (layer = first_layer; layer <= checked_last_layer; layer++) {
303 struct pipe_surface *cbsurf, surf_tmpl;
304
305 surf_tmpl.format = rtex->resource.b.b.format;
306 surf_tmpl.u.tex.level = level;
307 surf_tmpl.u.tex.first_layer = layer;
308 surf_tmpl.u.tex.last_layer = layer;
309 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
310
311 si_blitter_begin(ctx, SI_DECOMPRESS);
312 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
313 si_blitter_end(ctx);
314
315 pipe_surface_reference(&cbsurf, NULL);
316 }
317
318 /* The texture will always be dirty if some layers aren't flushed.
319 * I don't think this case occurs often though. */
320 if (first_layer == 0 && last_layer == max_layer) {
321 rtex->dirty_level_mask &= ~(1 << level);
322 }
323 }
324 }
325
326 void si_decompress_color_textures(struct si_context *sctx,
327 struct si_textures_info *textures)
328 {
329 unsigned i;
330 unsigned mask = textures->compressed_colortex_mask;
331
332 while (mask) {
333 struct pipe_sampler_view *view;
334 struct r600_texture *tex;
335
336 i = u_bit_scan(&mask);
337
338 view = textures->views.views[i];
339 assert(view);
340
341 tex = (struct r600_texture *)view->texture;
342 assert(tex->cmask.size || tex->fmask.size || tex->dcc_offset);
343
344 si_blit_decompress_color(&sctx->b.b, tex,
345 view->u.tex.first_level, view->u.tex.last_level,
346 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level),
347 false);
348 }
349 }
350
351 static void si_clear(struct pipe_context *ctx, unsigned buffers,
352 const union pipe_color_union *color,
353 double depth, unsigned stencil)
354 {
355 struct si_context *sctx = (struct si_context *)ctx;
356 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
357 struct pipe_surface *zsbuf = fb->zsbuf;
358 struct r600_texture *zstex =
359 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
360
361 if (buffers & PIPE_CLEAR_COLOR) {
362 evergreen_do_fast_color_clear(&sctx->b, fb,
363 &sctx->framebuffer.atom, &buffers,
364 &sctx->framebuffer.dirty_cbufs,
365 color);
366 if (!buffers)
367 return; /* all buffers have been fast cleared */
368 }
369
370 if (buffers & PIPE_CLEAR_COLOR) {
371 int i;
372
373 /* These buffers cannot use fast clear, make sure to disable expansion. */
374 for (i = 0; i < fb->nr_cbufs; i++) {
375 struct r600_texture *tex;
376
377 /* If not clearing this buffer, skip. */
378 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
379 continue;
380
381 if (!fb->cbufs[i])
382 continue;
383
384 tex = (struct r600_texture *)fb->cbufs[i]->texture;
385 if (tex->fmask.size == 0)
386 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
387 }
388 }
389
390 if (zstex && zstex->htile_buffer &&
391 zsbuf->u.tex.level == 0 &&
392 zsbuf->u.tex.first_layer == 0 &&
393 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
394 if (buffers & PIPE_CLEAR_DEPTH) {
395 /* Need to disable EXPCLEAR temporarily if clearing
396 * to a new value. */
397 if (zstex->depth_cleared && zstex->depth_clear_value != depth) {
398 sctx->db_depth_disable_expclear = true;
399 }
400
401 zstex->depth_clear_value = depth;
402 sctx->framebuffer.dirty_zsbuf = true;
403 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
404 sctx->db_depth_clear = true;
405 si_mark_atom_dirty(sctx, &sctx->db_render_state);
406 }
407
408 if (buffers & PIPE_CLEAR_STENCIL) {
409 stencil &= 0xff;
410
411 /* Need to disable EXPCLEAR temporarily if clearing
412 * to a new value. */
413 if (zstex->stencil_cleared && zstex->stencil_clear_value != stencil) {
414 sctx->db_stencil_disable_expclear = true;
415 }
416
417 zstex->stencil_clear_value = stencil;
418 sctx->framebuffer.dirty_zsbuf = true;
419 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
420 sctx->db_stencil_clear = true;
421 si_mark_atom_dirty(sctx, &sctx->db_render_state);
422 }
423 }
424
425 si_blitter_begin(ctx, SI_CLEAR);
426 util_blitter_clear(sctx->blitter, fb->width, fb->height,
427 util_framebuffer_get_num_layers(fb),
428 buffers, color, depth, stencil);
429 si_blitter_end(ctx);
430
431 if (sctx->db_depth_clear) {
432 sctx->db_depth_clear = false;
433 sctx->db_depth_disable_expclear = false;
434 zstex->depth_cleared = true;
435 si_mark_atom_dirty(sctx, &sctx->db_render_state);
436 }
437
438 if (sctx->db_stencil_clear) {
439 sctx->db_stencil_clear = false;
440 sctx->db_stencil_disable_expclear = false;
441 zstex->stencil_cleared = true;
442 si_mark_atom_dirty(sctx, &sctx->db_render_state);
443 }
444 }
445
446 static void si_clear_render_target(struct pipe_context *ctx,
447 struct pipe_surface *dst,
448 const union pipe_color_union *color,
449 unsigned dstx, unsigned dsty,
450 unsigned width, unsigned height)
451 {
452 struct si_context *sctx = (struct si_context *)ctx;
453
454 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
455 util_blitter_clear_render_target(sctx->blitter, dst, color,
456 dstx, dsty, width, height);
457 si_blitter_end(ctx);
458 }
459
460 static void si_clear_depth_stencil(struct pipe_context *ctx,
461 struct pipe_surface *dst,
462 unsigned clear_flags,
463 double depth,
464 unsigned stencil,
465 unsigned dstx, unsigned dsty,
466 unsigned width, unsigned height)
467 {
468 struct si_context *sctx = (struct si_context *)ctx;
469
470 si_blitter_begin(ctx, SI_CLEAR_SURFACE);
471 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
472 dstx, dsty, width, height);
473 si_blitter_end(ctx);
474 }
475
476 /* Helper for decompressing a portion of a color or depth resource before
477 * blitting if any decompression is needed.
478 * The driver doesn't decompress resources automatically while u_blitter is
479 * rendering. */
480 static void si_decompress_subresource(struct pipe_context *ctx,
481 struct pipe_resource *tex,
482 unsigned level,
483 unsigned first_layer, unsigned last_layer)
484 {
485 struct si_context *sctx = (struct si_context *)ctx;
486 struct r600_texture *rtex = (struct r600_texture*)tex;
487
488 if (rtex->is_depth && !rtex->is_flushing_texture) {
489 si_blit_decompress_depth_in_place(sctx, rtex, false,
490 level, level,
491 first_layer, last_layer);
492 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
493 si_blit_decompress_depth_in_place(sctx, rtex, true,
494 level, level,
495 first_layer, last_layer);
496 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
497 si_blit_decompress_color(ctx, rtex, level, level,
498 first_layer, last_layer, false);
499 }
500 }
501
502 struct texture_orig_info {
503 unsigned format;
504 unsigned width0;
505 unsigned height0;
506 unsigned npix_x;
507 unsigned npix_y;
508 unsigned npix0_x;
509 unsigned npix0_y;
510 };
511
512 void si_resource_copy_region(struct pipe_context *ctx,
513 struct pipe_resource *dst,
514 unsigned dst_level,
515 unsigned dstx, unsigned dsty, unsigned dstz,
516 struct pipe_resource *src,
517 unsigned src_level,
518 const struct pipe_box *src_box)
519 {
520 struct si_context *sctx = (struct si_context *)ctx;
521 struct pipe_surface *dst_view, dst_templ;
522 struct pipe_sampler_view src_templ, *src_view;
523 unsigned dst_width, dst_height, src_width0, src_height0;
524 unsigned src_force_level = 0;
525 struct pipe_box sbox, dstbox;
526
527 /* Handle buffers first. */
528 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
529 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, false);
530 return;
531 }
532
533 assert(u_max_sample(dst) == u_max_sample(src));
534
535 /* The driver doesn't decompress resources automatically while
536 * u_blitter is rendering. */
537 si_decompress_subresource(ctx, src, src_level,
538 src_box->z, src_box->z + src_box->depth - 1);
539
540 dst_width = u_minify(dst->width0, dst_level);
541 dst_height = u_minify(dst->height0, dst_level);
542 src_width0 = src->width0;
543 src_height0 = src->height0;
544
545 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
546 util_blitter_default_src_texture(&src_templ, src, src_level);
547
548 if (util_format_is_compressed(src->format) ||
549 util_format_is_compressed(dst->format)) {
550 unsigned blocksize = util_format_get_blocksize(src->format);
551
552 if (blocksize == 8)
553 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
554 else
555 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
556 dst_templ.format = src_templ.format;
557
558 dst_width = util_format_get_nblocksx(dst->format, dst_width);
559 dst_height = util_format_get_nblocksy(dst->format, dst_height);
560 src_width0 = util_format_get_nblocksx(src->format, src_width0);
561 src_height0 = util_format_get_nblocksy(src->format, src_height0);
562
563 dstx = util_format_get_nblocksx(dst->format, dstx);
564 dsty = util_format_get_nblocksy(dst->format, dsty);
565
566 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
567 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
568 sbox.z = src_box->z;
569 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
570 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
571 sbox.depth = src_box->depth;
572 src_box = &sbox;
573
574 src_force_level = src_level;
575 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src) ||
576 /* also *8_SNORM has precision issues, use UNORM instead */
577 util_format_is_snorm8(src->format)) {
578 if (util_format_is_subsampled_422(src->format)) {
579 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
580 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
581
582 dst_width = util_format_get_nblocksx(dst->format, dst_width);
583 src_width0 = util_format_get_nblocksx(src->format, src_width0);
584
585 dstx = util_format_get_nblocksx(dst->format, dstx);
586
587 sbox = *src_box;
588 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
589 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
590 src_box = &sbox;
591 } else {
592 unsigned blocksize = util_format_get_blocksize(src->format);
593
594 switch (blocksize) {
595 case 1:
596 dst_templ.format = PIPE_FORMAT_R8_UNORM;
597 src_templ.format = PIPE_FORMAT_R8_UNORM;
598 break;
599 case 2:
600 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
601 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
602 break;
603 case 4:
604 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
605 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
606 break;
607 case 8:
608 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
609 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
610 break;
611 case 16:
612 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
613 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
614 break;
615 default:
616 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
617 util_format_short_name(src->format), blocksize);
618 assert(0);
619 }
620 }
621 }
622
623 /* Initialize the surface. */
624 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
625 dst_width, dst_height);
626
627 /* Initialize the sampler view. */
628 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
629 src_width0, src_height0,
630 src_force_level);
631
632 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
633 abs(src_box->depth), &dstbox);
634
635 /* Copy. */
636 si_blitter_begin(ctx, SI_COPY);
637 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
638 src_view, src_box, src_width0, src_height0,
639 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
640 FALSE);
641 si_blitter_end(ctx);
642
643 pipe_surface_reference(&dst_view, NULL);
644 pipe_sampler_view_reference(&src_view, NULL);
645 }
646
647 /* For MSAA integer resolving to work, we change the format to NORM using this function. */
648 static enum pipe_format int_to_norm_format(enum pipe_format format)
649 {
650 switch (format) {
651 #define REPLACE_FORMAT_SIGN(format,sign) \
652 case PIPE_FORMAT_##format##_##sign##INT: \
653 return PIPE_FORMAT_##format##_##sign##NORM
654 #define REPLACE_FORMAT(format) \
655 REPLACE_FORMAT_SIGN(format, U); \
656 REPLACE_FORMAT_SIGN(format, S)
657
658 REPLACE_FORMAT_SIGN(B10G10R10A2, U);
659 REPLACE_FORMAT(R8);
660 REPLACE_FORMAT(R8G8);
661 REPLACE_FORMAT(R8G8B8X8);
662 REPLACE_FORMAT(R8G8B8A8);
663 REPLACE_FORMAT(A8);
664 REPLACE_FORMAT(I8);
665 REPLACE_FORMAT(L8);
666 REPLACE_FORMAT(L8A8);
667 REPLACE_FORMAT(R16);
668 REPLACE_FORMAT(R16G16);
669 REPLACE_FORMAT(R16G16B16X16);
670 REPLACE_FORMAT(R16G16B16A16);
671 REPLACE_FORMAT(A16);
672 REPLACE_FORMAT(I16);
673 REPLACE_FORMAT(L16);
674 REPLACE_FORMAT(L16A16);
675
676 #undef REPLACE_FORMAT
677 #undef REPLACE_FORMAT_SIGN
678 default:
679 return format;
680 }
681 }
682
683 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
684 const struct pipe_blit_info *info)
685 {
686 struct si_context *sctx = (struct si_context*)ctx;
687 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
688 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
689 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
690 enum pipe_format format = int_to_norm_format(info->dst.format);
691 unsigned sample_mask = ~0;
692
693 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
694 * the format is R16G16. Use R16A16, which does work.
695 */
696 if (format == PIPE_FORMAT_R16G16_UNORM)
697 format = PIPE_FORMAT_R16A16_UNORM;
698 if (format == PIPE_FORMAT_R16G16_SNORM)
699 format = PIPE_FORMAT_R16A16_SNORM;
700
701 if (info->src.resource->nr_samples > 1 &&
702 info->dst.resource->nr_samples <= 1 &&
703 util_max_layer(info->src.resource, 0) == 0 &&
704 util_max_layer(info->dst.resource, info->dst.level) == 0 &&
705 info->dst.format == info->src.format &&
706 !util_format_is_pure_integer(format) &&
707 !util_format_is_depth_or_stencil(format) &&
708 !info->scissor_enable &&
709 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
710 dst_width == info->src.resource->width0 &&
711 dst_height == info->src.resource->height0 &&
712 info->dst.box.x == 0 &&
713 info->dst.box.y == 0 &&
714 info->dst.box.width == dst_width &&
715 info->dst.box.height == dst_height &&
716 info->dst.box.depth == 1 &&
717 info->src.box.x == 0 &&
718 info->src.box.y == 0 &&
719 info->src.box.width == dst_width &&
720 info->src.box.height == dst_height &&
721 info->src.box.depth == 1 &&
722 dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
723 !(dst->surface.flags & RADEON_SURF_SCANOUT) &&
724 (!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be fast-cleared */
725 !dst->dcc_offset) {
726 si_blitter_begin(ctx, SI_COLOR_RESOLVE |
727 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
728 util_blitter_custom_resolve_color(sctx->blitter,
729 info->dst.resource, info->dst.level,
730 info->dst.box.z,
731 info->src.resource, info->src.box.z,
732 sample_mask, sctx->custom_blend_resolve,
733 format);
734 si_blitter_end(ctx);
735 return true;
736 }
737 return false;
738 }
739
740 static void si_blit(struct pipe_context *ctx,
741 const struct pipe_blit_info *info)
742 {
743 struct si_context *sctx = (struct si_context*)ctx;
744
745 if (do_hardware_msaa_resolve(ctx, info)) {
746 return;
747 }
748
749 assert(util_blitter_is_blit_supported(sctx->blitter, info));
750
751 /* The driver doesn't decompress resources automatically while
752 * u_blitter is rendering. */
753 si_decompress_subresource(ctx, info->src.resource, info->src.level,
754 info->src.box.z,
755 info->src.box.z + info->src.box.depth - 1);
756
757 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
758 util_try_blit_via_copy_region(ctx, info))
759 return;
760
761 si_blitter_begin(ctx, SI_BLIT |
762 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
763 util_blitter_blit(sctx->blitter, info);
764 si_blitter_end(ctx);
765 }
766
767 static void si_flush_resource(struct pipe_context *ctx,
768 struct pipe_resource *res)
769 {
770 struct r600_texture *rtex = (struct r600_texture*)res;
771
772 assert(res->target != PIPE_BUFFER);
773
774 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
775 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
776 0, util_max_layer(res, 0), false);
777 }
778 }
779
780 static void si_decompress_dcc(struct pipe_context *ctx,
781 struct r600_texture *rtex)
782 {
783 if (!rtex->dcc_offset)
784 return;
785
786 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
787 0, util_max_layer(&rtex->resource.b.b, 0),
788 true);
789 }
790
791 static void si_pipe_clear_buffer(struct pipe_context *ctx,
792 struct pipe_resource *dst,
793 unsigned offset, unsigned size,
794 const void *clear_value_ptr,
795 int clear_value_size)
796 {
797 struct si_context *sctx = (struct si_context*)ctx;
798 uint32_t dword_value;
799 unsigned i;
800
801 assert(offset % clear_value_size == 0);
802 assert(size % clear_value_size == 0);
803
804 if (clear_value_size > 4) {
805 const uint32_t *u32 = clear_value_ptr;
806 bool clear_dword_duplicated = true;
807
808 /* See if we can lower large fills to dword fills. */
809 for (i = 1; i < clear_value_size / 4; i++)
810 if (u32[0] != u32[i]) {
811 clear_dword_duplicated = false;
812 break;
813 }
814
815 if (!clear_dword_duplicated) {
816 /* Use transform feedback for 64-bit, 96-bit, and
817 * 128-bit fills.
818 */
819 union pipe_color_union clear_value;
820
821 memcpy(&clear_value, clear_value_ptr, clear_value_size);
822 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
823 util_blitter_clear_buffer(sctx->blitter, dst, offset,
824 size, clear_value_size / 4,
825 &clear_value);
826 si_blitter_end(ctx);
827 return;
828 }
829 }
830
831 /* Expand the clear value to a dword. */
832 switch (clear_value_size) {
833 case 1:
834 dword_value = *(uint8_t*)clear_value_ptr;
835 dword_value |= (dword_value << 8) |
836 (dword_value << 16) |
837 (dword_value << 24);
838 break;
839 case 2:
840 dword_value = *(uint16_t*)clear_value_ptr;
841 dword_value |= dword_value << 16;
842 break;
843 default:
844 dword_value = *(uint32_t*)clear_value_ptr;
845 }
846
847 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value, false);
848 }
849
850 void si_init_blit_functions(struct si_context *sctx)
851 {
852 sctx->b.b.clear = si_clear;
853 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
854 sctx->b.b.clear_render_target = si_clear_render_target;
855 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
856 sctx->b.b.resource_copy_region = si_resource_copy_region;
857 sctx->b.b.blit = si_blit;
858 sctx->b.b.flush_resource = si_flush_resource;
859 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
860 sctx->b.decompress_dcc = si_decompress_dcc;
861 }